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austin <austin@xilinx.com> wrote: < A good paper was presented In Monterey FPGA conference 2009 from < Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom < processor before layout. < One of the things they talk about is how their ASIC standard cell/ < custom flow uses Latches for speed and power improvements (over the < use of edge triggered flip flops). < If you want to learn about why someone would use latches in an ASIC, I < suggest reading this paper. (snip) < http://www.ece.wisc.edu/~kati/fpga2009/index.html That seems to be the conference page, but I don't see a reference to the paper. Maybe directly from intel? -- glenArticle: 143551
glen herrmannsfeldt schrieb: > austin <austin@xilinx.com> wrote: > > < A good paper was presented In Monterey FPGA conference 2009 from > < Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom > < processor before layout. > > < One of the things they talk about is how their ASIC standard cell/ > < custom flow uses Latches for speed and power improvements (over the > < use of edge triggered flip flops). > > < If you want to learn about why someone would use latches in an ASIC, I > < suggest reading this paper. > > (snip) > > < http://www.ece.wisc.edu/~kati/fpga2009/index.html > > That seems to be the conference page, but I don't see a reference > to the paper. > > Maybe directly from intel? > > -- glen There's only one talk on this topic in this whole conference: Intel Atom Processor Core Made FPGA Synthesizable Perry Wang, Jamison Collins, Chris Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham Chinya, Ethan Schuchman, Oliver Schilling, Sebastian Steibl and Hong Wang Intel Corp., USA so hard to find??Article: 143552
Hello, Does anyone know how to contact Jerry Harthcock? Yours faithfully, Colin Paul GlosterArticle: 143553
Hello, Does anyone know of a softcore for either the Analog Devices ADSP-2191 or 2181 DSPs? Looks like the 2191's life is only 2 years and I need something that is code compatible with the 2181 DSP. Thanks!Article: 143554
SpiffyGuy <spiffyguy917@gmail.com> wrote in news:b486eb62-43f9-430b-9f62- d4805aa74916@j39g2000yqh.googlegroups.com: > Hello, > > Does anyone know of a softcore for either the Analog Devices ADSP-2191 > or 2181 DSPs? Looks like the 2191's life is only 2 years and I need > something that is code compatible with the 2181 DSP. > > Thanks! > I haven't heard that the 2191 is EOL, but it seems to me that it would be easier to port code to another DSP that try to duplicate it with a softcore. From strictly a MIPs and peripheral point of view, most of the Blackfin product line can serve the same purpose. From an assembly language perspective, I think it would be easier to port 218x or 219x code to the SHARC. The ADSP-21371 would be one possibility. It has all the peripherals of the 2191 and is much more powerful. It even costs less. I learned 218x and 219x code before I learned SHARC assembly. It was a very easy transition. Al Clark www.danvillesignal.comArticle: 143555
Error recurrence : just modify MAXPAYLOAD size in tb.v like this : `define MAXPAYLOAD 256 // choose 128, 256, 512, 1024, 2048, or 4096 When simulation, following error occurs: # Set MAX PAYLOAD and MAX READ REQUEST size to 256 # ----------------------------- # ** Changing FE config registers # 53636 64 DW read from address 0x00 # XILINX_PCIE_312 : TRANSMITTED UNSUPPORTED REQUEST # XILINX_PCIE_311 : RECEIVED UNSUPPORTED REQUEST COMPLETION # Checking 64 DW read from address 0x00 # 54412 Error: Packet Error in data ( 0) and ( 0) : 0x01001010000000000000000001000000 /= 0x00001010000000000000000000000000 # 54416 1 DW read from config address 0x68 # Read 4a000001 from rx_data_buffer[0] # Read 00000004 from rx_data_buffer[1] # Read 55000000 from rx_data_buffer[2] # Read 10280000 from rx_data_buffer[3] # New config data is 30180000 # 55176 1 DW write to config address 0x68 # Check if config write was successful # 55936 1 DW read from config address 0x68 # Read 4a000001 from rx_data_buffer[0] # Read 00000004 from rx_data_buffer[1] # Read 55000000 from rx_data_buffer[2] # Read 30180000 from rx_data_buffer[3] # ** Changing NE config registers # 56696 1 DW read from ne config address 0x68 # Read 4a000001 from rx_data_buffer[0] # Read 00000004 from rx_data_buffer[1] # Read 55000000 from rx_data_buffer[2] # Read 10280000 from rx_data_buffer[3] # New config data is 30180000 # 56808 1 DW write to ne config address 0x68 # Check if config write was successful # 56932 1 DW read from ne config address 0x68 # Read 4a000001 from rx_data_buffer[0] # Read 00000004 from rx_data_buffer[1] # Read 55000000 from rx_data_buffer[2] # Read 30180000 from rx_data_buffer[3] # 57056 1 DW write to config address 0x10 # BAR0 is 0xff4ffc00 Even if I use "memory_read" task in other place like: memory_read(11'd1, 32'hff4ffc10, G_TC_NUMBER, 4'hf, 4'h0); Modelsim will always report Packet Error like: Packet Error in data ( 0) and ( 0) : 0x01001010000000000000000001000000 /= 0x00001010000000000000000000000000 What is wrong with this task?Article: 143556
Target device is Virtex5 LX30TFF665-1, and my final design is very hard to acheving timing closure using ISE 10.1.3, which uses MIG2.3 DDR2 SDRAM interface and endpoint block plus for PCIe V1.9. Now I am considering migration to ISE 11.3. While I found that when I change MIG2.3 core to MIG3.2 and remains endpoint block plus with V1.9, ISE 11.3 could meet timing constraints, and the PAR output listed below: Phase 1 : 56169 unrouted; REAL time: 25 secs INFO:Route:538 - One or more MIG cores have been detected in your design and have been successfully placed and routed. All appropriate timing requirements have been met. Phase 2 : 48559 unrouted; REAL time: 31 secs Phase 3 : 14055 unrouted; REAL time: 1 mins 6 secs Phase 4 : 14125 unrouted; (Setup:581, Hold:112848, Component Switching Limit:0) REAL time: 1 mins 16 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:887, Hold:106855, Component Switching Limit:0) REAL time: 1 mins 36 secs Phase 6 : 0 unrouted; (Setup:807, Hold:106855, Component Switching Limit:0) REAL time: 1 mins 41 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 7 : 0 unrouted; (Setup:804, Hold:106855, Component Switching Limit:0) REAL time: 2 mins 36 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 8 : 0 unrouted; (Setup:449, Hold:106855, Component Switching Limit:0) REAL time: 2 mins 54 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 9 : 0 unrouted; (Setup:86, Hold:106779, Component Switching Limit:0) REAL time: 6 mins 19 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 10 : 0 unrouted; (Setup:86, Hold:106779, Component Switching Limit:0) REAL time: 6 mins 25 secs Phase 11 : 0 unrouted; (Setup:86, Hold:0, Component Switching Limit:0) REAL time: 6 mins 30 secs Phase 12 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 35 secs Total REAL time to Router completion: 6 mins 35 secs Total CPU time to Router completion: 6 mins 17 secs Now I upgrade the endpoint block plus core to V1.12. I use command script to synthesis V1.12 source code first, and use the produced ngc file as what I did in V1.9 in rest ISE flow. Other source files and ISE settings remain the same compared to the before one. However achieving timing closure is very hard: Phase 1 : 56043 unrouted; REAL time: 25 secs INFO:Route:538 - One or more MIG cores have been detected in your design and have been successfully placed and routed. All appropriate timing requirements have been met. Phase 2 : 48382 unrouted; REAL time: 30 secs Phase 3 : 14005 unrouted; REAL time: 1 mins 4 secs Phase 4 : 14078 unrouted; (Setup:15845, Hold:113648, Component Switching Limit:0) REAL time: 1 mins 12 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:15119, Hold:104343, Component Switching Limit:0) REAL time: 1 mins 31 secs Phase 6 : 0 unrouted; (Setup:7535, Hold:104347, Component Switching Limit:0) REAL time: 1 mins 37 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 7 : 0 unrouted; (Setup:6477, Hold:102653, Component Switching Limit:0) REAL time: 2 mins 22 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 8 : 0 unrouted; (Setup:6477, Hold:102653, Component Switching Limit:0) REAL time: 2 mins 31 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 9 : 0 unrouted; (Setup:175, Hold:95558, Component Switching Limit:0) REAL time: 9 mins 11 secs Updating file: pcie_dma_top.ncd with current fully routed design. Phase 10 : 0 unrouted; (Setup:175, Hold:95558, Component Switching Limit:0) REAL time: 9 mins 17 secs Phase 11 : 0 unrouted; (Setup:175, Hold:0, Component Switching Limit: 0) REAL time: 9 mins 24 secs Phase 12 : 0 unrouted; (Setup:58, Hold:0, Component Switching Limit:0) REAL time: 9 mins 29 secs Total REAL time to Router completion: 9 mins 29 secs Total CPU time to Router completion: 8 mins 55 secs The endpoint block plus core V1.12 synthesis report is uploaded in the attachment. I think there may be some mistakes in my PCIe core XST synthesis procedure, or there is indeed a performance regression in V1.12 compared to V1.9 ?Article: 143557
What is the purpose of releasing the source code? For better implement results? And when I use modelsim to run functional simulation, the following error occurs: # vsim -L secureip -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps tb glbl # ** Note: (vsim-3812) Design is being optimized... # ** Error: ../../ip_cores/pcie_mig/endpoint_blk_plus_v1_12/source/ pcie_top.v(1405): Module parameter 'REF_CLK_FREQ' not found for override. # Optimization failed # Error loading design I really don't find anything good with this change, and it indeed affects the migration to ISE 11.3Article: 143558
austin <austin@xilinx.com> schrieb:
> Fabian,
Hi Austin,
> Does your partial bitstream include the FSM registers? If it does, it
> will also contain initial conditions for these DFF.
Yep, the partial bitstream contains more than 5 FSMs, all have initial states
defined in the declaration.
> There is also the question of reconfiguring while the design is
> running: if there is a block RAM in your design (BRAM), it only has
> two ports that may be used simultaneously -- the configuration
> interface can not be used while the BRAM is being clocked (it will
> lead to data corruption in the BRAM).
Acctually we do reconfigure the running design. ATM we do not care about
corrupted data. The problem is, the FSMs do sometimes just stop after reconf.
and sometimes there continue running perfectly.
> The same may be true of the logic, in that the DFF used for the FSM
> can not be clocked while you are reconfiguring if they get inputs from
> the reconfigurable section, or are inside the reconfigurable section.
I do not completly understand what you mean. My FSMs are within the dynamic
part. the only connection between base/static part and dynamic part are FIFOs.
|---------| |---------|
| Base |->TXFIFO->| dynamic |
| design | | part |
| |<-RXFIFO<-| (FSMs) |
|---------| |---------|
--
best regards
-- Fabian Schuh
Article: 143559On Oct 15, 5:56=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > jay <heavenf...@gmail.com> wrote: > <> jay wrote: > > <> > The design mostly used latches, I'm unlucky. > (big snip) > > < The ASIC was designed so long ago that it was written by a proprietary > < HDL code, it will take lots man-months to rewrite it. > < It has a post-layout Verilog netlist with foundry library models for > < simulation, I have created all the libraries (gates, Latches, FFs, > < multipliers, memories) using Verilog RTL, so get a gate level > < synthesizable design. > > Yes, that is what I would expect. > > < What I'm thinking now is to replace Latch instance with FF > < instance in the design like below: > > < latch_cell latch_inst1 (.o(o), .i(i), .en(en)) to ff_cell ff_inst1 (.o > < (o), .i(i), .en(en), .clk(clk)) > > It would depend somewhat on the design, but my first thought > is that you just use (en) as the clock. =A0(or ~en depending on > rising edge or falling edge.) > > Does the design have a two phase clock? > > Does the signal flow go: > > (latch on phase 1) (gates) (latch on phase 2) (gates) (repeat as needed) > > In that case, you should be able to replace them all by edge > triggered FFs and run the clock twice as fast. =A0 > > How old is this design? > > < So it may fit into a FPGA better, I just need get a high speed clock > < (120MHz) to every modules, and write a script to convert all latch > < instances through the design. > > < My concern is 120MHz is fast enough for a low cost FPGA that I will > < get lots of setup time problems then... > > -- glen Hi Glen, I don't think I can replace Latch with FF that easy, the design intended to use Latch, changing the trigger from level to edge will change the registers behavior. The latest version of this ASIC was taped out about 10 years ago, it's probably the 3rd generation of it's family. I don't know when the design was initiated, should in the days when Latch uses less transistors than FF. JayArticle: 143560
On 2009-10-15, rickman <gnuarm@gmail.com> wrote: > Did you give them your email address? Is this spam or you just don't > like the fact that it is much harder for them to meet the regulations > of dozens of countries than it is to only make the offer in the single > country where most of their business comes from? On a related note: is it possible Xilinx is giving out mail addresses to other companies? I use separate disposable mail addresses for each web registration, and I just got spam from a Mentor Graphics user group, sent to the mail address that I only used at xilinx.com. Guess I'll have to disable that account on my mail server. cu MichaelArticle: 143561
On 15 Oct, 16:37, rickman <gnu...@gmail.com> wrote: > On Oct 13, 8:12=A0am, "colin_toog...@yahoo.com" > > > > > > <colin_toog...@yahoo.com> wrote: > > On 13 Oct, 11:52, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > colin <colin_toog...@yahoo.com> writes: > > > > I'm trying to implement a simple CLI so that I can do some debuggin= g. > > > > I have a microblaze license but I've just taken a look at it and > > > > sledgehammers and nuts come to mind. I then took a look on opencore= s > > > > and nothing seems quite finished enough (and few with a C compiler)= . > > > > > Does anyone have a suggestion? > > > > Picoblaze (but that's assembly only..) > > > > If you can fit a sledgehammer (sorry, microblaze :) in, why not use i= t? > > > What is it you're trying to do - just wiggle some port pins, or > > > something more complex? > > > > If it's slow pin/signal wiggling, and alternative might be to use > > > Chipscope's VIO block - it's not CLI, but I gather it has some tcl > > > libraries which you could build something with... > > > > Cheers, > > > Martin > > > > -- > > > martin.j.thomp...@trw.com > > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp= ://www.conekt.net/electronics.html > > > Martin > > > Your right, using the VIO block answers the question I posted. I need > > to read/write a dozen 32 bit registers. However I ultimately want a > > processor at the outermost control loop. I will take a look at using > > chipscope for debugging and the Picoblaze at the outer loop. Cludgy in > > the short term but ultimately quite elegant. > > > Colin > > I have some reservations about it, but I would say you might want to > look at the ZPU. =A0I am not a software person anymore, so I think very > differently than those guys, but they seem to have caught on and > recently I read that National Semi has released some sort of eval > board that is using the ZPU in an FPGA. =A0It is supported by a C > compiler and can get down to something well under 1000 LUTs, perhaps > as low as 600 I think. =A0It's not so fast at that size, but should be > plenty fast enough for a CLI (I had to google CLI to figure out what > that meant). > > Another option is one of the two processors from Lattice. =A0I have > never read the license in enough detail to actually understand it (I > am not a lawyer, thank god) but it is supposed to be open source. =A0I > don't know if that is the same as freely usable, but I'm pretty sure > you don't have to use it in their parts. =A0They have a Micro8 similar > to the Picoblaze and a 32 bit CPU like the uBlaze. > > If you are interested in using Forth (it comes with the CLI) there are > a number of processors to choose from including my own. =A0But I have > never completed the compiler so it is assembly only. =A0Even if that is > very forth like, it is not a forth compiler. > > Rick Rick The ZPU does look like one of the better projects on opencores. It is of course at the bottom of the opencores list and I was getting fed up looking at lots of half completed projects. Thanks for pointing me at it, I will google GIT later today and have a good look at it. Maybe I will register at lattice and take a look there as well. Sorry for yet another TLA :-) It is a term my colleagues at several companies have used throughout my 20 year career. Many thanks ColinArticle: 143562
I am trying to simulate in Modelsim XE web edition a verilog only project consisting of top level and few components. All components have same time resolution units and have wire type outputs. The problem is that Modelsim doesn't recognise the drive of any component's output connected to another's input. Yet it accepts the drive when connected to an output at toplevel itself. What am I missing here? Is there anything else to do about binding? Any help appreciated. This problem does not occur with vhdl projects. kadhiem --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143563
On Thu, 15 Oct 2009 23:14:49 -0700 (PDT), vcar <hitsx@163.com> wrote: >Target device is Virtex5 LX30TFF665-1, and my final design is very >hard to acheving timing closure using ISE 10.1.3, which uses MIG2.3 >DDR2 SDRAM interface and endpoint block plus for PCIe V1.9. > >Phase 12 : 0 unrouted; (Setup:58, Hold:0, Component Switching Limit:0) >REAL time: 9 mins 29 secs >Total REAL time to Router completion: 9 mins 29 secs >Total CPU time to Router completion: 8 mins 55 secs If it's this close to working, try re-running MAP and PAR with a different seed. (MAP and PAR need the same seed as each other). This changes the placement, and may or may not offer better routing. You may need to try three or your different seeds. Small perturbations to the original design often have the same effect on MAP/PAR. - BrianArticle: 143564
When using PCIe Core V1.9: Phase 4 : 14125 unrouted; (Setup:581, Hold:112848, Component Switching Limit:0) REAL time: 1 mins 16 secs When using PCIe Core V1.12: Phase 4 : 14078 unrouted; (Setup:15845, Hold:113648, Component Switching Limit:0) REAL time: 1 mins 12 secs I think it is not a simple timing closure problem. There must be something wrong with my generated V1.12 core. However I uses the XST script provided by Xilinx, and I do not know where the problem is.Article: 143565
jay <heavenfish@gmail.com> wrote: < On Oct 15, 5:56?pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: <> jay <heavenf...@gmail.com> wrote: <> <> jay wrote: <> <> > The design mostly used latches, I'm unlucky. <> (big snip) (snip) <> < What I'm thinking now is to replace Latch instance with FF <> < instance in the design like below: <> < latch_cell latch_inst1 (.o(o), .i(i), .en(en)) to ff_cell ff_inst1 (.o <> < (o), .i(i), .en(en), .clk(clk)) <> It would depend somewhat on the design, but my first thought <> is that you just use (en) as the clock. ?(or ~en depending on <> rising edge or falling edge.) <> Does the design have a two phase clock? <> Does the signal flow go: <> (latch on phase 1) (gates) (latch on phase 2) (gates) (repeat as needed) <> In that case, you should be able to replace them all by edge <> triggered FFs and run the clock twice as fast. ? I had forgetten your original question, which was about a three phase clock. The big advantage of edge triggered FF's is the need for only a single clock. What actually has to happen is that, internally to each FF, a two phase clock is generated to clock separately the two halves of the FF, such that the input can be latched before the output changes. With an edge triggered FF, the timing requirement is that the input must have settled to the appropriate value by the next clock edge minus the setup time for that FF. It must not change before the clock edge plus the hold time. Most logic now has zero hold time, and a setup time sufficiently small that you don't have to worry about it. (The tools will do that for you, but propagation delay is much larger.) Using transparent latches requires a two (or more) phase clock such that the delay between FF states is less than the time from the rising edge of one to the falling edge of the next, minus the propagation delay for the latch itself. Clock skew subtracts from the time that you can allow, as one edge may come earlier than expected. If you replace the latches with rising edge FF's then the delay has to be less than the time between the rising edge of one and the rising edge of the next. If you replace transparent latches with edge triggered FF's, and if the clock is slow enough, the design should still work. Much of the complication of designing an FPGA is in clock distribution such that the user (you) doesn't have to worry about clock skew. The tools can compute the maximum delay from one FF output to the next input, add the allowable clock skew, and guarantee that the FF input is stable in time. With zero hold time, even after allowing for clock skew, you never need to worry about logic being too fast. <> How old is this design? <> < So it may fit into a FPGA better, I just need get a high speed clock <> < (120MHz) to every modules, and write a script to convert all latch <> < instances through the design. <> < My concern is 120MHz is fast enough for a low cost FPGA that I will <> < get lots of setup time problems then... I believe that your biggest problem is clock skew. < I don't think I can replace Latch with FF that easy, the design < intended to use Latch, changing the trigger from level to edge will < change the registers behavior. If you can verify that the logic works as I described, three phases and the appropriate amount of logic between each phase, then, with the appropriate clock speed it should work. Part of my previous suggestion included inverting every other phase such that you had the time from the rising edge of one to the falling edge of the next. That only works with an even number of phases. With transparent latches and using the general routing fabric for clock distribution I believe that the clock skew will be large enough that the timing will be worse. That depends on the specific FPGA, how the clock distribution works, and such. Also, the tools may or may not be able to do the timing calculation for you. < The latest version of this ASIC was taped out about 10 years ago, it's < probably the 3rd generation of it's family. I don't know when the < design was initiated, should in the days when Latch uses less < transistors than FF. Well, yes, but the complications of distributing three clock phases have to be added in. As logic gets faster, clock skew becomes more singificant. I do remember someone trying to design with the original TMS9900 with a four phase clock. I don't know of a commercial microprocessor using a three phase clock, though it is hard to know now. All the clock generation is done on chip on the high end processors. -- glenArticle: 143566
Fabian Schuh <usenet@xeroc.org> wrote: > austin <austin@xilinx.com> schrieb: >> Does your partial bitstream include the FSM registers? If it does, it >> will also contain initial conditions for these DFF. > Yep, the partial bitstream contains more than 5 FSMs, all have > initial states defined in the declaration. (snip) > Acctually we do reconfigure the running design. ATM we do not care about > corrupted data. The problem is, the FSMs do sometimes just stop after reconf. > and sometimes there continue running perfectly. Make sure that you FSM can get out of any illegal state that it happens to get itself into. I presume you allow a sufficient number of clock cycles after reconfiguration, but if the FSM is stable in states that it isn't supposed to ever get to, then no delay will be long enough. -- glenArticle: 143567
glen herrmannsfeldt <gah@ugcs.caltech.edu> schrieb:
> Make sure that you FSM can get out of any illegal state that
> it happens to get itself into. I presume you allow a sufficient
> number of clock cycles after reconfiguration, but if the FSM is
> stable in states that it isn't supposed to ever get to, then
> no delay will be long enough.
Hi glen,
All my FSM do have the
----------------------
when others=>
state <= idle;
----------------------
Is this enough? I thought so.
Just started implementing a wait counter to reset the FSM for some clockclycles
before starting the FSMs. Gonna test, if it helps.
Is there some good way to get an FSM into a defined state, if it runs into an
illegal one?
--
best regards
-- Fabian Schuh
Article: 143568Fabian Schuh <usenet@xeroc.org> wrote: < glen herrmannsfeldt <gah@ugcs.caltech.edu> schrieb: <> Make sure that you FSM can get out of any illegal state that <> it happens to get itself into. I presume you allow a sufficient <> number of clock cycles after reconfiguration, but if the FSM is <> stable in states that it isn't supposed to ever get to, then <> no delay will be long enough. < All my FSM do have the < ---------------------- < when others=> < state <= idle; < ---------------------- < Is this enough? I thought so. That sounds right to me. Though that doesn't guarantee that it works in all legal states. Some years ago (should be fixed now) I ran into some tools that internally converted my state machine to a 'one hot' form. The problem was that I used the state counter in external logic. The tools were supposed to recognize that, but missed it in my case. -- glenArticle: 143569
On Oct 16, 6:45=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Fabian Schuh <use...@xeroc.org> wrote: > > < glen herrmannsfeldt <g...@ugcs.caltech.edu> schrieb: > > <> Make sure that you FSM can get out of any illegal state that > <> it happens to get itself into. =A0I presume you allow a sufficient > <> number of clock cycles after reconfiguration, but if the FSM is > <> stable in states that it isn't supposed to ever get to, then > <> no delay will be long enough. > > < All my FSM do have the > < =A0 =A0 =A0 =A0---------------------- > < =A0 =A0 =A0 =A0when others=3D> > < =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0state <=3D idle; > < =A0 =A0 =A0 =A0---------------------- > < Is this enough? I thought so. > > That sounds right to me. > > Though that doesn't guarantee that it works in all legal states. =A0 > > Some years ago (should be fixed now) I ran into some tools that > internally converted my state machine to a 'one hot' form. > The problem was that I used the state counter in external logic. > The tools were supposed to recognize that, but missed it in > my case. =A0 > > -- glen Xilinx XST ALWAYS encodes state machines one-hot unless you force it to use your encoding (see synthesis options). Are you sure that your dynamic portion has a reset term for starting up the FSM logic? One of my favorite approaches is to add a post-reset state that just continues onto the idle state. Then when reset is released all of the states other than idle cannot be reached until the post-reset state has become inactive, effectively a synchronous reset release. Regards, GaborArticle: 143570
On Oct 15, 12:26=A0pm, he <nova...@ddres.se> wrote:
> glen herrmannsfeldt schrieb:
>
>
>
>
>
> > austin <aus...@xilinx.com> wrote:
>
> > < A good paper was presented In Monterey FPGA conference 2009 from
> > < Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom
> > < processor before layout.
>
> > < One of the things they talk about is how their ASIC standard cell/
> > < custom flow uses Latches for speed and power improvements (over the
> > < use of edge triggered flip flops).
>
> > < If you want to learn about why someone would use latches in an ASIC, =
I
> > < suggest reading this paper.
>
> > (snip)
>
> > <http://www.ece.wisc.edu/~kati/fpga2009/index.html
>
> > That seems to be the conference page, but I don't see a reference
> > to the paper.
>
> > Maybe directly from intel?
>
> > -- glen
>
> There's only one talk on this topic in this whole conference:
>
> Intel Atom Processor Core Made FPGA Synthesizable
> Perry Wang, Jamison Collins, Chris Weaver, Belliappa Kuttanna, Shahram
> Salamian, Gautham Chinya, Ethan Schuchman, Oliver Schilling, Sebastian
> Steibl and Hong Wang
> Intel Corp., USA
>
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Hi,
I am really interested in the theoritic bases of how a latch circuit
can replace a flip-flop to save power and how to calculate the set-up
time, hold time, keeping output data unfloating and so on.
I used "latch" as keyword and "Intel" as assignee to search through
google and get the following tables.
If you are interested as I am, help look in the following patent lists
which patent Intel discloses its secret. The patent filed time from
1991 to 2009.
Weng
Optimizing clock crossing and data path latency
US Pat. 7590789 - Filed Dec 7, 2007 - Intel Corporation
... the state machine and to generate a load reference signal to
provide to the
data buffer to enable a clock controller of the data buffer to latch
the ...
Controlling transmission on an asynchronous bus
US Pat. 7590788 - Filed Oct 29, 2007 - Intel Corporation
The apparatus of claim 2, wherein the two-phase register includes a
first latch
and a second latch to receive the data and 35 to pass ...
[APPLICATION] Memory Array with Psedudo Single Bit Memory Cell and
Method
US Pat. 11834947 - Filed Aug 7, 2007 - INTEL CORPORATION
Then, if the sensing bus trips in the 3rd Sensing (cell Vt<PSBC
specific R3
wordline level), the post sensing will latch the multi bit Count
signal as "10",
...
[APPLICATION] Electromagnetic Coupler Registration and Mating
US Pat. 11771991 - Filed Jun 29, 2007 - INTEL CORPORATION
20-, arms 730 and 740 each include an upright guide 732 and 742,
respectively,
and a latch 734 and 744, respectively. [0106] Upright guides 732 and
742 each
...
Clock jitter detector
US Pat. 7587650 - Filed Dec 8, 2006 - Intel Corporation
During subsequent periods of operation, the reset input R of the
latches 350 may
be maintained at logic 0 and each latch 350-1 to 350-7 may transfer a
logic ...
[APPLICATION] MEMORY DEVICE, CIRCUITS AND METHODS FOR READING A MEMORY
DEVICE
US Pat. 11561972 - Filed Nov 21, 2006 - Intel Corporation
A device according to claim 4, further comprising a latch operable to
establish
a data value dependent upon the output of the comparator. 6. ...
Memory channel with unidirectional links
US Pat. 7343458 - Filed Nov 15, 2006 - Intel Corporation
10 15 serializer so that the transmit latch clocks the read data out
of the I/O
cell in response to the transmit clock signal ...
High speed comparator offset correction
US Pat. 7362246 - Filed Sep 8, 2006 - Intel Corporation
... latch 120, control logic 130, registers 140, and offset canceling
buffer 180
. Analog comparator 110 operates to 60 compare voltages present on
input ...
Serially sensing the output of multilevel cell arrays
US Pat. 7304889 - Filed Jul 26, 2006 - Intel Corporation
6 Claims, 6 Drawing Sheets LATCH B-^ ...
Ultra-drowsy circuit
US Pat. 7236032 - Filed Jun 30, 2006 - Intel Corporation
Consequently, memory cells or elements of memory 110 and 112 may use
an ultra-
drowsy latch element implemented using an ultra-drowsy state retention
circuit
...
Clock error detection circuits, methods, and systems
US Pat. 7339403 - Filed Jun 29, 2006 - Intel Corporation
In this 50 positive feedback scenario, the cross-coupled inverters
latch an
output value on ... 3 shows a duty cycle detection circuit and an
output latch.
...
Startup/yank circuit for self-biased phase-locked loops
US Pat. 7265637 - Filed Jun 29, 2006 - Intel Corporation
The first path includes a divide-by-N counter 71 with an asynchronous
reset (R),
a D flip-flop 72, and an SR latch 73. The second path may be
similarly ...
Receiver latch circuit and method
US Pat. 7362153 - Filed May 1, 2006 - Intel Corporation
Partially gated mux-latch keeper
US Pat. 7436220 - Filed Mar 31, 2006 - Intel Corporation
Programmable multi-cycle signaling in integrated circuits
US Pat. 7239254 - Filed Mar 31, 2006 - Intel Corporation
The method of claim 10 further comprising determining which of the N
phases of
the single digital data stream to latch on each conductor based on a
logical ...
Apparatus to receive signals from electromagnetic coupler
US Pat. 7365532 - Filed Mar 31, 2006 - Intel Corporation
The apparatus of claim 4, wherein the adaptive feedback loop is to
latch the
output of the integrator device. 6. The apparatus of claim 4, ...
Current-balanced logic circuit
US Pat. 7368955 - Filed Mar 28, 2006 - Intel Corporation
... latch", Electronics Letters, Feb. 4,; vol. 35, No. 3, pp.-. Allam
et al., "
Dynamic Current Mode Logic ...
Method for configurably enabling pulse clock generation for
multiple ...
US Pat. 7276942 - Filed Feb 21, 2006 - Intel Corporation
As described earlier, 16 latch banks 26 are illustrated for the
embodiments, the
latch banks 26 divided into two groups of even and odd latch
banks, ...
High speed DRAM cache architecture
US Pat. 7350016 - Filed Jan 10, 2006 - Intel Corporation
A de-multiplexer 430 sends the row address portion to a row address
latch 435
and a set of memory banks 455-1 to 455-N. The row lines of the memory
array ...
Fine granularity DRAM refresh
US Pat. 7221609 - Filed Dec 28, 2005 - Intel Corporation
In one embodiment, a 10 DRAM device (or bank) 300 is shown including
row latch
and decode circuitry, column decode circuitry, data path sending
and ...
Memory with spatially encoded data storage
US Pat. 7372763 - Filed Dec 28, 2005 - Intel Corporation
I FIGURE Delay Element Equally Distributed 'Os/' Is Delay Element Edge
Triggered
Latch To Write Driver ...
Multi-loop circuit capable of providing a delayed clock in phase
locked loops
US Pat. 7184503 - Filed Dec 15, 2005 - Intel Corporation
... latch.
Polarity driven dynamic on-die termination
US Pat. 7372293 - Filed Dec 7, 2005 - Intel Corporation
In some embodiments, control logic 240 may recognize and latch each of
the
different ... The latch(es) may stay set for a defined period of time
(eg, ...
Dynamic on-die termination launch latency reduction
US Pat. 7342411 - Filed Dec 7, 2005 - Intel Corporation
In 5 some embodiments, ODT activation logic 242 includes latch 246.
Latch 246
recognizes and latches ODT activation signals that are received on ODT
pin 238
...
List based method and apparatus for selective and rapid cache flushes
US Pat. 7266647 - Filed Nov 15, 2005 - Intel Corporation
Start Flush Generate Set Address 26 28 List Structure 56 32 Evict,
Latch Address
and Data All Lines Done? 42 End Flush Fig. ...
Integrated socket and cable connector
US Pat. 7244137 - Filed Oct 20, 2005 - Intel Corporation
The integrated socket 900 may further include a cable latch or lid
902, which
may snap down to connect the cable 310 to the integrated socket 900
T .. ...
Load adaptive power converter
US Pat. 7368897 - Filed Oct 7, 2005 - Intel Corporation
The latch SRI higher than the steady state switching frequency of the
CCM 20 is
set again at the next switching cycle by the OR-gate. The mode). ...
Write pointer error recovery systems and methods
US Pat. 7106633 - Filed Oct 3, 2005 - Intel Corporation
The buffer circuits 10A and 10C-10H may latch the data into address
(bit ...
However, buffer circuit 10B may not latch the data, so the data in
that bit ...
Method and system for a fast serial transmit equalization scheme
US Pat. 7126987 - Filed Sep 6, 2005 - Intel Corporation
A parallel bus includes, for 25 example, a group of data lines and a
clock, in
which the clock is transmitted along with the data in order to latch
in the ...
Scan friendly domino exit and domino entry sequential circuits
US Pat. 7227384 - Filed Aug 11, 2005 - Intel Corporation
The circuit of claim 23, wherein the latch is responsive to a high to
low clock
transition. 10 15 14 25. The circuit of claim 23, wherein the
latch ...
Serially sensing the output of multilevel cell arrays
US Pat. 7106626 - Filed Aug 3, 2005 - Intel Corporation
... LATCH ...
System and method for performing adaptive phase equalization
US Pat. 7590173 - Filed Jun 30, 2005 - Intel Corporation
... OFFSET CIRCUIT OUTBOUND MUX LATCH ADAPTIVE PHASE EQUALIZATION SIDE-
BAND
SIGNAL ... X 35 GLUT TRANSMIT TIMING ADJUSTMENT CIRCUIT 36 OUTBOUND
MUX LATCH
...
Memory array with pseudo single bit memory cell and method
US Pat. 7272041 - Filed Jun 30, 2005 - Intel Corporation
Then, if the sensing bus trips in the 3rd Sensing (cell Vt<PSBC
specific R3
wordline level), the post sensing will latch the multi bit Count
signal as "10",
...
Interpolator circuit
US Pat. 7102404 - Filed Jun 30, 2005 - Intel Corporation
Timing system 900 includes signal sources 910 and 915, latch 925, and
delay-
locked loop 920, ... Signal source 910 provides data signal DQ to
latch 925. ...
Performing multiple read operations via a single read command
US Pat. 7319612 - Filed May 18, 2005 - Intel Corporation
... with latch JI Ly Volat Word address le Array ...
System pulse latch and shadow pulse latch coupled to output joining
circuit
US Pat. 7373572 - Filed May 12, 2005 - Intel Corporation
In a capture operation, the hardening/scan cells 80 may function to
latch (
capture) the system response. In a scan-out shift operation, the
system response
...
Memory device, circuits and methods for operating a memory device
US Pat. 7161825 - Filed May 9, 2005 - Intel Corporation
Optional I/O data-latch & multiplexer 72 may capture data from sense
amplifiers
that may be held for subsequent retrieval. For 20 example, if the bit-
width ...
Yank detection circuit for self-biased phase locked loops
US Pat. 7095289 - Filed May 5, 2005 - Intel Corporation
The first path includes a divide-by-N counter 71 with an asynchronous
reset (R),
a D flip-flop 72, and an SR latch 50 73. The second path may be
similarly ...
Ferroelectric memory input/output apparatus
US Pat. 7082047 - Filed Apr 18, 2005 - Intel Corporation
However, the order of the data out latched using the address latch
shown in FIG.
3. on the data bus is flexible. A half cycle after the memory
device ...
Folding latching mechanism
US Pat. 7292457 - Filed Mar 31, 2005 - Intel Corporation
An embodiment of the folding latching mechanism includes a latch
member having
... A lever arm is pivotally-coupled to the latch member about a
second pivot
...
Pull lever latch apparatus
US Pat. 7083449 - Filed Mar 29, 2005 - Intel Corporation
Pull ...
Airflow redistribution device
US Pat. 7215552 - Filed Mar 23, 2005 - Intel Corporation
The 40 connection device 340 may be any type of apparatus (eg, clip,
hook, latch
) that would provide ...
Ferroelectric memory device and method of reading a ferroelectric
memory
US Pat. 7113419 - Filed Mar 21, 2005 - Intel Corporation
In accordance with an alternative exemplary embodiment, a known data
latch is
configured between, or as a part of Regarding the voltage levels, for
example,
...
Electromagnetic coupler registration and mating
US Pat. 7252537 - Filed Feb 3, 2005 - Intel Corporation
20-25, arms 730 and 740 each include an upright 35 guide 732 and 742,
respectively, and a latch 734 and 744, respectively. Upright guides
732 and 742
each ...
System and scanout circuits with error resilience circuit
US Pat. 7278076 - Filed Feb 4, 2005 - Intel Corporation
... latch ...
Speed-locked loop to provide speed information based on die operating
conditions
US Pat. 7123066 - Filed Jan 31, 2005 - Intel Corporation
For another embodiment SLL, 4 The die as set forth in claim 3, wherein
the speed
- latch 220 may be controlled so as to latch onto the smaller ...
Low-swing level shifter
US Pat. 7215173 - Filed Jan 31, 2005 - Intel Corporation
The level shifter 400 is useful in circuits which are implemented
using CML
logic. FIG. 5 illustrates an exemplary CML D-latch 500. ...
System and shadow circuits with output joining circuit
US Pat. 7278074 - Filed Jan 26, 2005 - Intel Corporation
... functional mode of operation and to generate a first shadow latch
test
output signal in response to a scan-in signal and a first scan clock
signal; ...
Method and apparatus for processing an event occurrence within a ...
US Pat. 7353370 - Filed Jan 20, 2005 - Intel Corporation
204 for each thread are set by the event detector 188 that Events are
communicated directly to the event detector triggers a latch which
sets the ...
Circuit and method for protecting vector tags in high performance ...
US Pat. 7315920 - Filed Jan 4, 2005 - Intel Corporation
In addition, if any of the bits of a cleared cell in the rows contain
a "1",
then the latch 344 can be set via w!3. In the second clock cycle the
enable bit
...
Reading phase change memories to reduce read disturbs
US Pat. 7259982 - Filed Jan 5, 2005 - Intel Corporation
2C is a theoretical depiction of the read strobe data latch voltage
versus time
in accordance with one embodiment of the present invention without
using ...
Circuit board latch system
US Pat. 7209364 - Filed Dec 29, 2004 - Intel Corporation
A system according to claim 1, wherein said knob and said at least one
latch are
disposed on said faceplate. 3. A system according to claim 1 wherein
said ...
Method and apparatus to read information from a content addressable
memory ...
US Pat. 7151682 - Filed Dec 22, 2004 - Intel Corporation
A nonvolatile memory, comprising a first content addressable memory
(CAM) cell,
wherein the first CAM cell comprises a latch to store volatile
binary ...
Detecting a current with a sensor having a wheatsone bridge
US Pat. 7064569 - Filed Dec 14, 2004 - Intel Corporation
The output of the blow timer (U1B) is connected to the cut out latch
(U1C), ....
The cutout latch (U1C) latches the over current comparator (U1A) until
a ...
Systems and methods for an improved card-edge connector
US Pat. 7029307 - Filed Dec 14, 2004 - Intel Corporation
A portion of the moveable retention mechanism 530 may, for example,
latch onto a
detent 564 such as the semi-circular cutouts shown in FIG. 5. ...
Network communications system
US Pat. 7038138 - Filed Dec 7, 2004 - Intel Corporation
The resilient tab 144 carries an outwardly projecting latch 146 that
engages the
top of the abutment 118 on the top of the associated cable 50
dispenser 82 ...
Amplifier apparatus, method, and system
US Pat. 7019592 - Filed Nov 12, 2004 - Intel Corporation
Integrated circuit 620 may utilize the clock signal received by clock
receiver
622 to latch data received by data receiver 624. For example, clock
receiver ...
Circuit for producing a variable frequency clock signal having a
high ...
US Pat. 7272534 - Filed Nov 10, 2004 - Intel Corporation
In an embodiment, the multiplexer 50 switch 106 output 142 is sampled
by using
the output 142 as an input to a resettable latch (not shown). ...
System and apparatus for receiver equalization
US Pat. 7230489 - Filed Nov 1, 2004 - Intel Corporation
In some embodiments any self-biased amplifier or latch may be used. In
some
embodiments a circuit is used that makes improvements in high
frequency ...
On-die monitoring device power grid
US Pat. 7138816 - Filed Oct 26, 2004 - Intel Corporation
... and N latch circuits coupled to the N amplifiers to convert the N
comparison
result signals into the N comparison output signals, the N
comparison ...
Protected socket for integrated circuit devices
US Pat. 7316573 - Filed Oct 25, 2004 - Intel Corporation
... said package land contact terminals are engaged with said socket
leaf spring
contact terminals and wherein said socket is adapted to latch said
package ...
Insertion and ejection mechanisms for modular boards and cards
US Pat. 7245499 - Filed Sep 30, 2004 - Intel Corporation
In one embodiment, a built-in handle latch switch 614 must be
activated ... The
handle latch switch is used to detect whether a handle is latched or
not. ...
Apparatus for an electro-optical device connection
US Pat. 7373031 - Filed Sep 30, 2004 - Intel Corporation
9 is a plan view of the electro-optical connector cally, to an optical
fiber
connector with an integrated latch assembly similar to FIG. ...
Single to dual non-overlapping converter
US Pat. 7199665 - Filed Sep 29, 2004 - Intel Corporation
... and a first latch and a second latch coupled in series between the
input
node and the output node to pass a signal from the input node to the
output 3Q
...
Bitcell having a unity beta ratio
US Pat. 7154770 - Filed Sep 25, 2004 - Intel Corporation
... PC (57) ABSTRACT In one embodiment, the present invention includes
a memory
device formed of a latch device that includes a pair of pull-up
transistors ...
Optical fiber connector
US Pat. 7374349 - Filed Sep 10, 2004 - Intel Corporation
... the first end and to terminate proximate to the second end. The
connector
case is coupled to the connector body. The latch spring is coupled to
the ...
Decision feedback equalizer with bi-directional mode and lookup table
US Pat. 7170438 - Filed Sep 8, 2004 - Intel Corporation
7 may be referred to as an active cascode differential latch. ... When
clock
signal =A7 is HIGH, the differential latch is put into a pre-charge mode
where ...
Programming suspend status indicator for flash memory
US Pat. 7093064 - Filed Aug 25, 2004 - Intel Corporation
210 =99 f AND GATING 213 =A7 ^ BLOCK BLOCK 2 BLOCK X DECODING N < BLOCK
LOCK MINI-
ARRAY X DECODING ~T ADDRESS r 2J1 211 215 221 LATCH m 212 ...
Single ended current-sensed bus with novel static power free receiver
circuit
US Pat. 7196548 - Filed Aug 25, 2004 - Intel Corporation
As a result, substantially no current flowing through the latch
circuit (eg, M1-
M4) because the latch circuit has 35 been substantially isolated by
the SPDB ...
Hybrid CVSL pass-gate level-converting sequential circuit for multi-
Vcc ...
US Pat. 7132856 - Filed Aug 25, 2004 - Intel Corporation
The logic circuit may be a flip-flop circuit, a latch circuit, or
another type
of circuit. 20 Claims, 9 Drawing Sheets ...
Method and apparatus for detecting and recovering from errors in a
source ...
US Pat. 7343528 - Filed Aug 6, 2004 - Intel Corporation
The latch 640 is also configured 6. The apparatus of claim 5 wherein
said bus
... The latch 640 generates a reset when there ^3 signals; are no
further ...
[APPLICATION] Two-latch clocked-LSSD flip-flop
US Pat. 10909382 - Filed Aug 3, 2004 - Intel Corporation
TWO-LATCH CLOCKED-LSSD FLIP-FLOP BACKGROUND OF THE INVENTION [0001] It
is
possible to build test hardware into integrated circuit devices, to
ease
automated ...
Buffer for a split cache line access
US Pat. 6862225 - Filed Jul 23, 2004 - Intel Corporation
2 shows the differential driver circuit 130 coupled to the cache
memory 110, the
first and second sense amplifiers 120 and 160, the latch 140, and the
split ...
Technique to create link determinism
US Pat. 7328359 - Filed Jul 21, 2004 - Intel Corporation
The strobe signals are used to latch data into a source synchronous
agent
whenever data is transmitted between the agents. For agents using a
common clock
...
Network processor with content addressable memory (CAM) mask
US Pat. 7281083 - Filed Jun 30, 2004 - Intel Corporation
... TAG LATCH =97 / =AB =BB =AB BANK SELECT b 1 STATUS 1- CAM ...
Error detecting circuit
US Pat. 7188284 - Filed Jun 30, 2004 - Intel Corporation
The apparatus according to claim 23, wherein the datapath circuit
includes a
master datapath latch and a slave datapath latch coupled to the master
datapath
...
Interconnect structure in integrated circuits
US Pat. 7326972 - Filed Jun 30, 2004 - Intel Corporation
The device of claim 10 further comprising at least one latch coupled
between two
of the drive units of one of the first and second circuit paths, ...
Flash memory with coarse/fine gate step programming
US Pat. 7057934 - Filed Jun 29, 2004 - Intel Corporation
This causes the input to OR gate 404 to transition high, and causes
register 410
to latch a "1," and assert the coarse pass signal. ...
Scan enabled storage device
US Pat. 7139951 - Filed Jun 29, 2004 - Intel Corporation
Latch 540 includes cross-coupled inverters 542 and 544. Signal node
517, when
driven with data by either data input circuit 510 or scan data input
circuit ...
Clocked cycle latch circuit
US Pat. 6970018 - Filed Jun 23, 2004 - Intel Corporation
CLOCKED CYCLE LATCH CIRCUIT CROSS-REFERENCE TO RELATED APPLICATIONS 5
This
application is a continuation of US application Ser. No. ...
Queue structure with validity vector and order array
US Pat. 7249230 - Filed Jun 23, 2004 - Intel Corporation
35 input ol every order array latch 230 in row[x] other than then ...
A of the
associated validity vector latch 220. The read word- processing system
may be
...
Interpolator testing system
US Pat. 7043392 - Filed Jun 16, 2004 - Intel Corporation
Flip-flops 370 and 390 are illustrated as D flip-flops, but 30 any
other flip-
flop or latch may be used in conjunction with some embodiments. ...
Memory agent core clock aligned to lane
US Pat. 7212423 - Filed May 31, 2004 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. 20 Read data signals RDX
[0 ...
[APPLICATION] Valid bit generation and tracking in a pipelined
processor
US Pat. 10847837 - Filed May 17, 2004 - Intel Corporation, a Delaware
corporation, Analog Devices, Inc., a Delaware corporation
[0030] After being qualified by the valid bit qualifier 504, the valid
bit may
be input to a latch 510. The latch 510 may be controlled by a latch
enable ...
Methods and apparatuses for validating AC I/O loopback tests using
delay ...
US Pat. 7228515 - Filed May 13, 2004 - Intel Corporation
The outbound strobe buffer 114 A is connected 15 to latch 115A. ...
The looped
back version of the test value is 30 captured by a latch 11 OA clocked
by a ...
System for end of interrupt handling
US Pat. 7054974 - Filed May 5, 2004 - Intel Corporation
... the 8-bit comparator of 130 associated with that 8-bit latch may
transmit a
signal on coupling 140. In this embodiment, this signal may in turn be
used ...
Methods and apparatuses for detecting clock loss in a phase-locked
loop
US Pat. 7038508 - Filed Apr 30, 2004 - Intel Corporation
The phase-locked loop of claim 9, further comprising a first latch and
a second
latch, the first latch coupled to the first output terminal such that
an ...
Socket lid and test device
US Pat. 7208936 - Filed Apr 12, 2004 - Intel Corporation
... a cantilever, a forced insertion conductor, and a silicon chip.
connection,
an adhesive, a latch, a retaining lid, a distributed 25. ...
Programmable clock delay circuit
US Pat. 7102407 - Filed Mar 31, 2004 - Intel Corporation
... within one period of reference clock signal 120 in order to latch
to 15 ...
clock signal 120 by delay A^, flip-flop FF2 would latch a stale value
of ...
Method and apparatus for a low latency source-synchronous address
receiver ...
US Pat. 6915407 - Filed Mar 30, 2004 - Intel Corporation
... two inputs: one is a source synchronous address strobe directing
the
receiver to latch the address and store data, while the other is a
protocol
signal, ...
Optical module with latching/delatching mechanism
US Pat. 7083336 - Filed Mar 18, 2004 - Intel Corporation
6A, thereby rotating the mating element 1300 (counter-clockwise)
around the
pivot element 1303 and releasing the latch 1028 from the 10 chamber
1305 and ...
Memory post-write page closing apparatus and method
US Pat. 7167947 - Filed Mar 15, 2004 - Intel Corporation
At 312, arbitration transaction is copied to a latch for storing the
address of
the logic arbitrates between any pending read transactions ...
Method and apparatus for an integrated circuit having flexible-
ratio ...
US Pat. 7257728 - Filed Mar 5, 2004 - Intel Corporation
A clock domain cross-over apparatus comprising: a plurality of latches
to latch
data items; an array of status bits comprising one valid bit and one
free ...
Wireless display systems and stylii
US Pat. 7248251 - Filed Mar 5, 2004 - Intel Corporation
... LATCH SENSOR h 1 404 412 416 --^442 i 42 rx^ ^~ WIRELESS INTERFACE
TO
COMPUTER ULTRASONIC -/A/D LATCH SENSOR -444 i \ p418 420 422 FILTER
DETECTOR . j
.
Convertible and detachable laptops
US Pat. 7251127 - Filed Mar 2, 2004 - Intel Corporation
The computer system of claim 39, further comprising a base flap
pivotally and
removably attached to the display housing using the latch and
pivotally ...
Dynamically activated memory controller data termination
US Pat. 7009894 - Filed Feb 19, 2004 - Intel Corporation
The apparatus of claim 29 wherein said second value corresponds to a
response to
a clear input of said latch being activated. 31. The apparatus of
claim 29 ...
Buffering and interleaving data transfer between a chipset and memory
modules
US Pat. 7249232 - Filed Feb 11, 2004 - Intel Corporation
The method also includes interleaving output of the buffers, and
configuring the
buffers to properly latch the data being transferred between the
chipset ...
Single stage level restore circuit with hold functionality
US Pat. 7202703 - Filed Jan 30, 2004 - Intel Corporation
2 300B may be utilized to capture, eg sample and latch, the data not
captured by
device 300A. For example, if device 300A captures data2 data4 data6
etc., ...
[APPLICATION] Solder ball attachment system
US Pat. 10768498 - Filed Jan 30, 2004 - Intel Corporation
The attachment mechanism 170 may be a latch-arrangement or magnetic
holders. The
ball placement mask 168 is properly aligned to the first section 164
by ...
Mounting system for high-mass heatsinks
US Pat. 7017258 - Filed Jan 26, 2004 - Intel Corporation
The mounting system of claim 3, the ratchet assembly further
comprising a latch
for inhibiting movement of the ratchet assembly once the mounting
system is ...
Apparatus coupling two circuits having different supply voltage
sources
US Pat. 7251740 - Filed Jan 23, 2004 - Intel Corporation
A master latch 18 and slave latch 20 receives a Datal signal which, in
response
to a clock signal, is provided to the level shifter 10 as a Data2
signal. ...
Network communications system
US Pat. 6909046 - Filed Jan 20, 2004 - Intel Corporation
The resilient tab 144 carries an outwardly projecting latch 146 that
engages the
top of the abutment 118 on the top of the associated cable dispenser
82 to ...
Method and apparatus for controlling a multi-mode I/O interface to
enable an ...
US Pat. 7159135 - Filed Jan 12, 2004 - Intel Corporation
... such that the serialization state machine generates a latch enable
signal
for the one or more latches. 20. A system comprising: a memory
controller, ...
Method and apparatus to delay signal latching
US Pat. 6930522 - Filed Jan 6, 2004 - Intel Corporation
Thus, CLK may be applied to input of delay 102 to produce LATCH, ...
Load
circuit 302 may provide additional control over timing of LATCH in a
manner ...
Write pointer error recovery
US Pat. 6956775 - Filed Dec 31, 2003 - Intel Corporation
The buffer circuits 10A and 10C-10H may latch the data into address
(bit ...
However, buffer 65 circuit 10B may not latch the data, so the data in
that bit
...
Configurable enabling pulse clock generation for multiple signaling
modes
US Pat. 7038505 - Filed Dec 31, 2003 - Intel Corporation
2 A and 2B illustrate input section 10 in further detail, in
particular sense
amplifier circuits and 16 and 15 latch banks 26, according to some
embodiments
...
Timing circuit for separate positive and negative edge placement in
a ...
US Pat. 7030676 - Filed Dec 31, 2003 - Intel Corporation
The method of claim, further comprising: 5 storing said logical values
of the
interim timing signal in a latch prior to respective edge transitions
of the ...
Method and apparatus for multiple row caches per bank
US Pat. 6990036 - Filed Dec 30, 2003 - Intel Corporation
Isolator control logic 250 may operate isolators 238a couple sense
amplifiers
230a to corresponding ones of global I/O lines 264 to latch the data
received
...
Detecting peak signals
US Pat. 7064585 - Filed Dec 30, 2003 - Intel Corporation
In such a manner, excellent absolute value detector; process,
temperature, and
supply tracking through biasing a latch coupled to the cascode
current ...
Fixed phase clock and strobe signals in daisy chained chips
US Pat. 7031221 - Filed Dec 30, 2003 - Intel Corporation
The clock is usually distributed in 20 received strobe signal is used
to latch
data from chip 40 to a similar multi-drop fashion, limiting the
bandwidth of ...
Variable-delay signal generators and methods of operation therefor
US Pat. 6970029 - Filed Dec 30, 2003 - Intel Corporation
This is desirable in order to measure the effective input latch setup
and hold
timing. Generally, the strobe signal is shifted by sequentially
applying an ...
Method and apparatus to perform on-die waveform capture
US Pat. 7275004 - Filed Dec 23, 2003 - Intel Corporation
... the multiplier and latch device according to an example embodi-
waveform
received on the ; t node 52 in response to the ment of the present
invention;
...
[APPLICATION] Process for exchanging information in a multiprocessor
system
US Pat. 10743468 - Filed Dec 23, 2003 - Intel Corporation
The corresponding outputs of the register LATCH are connected to the
inputs of a
priority encoder PRI, the outputs of which are connected to the inputs
of a ...
Circuit and method for protecting 1-hot and 2-hot vector tags in
high ...
US Pat. 6904502 - Filed Dec 23, 2003 - Intel Corporation
In place of the b!2 line is the output of a latch 344. Furthermore,
the gate of
transistor 300, which, when turned on, can cause the value at the
output of ...
Soft-error rate hardened pulsed latch
US Pat. 7038515 - Filed Dec 19, 2003 - Intel Corporation
ACTIVATE A NUMBER OF PASS ELEMENTS USING A PULSE PROPAGATE DATA TO A
NUMBER OF
STORAGE NODES VIA THE PASS ELEMENTS OUTPUT THE DATA FROM THE STORAGE
NODES ...
Single event upset hardened latch
US Pat. 7161404 - Filed Dec 19, 2003 - Intel Corporation
Single ...
System management memory for system management interrupt handler
independent ...
US Pat. RE38927 - Filed Dec 19, 2003 - Intel Corporation
The :o fetch address is delivered to the latch 134 via an address path
121 that
... Once the fetch address is latched in the latch 134, a set signal
131 is ...
[APPLICATION] Memory component with synchronous data transfer
US Pat. 10740012 - Filed Dec 18, 2003 - INTEL CORPORATION.
[0220] This arbitrator comprises a register LATCH, of which three
inputs receive
... The corresponding outputs of the register LATCH are connected to
the ...
[APPLICATION] Decision feedback equalization employing a lookup table
US Pat. 10742025 - Filed Dec 17, 2003 - Intel Corporation
Other types of regenerative latch circuits may be used to provide the
digital
output signal. [0055] FIG. 8 shows a block diagram of another
embodiment of a
...
Power supplies noise detector for integrated circuits
US Pat. 7157947 - Filed Dec 9, 2003 - Intel Corporation
... 15 an exclusive-OR gate coupled to the Schmitt trigger, to provide
noise
polarity selection; a logic-high latch comprising a NOR gate, a NAND
gate, ...
Circuit and method for protecting 1-hot and 2-hot vector tags in
high ...
US Pat. 6839814 - Filed Dec 4, 2003 - Intel Corporation
In place of the b!2 line is the and w!2 that are coupled to memory bit
circuits
210, 220 output of a latch 344. Furthermore, the gate of
transistor ...
Adder circuit with sense-amplifier multiplexer front-end
US Pat. 7325024 - Filed Dec 4, 2003 - Intel Corporation
... overheads of an explicit latch stage. 26 Claims, 9 Drawing
Sheets ...
Device, system and method for VLSI design analysis
US Pat. 7073141 - Filed Nov 25, 2003 - Intel Corporation
For example, in one embodiment, the analysis may result in an
identification of
a bus retainer, a domino structure or a precharge logic, a latch, ...
Synchronizing signals between clock domains
US Pat. 6949955 - Filed Nov 24, 2003 - Intel Corporation
... Circuit 200 kw Dn=AB;=AB ~ w clock ratio Window Circuit s|w cit, nse
Circuit w
TAT ww 204 latch r V pady < r ...
Method and apparatus for detecting and correcting clock duty cycle
skew in a ...
US Pat. 7260736 - Filed Nov 19, 2003 - Intel Corporation
In operation 220, the 10 is simultaneously distributed to clock
doubler 20,
latch difference between the leading edge of clock cycle P2 and
70, ...
Early CRC delivery for partial frame
US Pat. 7219294 - Filed Nov 14, 2003 - Intel Corporation
A multiplexer 15 100 selectively couples data signals from either the
buffer 94
or a serializer 102 to a transmit latch 104. Read data signals RDX
[0 ...
[APPLICATION] Lane testing with variable mapping
US Pat. 10714026 - Filed Nov 14, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. Read data signals RDX
[0 . . . n] ...
Data accumulation between data path having redrive circuit and memory
device
US Pat. 7143207 - Filed Nov 14, 2003 - Intel Corporation
Write data is taken from the output of the ^ ^ articular redrive
circuit: nor is
the fail.over transmit latch collected in a deserializer 108 and then
35 ...
System and method for dynamic rank specific timing adjustments for
double ...
US Pat. 7127584 - Filed Nov 14, 2003 - Intel Corporation
... the da a ~ ~ strobe signal may be input to a latch to capture the
data tains
two parts: a whole number portion and a fractional . i r> i, =95 a, ...
Parallel electrode memory
US Pat. 7184289 - Filed Nov 12, 2003 - Intel Corporation
The array 24 is addressed through a combination of the device control
55
circuitry 28 and the address latch 18. The address latch 18 stores
address ...
Method and apparatus for releasably locking an optical transceiver
into a ...
US Pat. 7064959 - Filed Nov 6, 2003 - Intel Corporation
Each latch 36a, 36A includes a first surface 38 (see FIG. 5) for
engaging and
moving the levers 26a, 26A in the direction of arrow 40 towards a
first or ...
Heat sink and antenna
US Pat. 6891726 - Filed Oct 30, 2003 - Intel Corporation
A latch 210 on heat sink 148 may catch with a latch 212 on housing 100
of
network interface card to secure heat sink 148 and antenna 114 into a
retracted
...
Oscillator with tunable capacitor
US Pat. 7109810 - Filed Oct 27, 2003 - Intel Corporation
The latch settings may also be modified by an operating system (OS)
running on
... The OS controls chipset 508 to adjust the latch settings according
to the
...
Staggering execution of a single packed data instruction using the
same circuit
US Pat. 6925553 - Filed Oct 20, 2003 - Intel Corporation
Each delay element 350, 360 may include a latch 370 and a driver 380.
Data input
to a delay element 40 350, 360 appears on its output with a one clock
cycle ...
Method and apparatus for on-die voltage fluctuation detection
US Pat. 7157924 - Filed Oct 10, 2003 - Intel Corporation
The asynchronous capture block 240 may correspond to a S/R type of
latch, ...
The synchronous capture block 250 may correspond to a D-type of
latch, ...
Reduced hardware network adapter and communication method
US Pat. 7080162 - Filed Oct 8, 2003 - Intel Corporation
The reduced hardware MAC 25 includes memory for buffering data as it
is
transferred to or received from the PHY 72 including, preferably, a
latch for
...
Dynamic prefetch in continuous burst read operation
US Pat. 7225318 - Filed Oct 8, 2003 - Intel Corporation
... and an output coupled to the control input of the address
multiplexer; and
an address latch having a first input to accept a prefetched
address, ...
Select logic for low voltage swing circuits
US Pat. 6922082 - Filed Sep 30, 2003 - Intel Corporation
Each branch 40, 42 and 44 includes a flip-flop 45 having in series a
master
latch 46, a Dl domino 48, a slave latch 50, and even number of
buffering ...
Branch-aware FIFO for interprocessor data sharing
US Pat. 7257665 - Filed Sep 29, 2003 - Intel Corporation
Examples of these types of memory cells are a latch or a flip-flop. 35
Basic
control of FIFO memories devices is known, such as how to control the
pushing
...
Method and apparatus including heuristic for sharing TLB entries
US Pat. 7165164 - Filed Sep 24, 2003 - Intel Corporation
Latch 633 includes both data 45 portion 614 for storing virtual
address data ...
The latch 637 includes, in data portion 624, a 50 corresponding
physical ...
Electromagnetically-coupled bus system
US Pat. 7080186 - Filed Sep 23, 2003 - Intel Corporation
In addition to amplification, amplifiers 920 may latch their outputs
with
appropriate timing signals to provide sufficient pulse widths for
succeeding ...
Apparatus, method and system for counting logic events, determining
logic ...
US Pat. 6856944 - Filed Sep 17, 2003 - Intel Corporation
Thus, for example, the particular or both of the event count latch
arrangement
35 and the test to be performed may depend on the particular experi-
30 ...
Computer system with detachable display
US Pat. 7206196 - Filed Sep 15, 2003 - Intel Corporation
4A illustrates one example ol the back side 107 ol latching mechanism
115 when
force is applied to the latch- ., ,. , .. 1A, . , ... , ,. ,. ...
Method, apparatus, and system for high speed data transfer using
source ...
US Pat. 6839290 - Filed Sep 15, 2003 - Intel Corporation
An apparatus comprising: first logic to generate a write strobe signal
that is
used to latch output data into a memory unit, the write strobe signal
having ...
Adaptive equalization using a conditional update sign-sign least mean
square ...
US Pat. 7289557 - Filed Sep 10, 2003 - Intel Corporation
... a data generator coupled to the filter to provide a discrete- time
sequence
of desired voltages d(t), t=3Dl, 2, . . . , T; a latch circuit coupled
to the ...
Ferroelectric memory input/output apparatus
US Pat. 6901001 - Filed Sep 4, 2003 - Intel Corporation
The data latch on the accessed device captures the data, once the read
operation
.... The address signals are latched using the address latch shown in
FIG. ...
Hardware recovery in a multi-threaded architecture
US Pat. 7373548 - Filed Aug 29, 2003 - Intel Corporation
The raw FIT rate can be computed using circuit models and currently
ranges
between 0.001 and TECHNICAL FIELD 15 0.01 per latch. The derating
factor is the
...
Lower power high speed design in BiCMOS processes
US Pat. 7126382 - Filed Aug 29, 2003 - Intel Corporation
A BiCMOS latch comprising: a first transistor and a second
transistor ... The
BiCMOS latch of claim 28, further comprising a level shifter coupled
to the ...
IC memory complex with controller for clusters of memory blocks I/
O ...
US Pat. 7318115 - Filed Aug 27, 2003 - Intel Corporation
The left and right latch arrays ... appro- priately turn on the sense
amplifier
arrays and to then latch the data signal The column select decoder
3710 only ...
Bus state keepers
US Pat. 7233166 - Filed Aug 27, 2003 - Intel Corporation
Inverter 19 inverts and buffers the output into the latch 4105N. The
latch 4105N
is a conventional latch which is clocked by a latch clock. ...
High-accuracy continuous duty-cycle correction circuit
US Pat. 7120839 - Filed Aug 22, 2003 - Intel Corporation
Background of the Related Art Synchronous chips often use a latch
design in
which a logic path propagates in one phase (high or low) of a clock
signal. ...
Secure hardware random number generator
US Pat. 7269614 - Filed Aug 7, 2003 - Intel Corporation
VCO 216 generates and outputs a relatively low frequency digital
oscillating
signal at an output 15 coupled to a clock input terminal of D-type
latch 218.
...
[APPLICATION] Apparatus and method for protecting critical resources
against soft errors ...
US Pat. 10634899 - Filed Aug 6, 2003 - INTEL CORPORATION
The apparatus of claim 4 further comprising a result latch coupled
between the
first XOR gate and the second XOR gate, the result latch being
configured to ...
Apparatus and associated methods for precision ranging measurements in
a ...
US Pat. 7203500 - Filed Aug 1, 2003 - Intel Corporation
Once the analog representation of the received message reaches a
threshold, the
matched filter 306 generates a strobe signal 307, which causes latch
308 to ...
Programmable random bit source
US Pat. 7177888 - Filed Aug 1, 2003 - Intel Corporation
2 are input to a D type latch to produce a synchronized output of
digital bits.
... For a latch-based random bit source, the reference voltage level
45 ...
Digitally controlled variable offset amplifier
US Pat. 6798293 - Filed Jul 30, 2003 - Intel Corporation
... LATCH ...
Filtering variable offset amplifier
US Pat. 6946902 - Filed Jul 24, 2003 - Intel Corporation
The filter circuit of claim 16, wherein the output nodes are coupled
to at least
one load selected from the group consisting of a regenerative
latch, ...
Dynamic current calibrated driver circuit
US Pat. 6947859 - Filed Jul 18, 2003 - Intel Corporation
What these techniques have in common is that they rely upon a current
control
value that is stored in a latch or register on the integrated
circuit. ...
[APPLICATION] Statistics collection framework for a network processor
US Pat. 10620488 - Filed Jul 15, 2003 - Intel Corporation (a Delaware
corporation)
... MUX l~^V> ^ \ MUX li ' r \ ' \ 7-176 150 \ | RAM CONTROL STORE
PIPE LATCH
PIPE LATCH[- -180 \ 178 ,, | \ ' FIG.3 \ MUX /-182 \ MUX /- -184 188-
A^ ALU J
...
Structural regularity extraction and floorplanning in datapath
circuits ...
US Pat. 7337418 - Filed Jul 14, 2003 - Intel Corporation
2, if the AND gate of SI of bit slice 1 were deleted, but the output
of the AND
gate of SI of bit slice 0 were fed into the input of the latch of SI
of bit ...
Memory driver architecture and associated methods
US Pat. 7200060 - Filed Jul 15, 2003 - Intel Corporation
2, a timing diagram of signals generated by the As shown, transistors
128 and
132 are coupled in a 5 pulse generator of latch element 106 is
presented, ...
Slave-less edge-triggered flip-flop
US Pat. 6956421 - Filed Jul 10, 2003 - Intel Corporation
During the time that both transistors in each stack 38, 35 40 are on,
one of
storage nodes 28, 30 of the latch 20 within the state retention
portion 12 will
...
Parallel to serial conversion device and method
US Pat. 6771194 - Filed Jul 9, 2003 - Intel Corporation
In the case that there is no bit being transferred, then DOP 71 and
DON 72 stay
with the last bit value, and MN5 52 and MN6 54 may act as a
latch. ...
Generalized pre-charge clock circuit for pulsed domino gates
US Pat. 6968475 - Filed Jul 8, 2003 - Intel Corporation
In one operation, latch 102 stores the enable signal 106 during the
positive
clock cycle. Next, the clock circuit 104 40 receives the output of
latch 102,
...
Faster shift value calculation using modified carry-lookahead adder
US Pat. 7240085 - Filed Jul 7, 2003 - Hewlett-Packard Development
Company, L.P., Intel Corporation
... r 14 16 J\ LATCH CSA (19-BITS) CSA Jfl CONSTANT RESULT FIG.1 PRIOR
ART ABC
... LATCH WTCH LATCH ^36 ^ 32 34 ^. 1 4=B0\_ CSA 46 =97^CONTROL SIGNAL CLA
WITH ...
Rate matching apparatus, systems, and methods
US Pat. 7260659 - Filed Jun 30, 2003 - Intel Corporation
... 316, 416, rate matcher bit pattern 120, 220, FIFO memory 124, 224,
Enable
signal 128, multiplexer, 230, 430, mode bit, register, latch 142,
memory 144,
...
Application of the retimed normal form to the formal equivalence ...
US Pat. 7117465 - Filed Jun 30, 2003 - Intel Corporation
WHILE {remaining latches is not empty} 6. latch :=3D head remaining
latches 7.
remaining -latches :=3D tail remaining -latches. IF{latch is latching
data =3DG(L:,
...
System and method for testing semiconductor devices
US Pat. 6894523 - Filed Jul 1, 2003 - Intel Corporation
2, the force retainer 216 is hinged at one end with hinge 222 and
latched at
another end with latch 223. The force retainer 20 216 might be hinged
depending
...
Pseudo-dynamic latch deracer
US Pat. 6879186 - Filed Jun 30, 2003 - Intel Corporation
... latch ...
Automatic self test of an integrated circuit component via AC I/O
loopback
US Pat. 7139957 - Filed Jun 30, 2003 - Intel Corporation
For example, each latch 204 need only be loaded once for an AC I/O
loopback ...
The sequence is further qualified a by latch circuit 312 which is
clocked by ...
Low power differential link interface methods and apparatuses
US Pat. 7069455 - Filed Jun 30, 2003 - Intel Corporation
... the receiver 25 includes an integration and a latch coupled
together, the
integration coupled to the two lines to receive the data, and the
latch ...
System and method for data retention with reduced leakage current
US Pat. 7170327 - Filed Jun 27, 2003 - Intel Corporation
5 illustrates a portion of a semiconductor die in an output inverter
may be part
of slave latch of one of accordance with embodiments of the
present ...
Apparatus for receiver equalization
US Pat. 7227414 - Filed Jun 27, 2003 - Intel Corporation
In some embodiments any self-biasing amplifier or latch is used. In
some
embodiments the amplifier uses a form of positive feedback to assist
the
amplifier ...
Variable delay element for use in delay tuning of integrated circuits
US Pat. 6885231 - Filed Jun 20, 2003 - Intel Corporation
Accordingly, a latch 200 is provided between the source of the data
signal and
the ... The latch 200 itself is clocked by a non-delayed clock signal
200. ...
Double-gate transistor with enhanced carrier mobility
US Pat. 6974733 - Filed Jun 16, 2003 - Intel Corporation
... a structure and fabrication method using latch-up implantation to
improve
latch- up immunity in CMOS circuit. US Patent Application Publication
Number ...
Method and apparatus to analyze noise in a pulse logic digital circuit
design
US Pat. 7107552 - Filed Jun 10, 2003 - Intel Corporation
1 to an AND gate coupled to a latch and apply steady state signals to
inputs of
the equivalent circuit to analyze noise effects. ...
Speed-locked loop to provide speed information based on die operating
conditions
US Pat. 6982580 - Filed Jun 6, 2003 - Intel Corporation
For another embodiment SLL, latch 220 may be controlled so as to latch
onto the
smaller of the two values of ...
Memory channel with redundant presence detect
US Pat. 7340537 - Filed Jun 4, 2003 - Intel Corporation
12, the redrive path includes sampling unit 96, termination unit 98,
buffer 94,
multiplexer 100, transmit latch 104, and transmitter 106. ...
Memory channel with unidirectional links
US Pat. 7165153 - Filed Jun 4, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. Read data signals RDX
[0 . . . n] ...
[APPLICATION] Memory channel with bit lane fail-over
US Pat. 10456353 - Filed Jun 5, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. Read data signals RDX
[0 . . . n] ...
[APPLICATION] Memory channel having deskew separate from redrive
US Pat. 10456206 - Filed Jun 4, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. Read data signals RDX
[0 . . . n] ...
Apparatus and method for reducing power consumption by a data
synchronizer
US Pat. 6989695 - Filed Jun 4, 2003 - Intel Corporation
The data synchronizer circuit 400 includes a transparent 40 latch 402
and a ...
The transparent latch 402 and the D-type flip-flop 404 may themselves
be ...
Memory channel utilizing permuting status patterns
US Pat. 7200787 - Filed Jun 3, 2003 - Intel Corporation
Another multiplexer may be disposed between buffer 94 and transmit
latch 104
with one input connected to the buffer and another input connected to
an output
...
Memory channel with hot add/remove
US Pat. 7194581 - Filed Jun 3, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. ...
Redriving a data signal responsive to either a sampling clock signal
or ...
US Pat. 7127629 - Filed Jun 3, 2003 - Intel Corporation
A multiplexer 100 selectively couples data signals from either the
buffer 94 or
a serializer 102 to a transmit latch 104. Read data signals RDX
[0 . . . n] ...
Data-enabled static flip-flop circuit with no extra forward-path delay
penalty
US Pat. 6864733 - Filed May 29, 2003 - Intel Corporation
Through this structural configuration, the flip-flop or latch outputs
logical
values without requiring any additional forward-path delay
elements. ...
Vectored flip-flops and latches with embedded output-merge logic and
shared ...
US Pat. 6828838 - Filed May 30, 2003 - Intel Corporation
The first flip-flop 1002 includes a master latch 1014 and a slave
latch 1016.
... 11, a logic cell 1100 includes a first latch 1102, a second latch
1104, ...
Startup/yank circuit for self-biased phase-locked loops
US Pat. 6922047 - Filed May 29, 2003 - Intel Corporation
The first path includes a divider-by-N counter 71 with an a
synchronous reset (R
), a D flip-flop 72, and an SR latch 73. The second path maybe
similarly ...
[APPLICATION] High-speed serial link receiver with centrally
controlled offset ...
US Pat. 10444310 - Filed May 22, 2003 - Intel Corporation
... and wherein the receiver further comprises a latch to store the
multiple-bit
code for each comparator element of the comparator stage. 5. ...
[APPLICATION] OSCILLATOR SYSTEM WITH SWITCHED-CAPACITOR NETWORK AND
METHOD FOR GENERATING ...
US Pat. 10444311 - Filed May 22, 2003 - Intel Corporation
In other embodiments, the stability of the oscillator frequency may
be
determined by sampling energy of the oscillation frequency and setting
a latch
when ...
Circuit and method for protecting 1-hot and 2-hot vector tags in
high ...
US Pat. 6775746 - Filed May 12, 2003 - Intel Corporation
In place of the b!2 line is the output of a latch 344. Furthermore,
the gate of
transistor 300, which, when turned on, can cause the value at the
output of ...
Method and apparatus for flash voltage detection and lockout
US Pat. 6789027 - Filed May 12, 2003 - Intel Corporation
... or any other As described above, the trip point voltage is a
voltage system
which uses a latch type mechanism for other embodi- 50 level at which
power ...
Amplifier apparatus, method, and system
US Pat. 6838939 - Filed Apr 29, 2003 - Intel Corporation
Integrated circuit 620 may utilize the clock signal received by clock
receiver
622 to latch data received by data , receiver 624. ...
Self-timed activation logic for memory
US Pat. 6785184 - Filed Apr 25, 2003 - Intel Corporation
... LATCH CLOCK LATCH ...
Method and apparatus for dynamic branch prediction utilizing multiple
stew ...
US Pat. 7143273 - Filed Mar 31, 2003 - Intel Corporation
... t latch | readout instr ptr trace line BHT filled-in stew logic
esj ...
System for a card proxy link architecture
US Pat. 6678776 - Filed Mar 28, 2003 - Intel Corporation
The PCI RST# signal is applied to the latch enable input LE of latch
92. A
standard PCI card must hold this signal in a Hi-Z state during PCI
RST#
assertion ...
Apparatus and a method for pMOS drain current degradation compensation
US Pat. 6768351 - Filed Mar 26, 2003 - Intel Corporation
The signal Latch Enable 510 in FIG. 5 corresponds to the opposite of
the ...
Thus, Latch Enable 510 is low when the pMOS transistors 320 are
stressed, ...
Reusable, built-in self-test methodology for computer systems
US Pat. 7155370 - Filed Mar 20, 2003 - Intel Corporation
The N bit pattern latch 430 may be a serial/parallel latch that is in
a user ...
The pattern latch 430 may be clocked by a Test Access Port (TAP) clock
for ...
Variable latch
US Pat. 7160127 - Filed Mar 18, 2003 - Intel Corporation
particular configuration, but may comprise any latch with a plurality
of contact
points, for example. The latch shown in FIG. \a may be formed of a
plastic ...
Convertible and detachable laptops
US Pat. 6775129 - Filed Feb 14, 2003 - Intel Corporation
... communication ports, a keyboard, and the like. go The base flap
308 may be
wrapped around the tablet 304 and attached to it by a latch 310. ...
Memory controller for synchronous burst transfers
US Pat. 7136971 - Filed Feb 10, 2003 - Intel Corporation
This arbitrator comprises a register LATCH, of which In writing the
cache memory
, the management processor three inputs receive respectively the
signals ...
Burn in board having a remote current sensor
US Pat. 6850083 - Filed Feb 5, 2003 - Intel Corporation
The output of the blow timer (U1B) is connected to the cut out latch
(U1C), ....
The cutout latch (U1C) latches the over current comparator (U1A) until
a ...
Double data rate memory interface
US Pat. 6791889 - Filed Feb 4, 2003 - Intel Corporation
By design, MUX has inputs connected to the output of buffer 232 and to
an 212
properly aligns STROBE signal transitions with DATA output of latch
242, ...
System and method for extending delay-locked loop frequency
application range
US Pat. 6803797 - Filed Jan 31, 2003 - Intel Corporation
The fast detection unit includes a latch for noise filtering which
includes ...
In addition to forming a latch, inverters 311 and 312 may be said to
form a ...
Frequency phase detector for differentiating frequencies having small
phase ...
US Pat. 6803753 - Filed Jan 7, 2003 - Intel Corporation
In an embodiment, latch keeper 44, a cross-coupled inverter, having
inverter 46
and inverter 48, maintains a value at logic NAND gate 50 and logic
NAND gate ...
High gain amplifier circuits and their applications
US Pat. 6710656 - Filed Jan 2, 2003 - Intel Corporation
However, in other embodiments, the regenerative latch circuit 510 may
be ... 5,
after being reset by an input signal (RESET), the regenerative latch
circuit ...
Retention mechanism for an electrical assembly
US Pat. 6722908 - Filed Jan 2, 2003 - Intel Corporation
Each post 10 includes an aperture 11 which receives a latch 12 that
extends ...
When inserted into the aperture 11 each latch 12 prevents the
substrate 2 ...
Method and apparatus for flexible and programmable clock crossing
control ...
US Pat. 7269754 - Filed Dec 30, 2002 - Intel Corporation
The wide latch 320 may in one embodiment be either 4 or 8 bits wide,
with a
common clock ... Wide latch 320 may contain the current count of the
number of
...
Same edge strobing for source synchronous bus systems
US Pat. 7076677 - Filed Dec 30, 2002 - Intel Corporation
... EDGE OF DATA START ) \UO RECEIVE DATA AND STROBE SIGNALS U20
SELECT RISING
EDGE OF STROBE SIGNALS TO LATCH RISING EDGE OF DATA ...
Time-borrowing N-only clocked cycle latch
US Pat. 6806739 - Filed Dec 30, 2002 - Intel Corporation
In addition to these advantages, the control circuit allows the cycle
latch of
the invention to achieve better noise robustness. ...
Electromagnetic coupler registration and mating
US Pat. 6887095 - Filed Dec 30, 2002 - Intel Corporation
20-25, arms 730 and 740 each include an upright guide 732 and 742,
respectively,
and a latch 734 and 744, respectively. Upright guides 732 and 742
each ...
Selecting a first clock signal based on a comparison between a
selected ...
US Pat. 7043654 - Filed Dec 31, 2002 - Intel Corporation
... wherein said decoding is associated with a latch to receive each
comparison
clock signal and a logic 45 gate to receive information from each
latch ...
Scan cell designs for a double-edge-triggered flip-flop
US Pat. 6943605 - Filed Dec 31, 2002 - Intel Corporation
A master latch receives the output of the multiplexer along with
SCLKA1. Aslave
latch receives an output of the master latch along with ...
Low power state retention
US Pat. 6775180 - Filed Dec 23, 2002 - Intel Corporation
5 is a schematic for a Set Dominant Latch (SDL) 500 40 having a state
retentive
... The state value retained in latch 128 is written by transistors
122, ...
Scan cell systems and methods
US Pat. 6815977 - Filed Dec 23, 2002 - Intel Corporation
Similarly, the Bclk signal is received by slave latch and controls the
storage
of a data ... As shown, slave latch stores data using full static
keeper. ...
Tail current node equalization for a variable offset amplifier
US Pat. 6617926 - Filed Dec 23, 2002 - Intel Corporation
Other types of regenerative 10 latch circuits may be used to provide
the digital
type output signal typically associated with a sense amplifier or
a ...
Simultaneous bidirectional signal subtraction
US Pat. 7164721 - Filed Dec 20, 2002 - Intel Corporation
Receiver 15 may comprise a latch to store the output signal and to
output the
signal in response to a clock pulse. Receiver 15 may also be adapted
to ...
Analog filter architecture
US Pat. 6768372 - Filed Dec 20, 2002 - Intel Corporation
... loads represent a filtered differential voltage signal that is
input to
differential evaluation circuit 50, which may comprise a differential
latch. ...
Pulse amplitude-modulated signal processing
US Pat. 7345605 - Filed Dec 20, 2002 - Intel Corporation
Each differential signal received by a particular latch is a filtered
current
signal that, in conjunction with its differential counterpart also
received by
...
Variable width, at least six-way addition/accumulation instructions
US Pat. 7293056 - Filed Dec 18, 2002 - Intel Corporation
... 440 and 445, where storage locations 440 and 445 may be used to
temporarily
latch 35 source operands that may not be used in the first stage
additions; ...
Gate-clocked domino circuits with reduced leakage current
US Pat. 6952118 - Filed Dec 18, 2002 - Intel Corporation
4 is a static-to-domino latch in an embodiment of the present
invention.
DESCRIPTION OF EMBODIMENTS 55 By clock gating during an evaluation
phase instead
of ...
Testing methodology and apparatus for interconnects
US Pat. 7047458 - Filed Dec 16, 2002 - Intel Corporation
... a pattern generator, a pattern checker, an error checking device,
local
control (or a local control device), a pattern latch and/or a pattern
sequencer.
...
Level shifter and voltage translator
US Pat. 6774696 - Filed Dec 12, 2002 - Intel Corporation
The translator circuit of claim 13 further including a latch having an
input
coupled to the drain of the second transistor and an output to provide
a signal
...
Over-clocking detection system utilizing a reference signal and
thereafter ...
US Pat. 6754840 - Filed Dec 10, 2002 - Intel Corporation
... 13 latches to latch comparator outputs indicating at least whether
said over
-clocking condition has been detected; and a thermal control logic
circuit ...
Apparatus and method for data bus power control
US Pat. 7152167 - Filed Dec 11, 2002 - Intel Corporation
2, for one embodiment, 30 the input buffer 310 further includes a
latch 352 ...
An output of the latch 352 is coupled to enable inputs of each of the
data ...
[APPLICATION] Low power modulation
US Pat. 10306772 - Filed Nov 26, 2002 - Intel Corporation
HE) and its complement, eg the signals at inputs 602 and 604. In
addition to
amplification, amplifiers 920 may latch their outputs with
appropriate ...
Differential charge transfer sense amplifier
US Pat. 6751141 - Filed Nov 26, 2002 - Intel Corporation
Even if the latch comprising the cross-coupled inverters were not
present, ...
But with the latch present, pMOSFET 312 will also charge node
322, ...
Quadrature direct synthesis discrete time multi-tone generator
US Pat. 7069042 - Filed Nov 1, 2002 - Intel Corporation
D-latch 322 also receives the clock signal CK and generates a signal
at the Q
output that, along with a signal provided at the QB output of D-latch
318, ...
Glitch protection and detection for strobed data
US Pat. 6591319 - Filed Oct 31, 2002 - Intel Corporation
Each data latch (say, 650-1) is 40 enabled by a respective latch
enabler 660-1.
Each latch enabler (say, 660-1) is controlled by a strobe signal ...
Deskew architecture
US Pat. 7164742 - Filed Oct 31, 2002 - Intel Corporation
This is because deterministic embodiments of the invention, the phase
detector
12 edge jitter is partly dependent on how long the input has includes
a latch
...
Discrete-time analog filter
US Pat. 6791399 - Filed Oct 9, 2002 - Intel Corporation
This is the reason why the voltages at embodiments, a resistor may be
used in
place of pMOSFET output ports 1622 and 1624 of differential latch 1608
are ...
Scan design for double-edge-triggered flip-flops
US Pat. 6938225 - Filed Sep 4, 2002 - Intel Corporation
The AND gate 415 has one input coupled to an output of the dual-ported
latch 405
, a second input coupled to receive the CLK2 signal and an output
coupled to ...
Increasing robustness of source synchronous links by avoiding write
pointers ...
US Pat. 7210050 - Filed Aug 30, 2002 - Intel Corporation
An apparatus comprising: a data receiving unit having a first latch
and a second
latch 55 coupled to receive data from a first clock domain and to
clock in ...
Memory device, circuits and methods for operating a memory device
US Pat. 6920060 - Filed Aug 14, 2002 - Intel Corporation
16 and 19-21 at time t4, self timer controller 262 activates LATCH ...
Sampling
comparator 214 and latch 222 may then determine (344, 326, 328 of
FIG. ...
Refreshing memory cells of a phase change material memory device
US Pat. 6768665 - Filed Aug 5, 2002 - Intel Corporation
This comparison produces an output signal (indicative of the read bit)
and may
be stored in a latch or flip-flop- 40 The threshold voltage may be
formed, ...
Techniques to map cache data to memory arrays
US Pat. 6954822 - Filed Aug 2, 2002 - Intel Corporation
A 60 de-multiplexer 530 sends the row address portion to a row address
latch 535
and a set of memory banks 555-1 to 555-N. The row lines of the memory
array ...
High speed DRAM cache architecture
US Pat. 7054999 - Filed Aug 2, 2002 - Intel Corporation
In this embodiment, each page is 256 bytes (4 latch 440 and onto a set
of
selectors 460-1 to 460-N. In this , , =84 . , =84 , .,,,,,, , TS bytes/
entry per ...
Circuits and methods for selectively latching the output of an adder
US Pat. 6731138 - Filed Jul 31, 2002 - Intel Corporatioin
Therefore, the transistor 84 switches on and off in response to the
clock signal
. A truth table illustrating the response of the set dominant 10 latch
76 to ...
Dynamic power level control based on a board latch state
US Pat. 6950952 - Filed Aug 1, 2002 - Intel Corporation
Upon detecting a latch event at the ejector switch, the control
circuit signals
the operating system with the appropriate power management
instruction. ...
Flip flop circuit
US Pat. 6597223 - Filed Jul 30, 2002 - Intel Corporation
Inverters 122 and 124 are cross-coupled to form a latch, as are
inverters 142
and 144. Inverters 124 and 144 are "clocked inverters," each having a
control
...
[APPLICATION] Flip-flop circuit
US Pat. 10201658 - Filed Jul 23, 2002 - Intel Corporation
[0007] Each of the master and slave stages has a feedback loop in the
form of a
latch controlled by the clock signal CLK, its complement ...
Heat sink with heat pipes and fan
US Pat. 6625021 - Filed Jul 22, 2002 - Intel Corporation
The heat sink of claim 19, further comprising: a latch assembly for
coupling the
heat sink to the printed circuit board without tools, the latch
assembly ...
Method and apparatus for dynamic timing of memory interface signals
US Pat. 7047384 - Filed Jun 27, 2002 - Intel Corporation
... A method and apparatus for using different timings to latch
signals sent by
two memory devices of identical design to compensate for differences
in the ...
Memory bus termination
US Pat. 6965529 - Filed Jun 21, 2002 - Intel Coproration
25 Claims, 4 Drawing Sheets Write Latch Control Logic VREF VHIGH
Impedance ...
Table 216 Impedance Control 212 WIMP RIMP Read Latch Memory I/O Buffer
Input ...
Method and system for shutting down and restarting a computer system
US Pat. 7120788 - Filed Jun 20, 2002 - Intel Corporation
Memory Controller Hub (MCH) ; =97 ^ =ABa"^ ^~* Latch Signal I/O Controller
^ Hub (
ICH) " *^__ 52 ' y=97 _._2_._^^_1_.. Latch Circuit Firmware Hub
(FWH) ...
Method and apparatus for jitter reduction in phase locked loops
US Pat. 7023945 - Filed Jun 17, 2002 - Intel Corporation
Multi-loop circuit 10 may also include a latch or storage device that
receives a
pll lock ...
Externally programmable antifuse
US Pat. 6888398 - Filed Jun 11, 2002 - Intel Corporation
5 For example, detector 13 can be a resistor to detect current flow
through MOS
capacitor 12; or a latch that detects the voltage across MOS capacitor
12; ...
Method and apparatus for staggering execution of a single packed
data ...
US Pat. 6687810 - Filed Jun 6, 2002 - Intel Corporation
At cycle T+4, however, the bypass controller 180 bypasses high order
data from
the delay latch 200 to execution unit 130 to complete the PSUB
instruction of
...
Arrangements for self-measurement of I/O timing
US Pat. 6898741 - Filed Jun 6, 2002 - Intel Corporation
In this arrangement, an output pad is connected to an output latch
through a
driver, and also connected to an input latch through a buffer, so as
to form a
...
Active cascode differential latch
US Pat. 6791372 - Filed Jun 4, 2002 - Intel Corporation
The analog filer as set forth in claim 4, the active cascode
differential latch
further comprising: a pre-charge transistor to provide a low impedance
path ...
Discrete-time analog filter
US Pat. 6621330 - Filed Jun 4, 2002 - Intel Corporation
Typical curves for differential latch of FIG. 11. the node voltages at
nodes nl
and n2 for a bit transition are FIG. 13 is a voltage-to-current
converter ...
Silicon wafers for CMOS and other integrated circuits
US Pat. 6667522 - Filed May 23, 2002 - Intel Corporation
... region 22 enables circuit fabrication while the heavier doping of
the bulk
region 24 of the wafer can help prevent the occurrence of latch -
up. ...
CMOS Amplifier for optoelectronic receivers
US Pat. 6771131 - Filed May 9, 2002 - Intel Corporation
An embodiment of a differential amplifier latch at the circuit level
is provided
in FIG. 6. ... The differential amplifier latch of FIG. 6 has two
stages. ...
Systems with non-volatile memory bit sequence program control
US Pat. 6597605 - Filed May 3, 2002 - Intel Corporation
Each bit slice 410 may further include a latch 412. Alternatively, a
latch, such
as latch 412' in the alternate embodiment the bit sequence
programming ...
Voltage control for clock generating circuit
US Pat. 6778033 - Filed May 2, 2002 - Intel Corporation
The logic 520 may include any type of latch, mechanism or state
machine to
perform a desired function in the core 101. FIG. ...
Frequency control for clock generating circuit
US Pat. 6771134 - Filed May 2, 2002 - Intel Corporation
The circuit of claim 11, further comprising a latch element to receive
a clock
signal from the clock distribution network. 22. A circuit comprising:
a clock
...
Arrangements having ternary-weighted parameter stepping
US Pat. 6642861 - Filed Apr 26, 2002 - Intel Corporation
... rnU| LATCH 14-\ ' llll 1 npi AV 1 BYPASS /'' BYPASS /'' BYPASS /''
i^ f^ t =95
. A 1 INIT^ ^w L - UNITS oyy ;, - 1UNIT Si W SIGNAL ...
Signal sampling circuits, systems, and methods
US Pat. 6621323 - Filed Apr 24, 2002 - Intel Corporation
Other types of regenerative latch circuits may be used to provide the
digital
type output 65 signal typically associated with a sense amplifier or
a ...
[APPLICATION] Decision feedback equalization employing a lookup table
US Pat. 10131444 - Filed Apr 24, 2002 - Intel Corporation
Other types of regenerative latch circuits may be used to provide the
digital
output signal. [0054] FIG. 8 shows a block diagram of another
embodiment of a
...
Nondestructive sensing mechanism for polarized materials
US Pat. 6842357 - Filed Apr 23, 2002 - Intel Corporation
This may include large, amplifier 48 is then latched by the latch
50. ... For
Generall this mem is static random access me example, the data latch
50 may be
...
Early power-down digital memory device and method
US Pat. 6781911 - Filed Apr 9, 2002 - Intel Corporation
An is registered into 226 only upon a Latch Column Address (LCA)
signal, which
could be the same signal used to latch a column address into column
address ...
Selectively multiplexing memory coupling global bus data bits to
narrower ...
US Pat. 6732203 - Filed Mar 29, 2002 - Intel Corporation
Inverter 19 inverts and buffers the output into the latch 4105N. The
latch 4105N
is a conventional latch which is clocked by a latch clock. ...
Method and apparatus for precise signal interpolation
US Pat. 6650159 - Filed Mar 29, 2002 - Intel Corporation
The I/O buffer 205 includes an output latch 215, an output go buffer
220, an
input buffer 225 and an input latch 230. The input buffer 225 has an
input ...
Low power entry latch to interface static logic with dynamic logic
US Pat. 6707318 - Filed Mar 26, 2002 - Intel Corporation
Low ...
Memory system with burst length shorter than prefetch length
US Pat. 6795899 - Filed Mar 22, 2002 - Intel Corporation
In some embodiments, circuitry 106 includes a latch 108 and a
multiplexer (Mux)
110, although the invention is not limited to this. ...
Measuring power supply stability
US Pat. 6617890 - Filed Mar 22, 2002 - Intel Corporation
The system of claim 1 wherein the indicator comprises violation
detector for
monitoring when a supply output of aa latch presenting the threshold
violation
...
Method and apparatus for fine granularity clock gating
US Pat. 6583648 - Filed Mar 19, 2002 - Intel Corporation
15 circuit 519 includes logic circuit 591, control logic 592, and
latch circuit
593. Local clock-buffer 521, similar to local gating circuit 300 in
FIG. ...
Positive and negative current feedback to vary offset in variable-
offset ...
US Pat. 6563374 - Filed Mar 15, 2002 - Intel Corporation
... transis- current flowing through a first Qne of me first ors' an
transistors
from flowing through a correspond- (b) a regenerative latch circuit
coupled ...
Low standby power using shadow storage
US Pat. 6639827 - Filed Mar 12, 2002 - Intel Corporation
3 is a schematic representation of a latch that may be used in the ...
7
illustrates another embodiment of a latch. It will be appreciated that
for ...
Method and apparatus for disabling a clock signal within a
multithreaded ...
US Pat. 6883107 - Filed Mar 8, 2002 - Intel Corporation
204 for each thread are set by the event detector 188 that Events are
communicated directly to the event detector triggers a latch which
sets the ...
Sparse refresh double-buffering
US Pat. 7038689 - Filed Feb 19, 2002 - Intel Corporation
... and issues a pixel write signal to this pixel cell's double-
buffering
circuitry, causing the back pixel buffer to read or latch the pixel
value. ...
Method and apparatus for off boundary memory access
US Pat. 6944087 - Filed Feb 15, 2002 - Intel Corporation
... memory cells depending upon the read/write signal (R/W) in
conjunction with
the memory cells that are accessed. The left and right latch arrays
408L and ...
(N-1)/n current reduction scheme in a n-to-one parallel-to-serial
conversion
US Pat. 6614372 - Filed Feb 12, 2002 - Intel Corporation
The current steering devices allow taking over by input data bit or
latch on the
previous bit il there is no input. The parallel bit is converted to a
bit ...
Register file scheme
US Pat. 6608775 - Filed Feb 4, 2002 - Intel Corporation
7 is a schematic diagram illustrating another embodiment of a latch
that may be
employed by embodiments of a register-file in accordance with the
invention. ...
Self-timed activation logic for memory
US Pat. 6618313 - Filed Jan 14, 2002 - Intel Corporation
5 The latch 305N includes inverters 131, 133, 154, and 155 and
transfer gates
TFG 26 and ... Inverter 19 inverts and buffers the output into the
latch 305N.
...
Memory controller with AC power reduction through non-return-to-idle
of ...
US Pat. 6529442 - Filed Jan 8, 2002 - Intel Corporation
In addition, in this embodiment, memory controller 11 includes NRI
circuit 17,
which includes a latch or register 67 that is 50 clocked on the
falling edge ...
Echo cancellation using a variable offset comparator
US Pat. 6978012 - Filed Jan 2, 2002 - Intel Corporation
Other types of regenerative latch circuits may be used to provide the
digital
type output signal typically associated with a sense amplifier or a
comparator
...
Power-up logic reference circuit and related method
US Pat. 6617874 - Filed Jan 2, 2002 - Intel Corporation
The apparatus of claim 6, wherein said latch circuit further comprises
a fourth
p-channel FET including a seventh source, a seventh drain, and a
seventh ...
Method and apparatus for reducing power consumption in a memory
bus ...
US Pat. 7000065 - Filed Jan 2, 2002 - Intel Corporation
The latch 151 captures its input from the output terminal of the sense
amplifier
102 in synchronization with the positive going edge of the delayed DQS
data ...
Zero mounting force solder-free connector/component and method
US Pat. 6817878 - Filed Dec 31, 2001 - Intel Corporation
The component 20 includes a latch element 23 configured as shown. The
latch
element 23 is shown inserted in the aperture 21. The component 20
further ...
High-speed, state-preserving, race-reducing, wide-pulsed-clock domino
design ...
US Pat. 6677783 - Filed Dec 31, 2001 - Intel Corporation
The latch 220 of one embodiment is a jam latch as shown in FIG. 2. For
other
embodiments, a different type of latch may be used to latch the output
of the
...
[APPLICATION] Ferroelectric memory device and method of reading a
ferroelectric memory
US Pat. 10028182 - Filed Dec 21, 2001 - Intel Corporation
Such data latch is operative to capture data of sense amplifiers 76
upon their
... By capturing this data, the latch retains the data for delayed
output and
...
Low clock swing latch for dual-supply voltage design
US Pat. 6762957 - Filed Dec 20, 2001 - Intel Corporation
(57) ABSTRACT A dual-supply voltage latch includes a data input node
to receive
an input data, internal nodes to hold the input data, and an output
node to ...
Long setup flip-flop for improved synchronization capabilities
US Pat. 6642763 - Filed Dec 19, 2001 - Intel Corporation
At least one master latch resolves a metastable condition ol a
received data
signal ... signal which is received and then displayed by a slave
latch. ...
Method and apparatus for optimizing clock distribution to reduce the
effect ...
US Pat. 6934872 - Filed Dec 19, 2001 - Intel Corporation
50 fed to registers and latches such as generating latch 70 and The X-
axis of
the graph represents time where the num- a receiving latch 74. ...
Level converting latch
US Pat. 6563357 - Filed Dec 20, 2001 - Intel Corporation
In some embodiments, the CLK* signal is generated outside latch 200
and inverter
217 is omitted. The CLK and 25 CLK* signal also control transmission
gate ...
Flash device operating from a power-supply-in-package (PSIP) or from a
power ...
US Pat. 6639864 - Filed Dec 18, 2001 - Intel Corporation
The latch or register may be located within processor 20 or may ... It
is not
intended that the location of the latch or register be a limitation of
the ...
Transmission-gate based flip-flop
US Pat. 6642765 - Filed Dec 6, 2001 - Intel Corporation
One type of low-energy flip-flop is the master-slave latch pair. ...
The master
latch includes the first pair of parallel-connected inverters
210, ...
Ferroelectric memory input/output apparatus
US Pat. 6646903 - Filed Dec 3, 2001 - Intel Corporation
Two of the structures that allow k ^ individual devices assert the
BUSY si L
when this to occur are the address latch and the data latch These =B1e
&st ...
Method and apparatus for processing events in a multithreaded
processor
US Pat. 6857064 - Filed Nov 30, 2001 - Intel Corporation
The bits within the pending event register 204 for each thread are set
by the
event detector 188 that triggers a latch which sets the appropriate
bit within
...
Modeling of phase synchronous circuits
US Pat. 6584597 - Filed Nov 27, 2001 - Intel Corporation
8 25 latch 230, or between primary output k and transparent latch
240. .... As
indicated by its phase label, for latch 230 the value of input signal
c (once
...
Method to reduce glitch energy in digital-to-analog converter
US Pat. 6507295 - Filed Oct 24, 2001 - Intel Corporation
... a first latching the data signal with a latch to generate a
latched field
effect transistor coupled between the first output signal; and a
current sink;
...
Pipelined, universal serial bus parallel frame delineator and NRZI
decoder
US Pat. 7003599 - Filed Oct 24, 2001 - Intel Corporation
latch logic 604. In one embodiment, the number of concurrent
comparators 602 is
... The latch logic 604 receives the position vector from the
concurrent ...
Method for improved electrostatic discharge protection
US Pat. 6570225 - Filed Oct 22, 2001 - Intel Corporation
Although it does not foreclose such a condition, the device of the
invention
does not rely on the latch-up event to increase the current
dissipation at a ...
High frequency inductive lamp and power oscillator
US Pat. 6949887 - Filed Oct 12, 2001 - Intel Corporation
The RF current should be kept sufficiently low to avoid causing the
PIN diode to
latch into an open state because of the rectified current. ...
Method and apparatus for a multi-purpose domino adder
US Pat. 6839729 - Filed Sep 28, 2001 - Intel Corporation
Accordingly, when the input selection gate 602 receives domino
signals, the
domino signals 604 are provided to a latch 630 in parallel with
providing of the
...
Generating pulses for resetting integrated circuits
US Pat. 6952122 - Filed Sep 28, 2001 - Intel Corporation
The use of the latch 14 may be advantageous in some embodiments since
it is ...
This pulls the output 47b harder towards ground and tends to latch the
pulse ...
Registering events while clocking multiple domains
US Pat. 6954872 - Filed Sep 28, 2001 - Intel Corporation
... a control logic coupled to said interface to determine 30 whether
a clocking
signal to latch an event at the designated location is absent, ...
Releasing functional blocks in response to a determination of a
supply ...
US Pat. 6661264 - Filed Sep 28, 2001 - Intel Corporation
... the reset signal may be latched off. 24 Claims, 4 Drawing Sheets
72
FUNCTIONAL BLOCK IN DECISION LOGIC PULSE GEN. PULSED RS-LATCH R
RESET ...
Montgomery multiplier with dual independent channels
US Pat. 6732133 - Filed Sep 28, 2001 - Intel Corporation
In one embodiment, Channel selection register 450 is a latch
containing a one-
bit selection value that is propagated through the PEs along with
control ...
Circuit compensation technique
US Pat. 6509780 - Filed Sep 10, 2001 - Intel Corp.
The output of the analog comparator 150 is inputted to the latch 160
which
receives a latching signal f sample. The output of the latch 160 is
inputted to
...
System and method for delaying a strobe signal based on a slave delay
base ...
US Pat. 6918048 - Filed Sep 6, 2001 - Intel Corporation
... B2 * 6/2003 Zumkehr 702/ Slave Strobe Delay Device Latch JI eov \ V
\ ... _Jx
Latch 33B J \ } 365, -\ |l Oscillator -* -=BB p =97 Rop r Flop Pop r
Flop ...
Quad pumped bus architecture and protocol
US Pat. 6807592 - Filed Aug 10, 2001 - Intel Corporation
According to an embodiment, all agents drive their common clock
outputs and
latch their common clock inputs on the bus clock rising edge. ...
Quad pumped bus architecture and protocol
US Pat. 6601121 - Filed Aug 10, 2001 - Intel Corporation
Full dock allowed for signal propagation BCLK A# B# Assert A# Full
clock allowed
for logic delays Latch A# Latch B# Assert B# ...
Latch circuit
US Pat. 6469953 - Filed Aug 8, 2001 - Intel Corporation
Assume, for example, that the canonical form of the latch circuit is
being used,
meaning that logic block 202 is formed of a single n-type
transistor, ...
Controlling signal states and leakage current during a sleep mode
US Pat. 6882200 - Filed Jul 23, 2001 - Intel Corporation
The latch is programmable with a value. The latch communicates the
input signal
to the output terminal in response to the circuit not being in a sleep
mode ...
Comparison circuit and method for verification of scan data
US Pat. 6883127 - Filed Jun 28, 2001 - Intel Corporation
The integrated circuit denned in claim 1 that further latch to retain
a signal
state at an automatically selected includes a strobe circuit to
strobe ...
On-die automatic selection of manipulated clock pulse
US Pat. 6892157 - Filed Jun 28, 2001 - Intel Corporation
Each scan latch 126; is to save a signal state of a coupled portion of
the -^
circuit-under-test 110 in response to a latch command. The scan
latches 126; ...
Flip-flop having multiple clock sources and method therefore
US Pat. 6944784 - Filed Jun 29, 2001 - Intel Corporation
In this mode of operation, flip-flop 50 may be referred to as a pulsed
latch
because a clock signal having a relatively short ...
Method and apparatus for testing an I/O buffer
US Pat. 6889350 - Filed Jun 29, 2001 - Intel Corporation
The output signals flop e and 30 flop o are input to a 2-latch bank
with mixing
circuit 130 (similar to the 8-latch circuit 126 shown in FIG. 1). ...
Dynamic bus repeater with improved noise tolerance
US Pat. 6940313 - Filed Jun 29, 2001 - Intel Corporation
The repeater of claim 6, wherein the repeater is operative to latch a
LOW signal
on the intermediate node during the evaluate mode in response to
receiving ...
Input circuit with non-delayed time blanking
US Pat. 6552570 - Filed Jun 27, 2001 - Intel Corporation
Accordingly, RS latch 50 outputs a logic high Qbar signal during the
reset ...
RS latch 51 operates as follows. When R=3DS=3D0, transistors 95P and 95N
are both
...
[APPLICATION] Cache architecture with redundant sub array
US Pat. 9894638 - Filed Jun 27, 2001 - Intel Corporation
Each of the bus repeaters is a synchronous device such a clocked flop,
buffer,
or latch. Bus repeaters are inserted in the data transmission path
because a ...
VDD modulated SRAM for highly scaled, high performance cache
US Pat. 6556471 - Filed Jun 27, 2001 - Intel Corporation
In the VDM SRAM cell, as in standard cells, read stability is
determined by the
conductance ratio (beta ratio) of the access device to the latch
device. ...
Method and apparatus including heuristic for sharing TLB entries
US Pat. 6728858 - Filed Jun 27, 2001 - Intel Corporation
Latch 633 includes both data portion 614 for storing virtual address
data (VAD)
... The latch 637 includes, in data portion 624, a corresponding
physical ...
Cache architecture for pipelined operation with on-die processor
US Pat. 6631444 - Filed Jun 27, 2001 - Intel Corporation
Each of the bus repeaters is a synchronous device such a clocked flop,
buffer,
or latch. Bus repeaters are inserted in the data transmission path
because a ...
Fault resilient booting for multiprocessor system using appliance
server ...
US Pat. 7251723 - Filed Jun 19, 2001 - Intel Corporation
... a watchdog timer including a watchdog timer reset input coupled to
a fourth
of the plurality of control signals; a latch including a set
input, ...
Method and apparatus for performing deferred transactions
US Pat. RE38388 - Filed Jun 14, 2001 - Intel Corporation
6 is comparison logic which receives four bits of the token (from a
latch, for
instance) representing the agent ID and compares them to the agent's
ID to ...
Adaptive de-skew clock generation
US Pat. 6917660 - Filed Jun 4, 2001 - Intel Corporation
In another embodiment, output buffer 29 may comprise latches, with a
specified
edge of the clock signal from multiplexer 28 being used to latch the
data ...
High performance impulse flip-flops
US Pat. 6366147 - Filed Jun 4, 2001 - Intel Corporation
... 327/208 Chen et al 327/211 Alexander 327/203 OTHER PUBLICATIONS
Hamid
Partovi, et al. "Flow-Through Latch and Edge-Triggered Flip-Flop
Hybrid Elements
", ...
Method and apparatus for control calibration of multiple memory
modules ...
US Pat. 6629225 - Filed May 31, 2001 - Intel Corporation
The output 260 of the gated receiver 234 is fed to the clock input of
a latch
238 via a delay block 236. The delaying of the forwarded strobe signal
260 in
...
Multi-bit scoreboarding to handle write-after-write hazards and
eliminate ...
US Pat. 6408378 - Filed May 31, 2001 - Intel Corporation
Execution unit has the ability to latch the input it receives from MUX
12 and
... It also must to latch the operation to be performed when that
operation is
...
Double data rate dynamic logic
US Pat. 6441648 - Filed May 9, 2001 - Intel Corporation
... a first dynamic latch connected to the first node to provide a
first output
signal; and a second dynamic latch connected to the second node to
provide a ...
Slide rail attachment
US Pat. 6588866 - Filed Apr 27, 2001 - Intel Corporation
... received in corresponding keyhole slots in the rail web, and then
slid along
the slots until a spring latch snaps into place, without the use of
tools. ...
Method and apparatus for an electromechanically controlled
electronic ...
US Pat. 6461185 - Filed Apr 20, 2001 - Intel Corporation
In the release capability to allow for undocking in case of a system
engaged
position hooks 22 and 24 are positioned to latch failure. ...
Algorithm for finding vectors to stimulate all paths and arcs through
an LVS ...
US Pat. 6557149 - Filed Apr 4, 2001 - Intel Corporation
Typically, in order to determine setup and hold times, a circuit is
simulated
while sweeping the clock to find where a latch fails. Because of the
number of
...
Clocked sense amplifier flip flop with keepers to prevent floating
nodes
US Pat. 6396309 - Filed Apr 2, 2001 - Intel Corporation
... a latch to latch a data bit from said first and second dynamic
data nodes
into an internal storage location of said latch in response to a
control ...
Multistage configuration and power setting
US Pat. 6792489 - Filed Mar 30, 2001 - Intel Corporation
1 receives fuse voltage from the input/output (I/O) circuitry and
support
components do not latch configuration states; FIG. 5 shows timing of
signal
states ...
Interchangeable and modular I/O panel
US Pat. 6550877 - Filed Mar 30, 2001 - Intel Corporation
Additionally depicted is the engagement of mounting tab 108 with latch
110. ...
5, mounting tab 108 joins with latch 110, without the use of tools or
screws ...
Memory addressing structural test
US Pat. 6721216 - Filed Mar 30, 2001 - Intel Corporation
... transmitting an address to the address decoder to be decoded, and
triggering
the signature analyzer to latch the state ol the word lines. ...
Memory cell structural test
US Pat. 6757209 - Filed Mar 30, 2001 - Intel Corporation
-65=B0 no latch the fact that a substantial difference was found during
test ...
Method and apparatus for aligning and orienting polarization
maintaining ...
US Pat. 6907147 - Filed Mar 30, 2001 - Intel Corporation
A device 74, such as a latch, can enable the knob 64 to be held in the
closed
position or to be released into the opened position. ...
Selective forwarding of a strobe based on a predetermined delay
following a ...
US Pat. 6456544 - Filed Mar 30, 2001 - Intel Corporation
The output of the comparator directly feeds the clock input of a
latch. A data
input of the latch receives a level-translated version of the data
signal. ...
Flip-flop circuit having dual-edge triggered pulse generator
US Pat. 6608513 - Filed Mar 28, 2001 - Intel Corporation
... Dual edge-triggered circuits latch data on both the rising
selectively pass
inverted signal of the input clock signal as and falling edges of the
clock. ...
Digital leakage compensation circuit
US Pat. 6396305 - Filed Mar 29, 2001 - Intel Corporation
This charge leakage can cause a dynamic circuit to malfunction (eg,
latch the
output signal with an incorrect logic level) when the logic level of
the input
...
Method and apparatus for de-skewing a clock using a first and second
phase ...
US Pat. 6810486 - Filed Mar 28, 2001 - Intel Corporation
The apparatus of claim 11, further comprising a buffer w
G . , , , , , , , , c .
, G . , . . ,. , ri , first memory element to latch data from the
first ...
Method and apparatus for high frequency data transmission and
testability in ...
US Pat. 7057672 - Filed Mar 29, 2001 - Intel Corporation
The data transmission path includes a data latch 315 and a transmitter
320,
wherein the data latch 315 is local to the transmitter 320. The data
latch 315
...
System and method for selecting and loading configuration data into
a ...
US Pat. 6925558 - Filed Mar 29, 2001 - Intel Corporation
in any latch 21 -x will cause corresponding latch 22-x to be set,
making its
output a logic 1. A logic '0' in any latch 21-x will cause
corresponding latch
...
Flash memory low-latency cache
US Pat. 6836816 - Filed Mar 28, 2001 - Intel Corporation
10 a mam memory; an address latch logic to receive addresses of
requested data;
a cache memory coupled to the main memory to store recently accessed
data ...
Microprocessor design support for computer system and platform
validation
US Pat. 7032134 - Filed Mar 28, 2001 - Intel Corporation
INSTR. LIBRARY 320 I ADDRESS MANIP. 340 Addr TRANS. LATCH 310 FIG. 300
ARBITER/
j60 Trans. Type EEC 340 VALIDATION FUB 300 130 ...
Method and apparatus to provide real-time access to flash memory
features
US Pat. 6549482 - Filed Mar 23, 2001 - Intel Corporation
In a typical operation of the flash memory 20, an address signal
(shown as ADDR)
is coupled into an address latch 23. The address signal once latched
is ...
Bus system
US Pat. 6510477 - Filed Mar 21, 2001 - Intel Corporation
The driver cut-off and latch-back circuitry must also be able to
operate from a
very ... Implementations of the latch-back controller circuit, drive
enable ...
System and apparatus for increasing the number of operations per ...
US Pat. 6779045 - Filed Mar 21, 2001 - Intel Corporation
The flash memory devices typically incorporate basic 30 command code
and flash
primitives code to latch and program, erase, or read a memory
cell. ...
Synchronous clock generator for integrated circuits
US Pat. 6741107 - Filed Mar 8, 2001 - Intel Corporation
The first and second input signal may be complimentary. 20 Claims, 3
Drawing
Sheets DATA CLOCK CLOCK 21 LATCH CIRCUIT 20 -26 ...
Enabling components to be removed without hot swap circuitry
US Pat. 6964576 - Filed Mar 8, 2001 - Intel Corporation
The door 14 may be latched closed by a latch 30 along its upper edge
in one
embodiment. Passing through the door 14 is an access port 21 to enable
a power
...
Generating and using calibration information
US Pat. 6665624 - Filed Mar 2, 2001 - Intel Corporation
It is possible for pre-charged compensate for the energy attenuation
associated
with elec- 1=B0 latch 928 and signal _RST to be in inconsistent
states, ...
Calibrating return time for resynchronizing data demodulated from a
master ...
US Pat. 6779123 - Filed Feb 28, 2001 - Intel Corporation
Pre-charged latch 928 reshapes received pulses example, in system 200
in ... It
is possible for pre-charged latch 928 and compensate for the
energy ...
Clock reshaping
US Pat. 6498512 - Filed Feb 27, 2001 - Intel Corporation
In addition to amplification, amplifiers 920 may latch their outputs
with
appropriate timing signals to provide sufficient pulse widths for
succeeding ...
Checkerboard parity techniques for a multi-pumped bus
US Pat. 6742160 - Filed Feb 14, 2001 - Intel Corporation
... A[35:24]# 0 REQ[4:0]# D- ADDR[23:3]# XOR 705 XOR 715 RESET LATCH
Z10 LATCH
720 AP1 -n APO FIG. ...
Response and data phases in a highly pipelined bus architecture
US Pat. 6804735 - Filed Feb 14, 2001 - Intel Corporation
... of the data transfer from the driving agent to any receiver should
be less
than or equal to one bus clock cycle minus the input latch setup
time. ...
Electromagnetic coupler socket
US Pat. 6533586 - Filed Dec 29, 2000 - Intel Corporation
... base 710 such that each latch 10 734 and 744 may be pivoted inward
toward
coupler region 715 to engage circuit board 352 and outward from
coupler region
...
Converting sensed signals
US Pat. 6879056 - Filed Dec 29, 2000 - Intel Corporation
The output of the comparator 231 is provided to the latch 234, in one
embodi-
... The latch 234 transfers a "0" or "1" at its input terminal to its
output ...
Differential simultaneous bi-directional receiver
US Pat. 7054374 - Filed Dec 29, 2000 - Intel Corporation
7) in ZC+ will cause the form, the data signal is toggled once for
every edge
detected. first stage =A70 512a of the edge+ pipeline 512 to latch that
Neither
...
Kicker for non-volatile memory drain bias
US Pat. 6744671 - Filed Dec 29, 2000 - Intel Corporation
From drain bias 120, memory cell signals are transferred to pre-sense
amplifier
160, which provides data to post-sense amplifier latch 170. ...
Wireless display systems, styli, and associated methods
US Pat. 6717073 - Filed Dec 29, 2000 - Intel Corporation
AOR v^.=99 4 WIRELESS INTERFACE TO COMPUTER ULTRASONIC -SA/D LATCH
SENSOR ^444 I \
420 422 ^418 i FILTER DETECTOR.
Electromagnetic coupler alignment
US Pat. 6836016 - Filed Dec 29, 2000 - Intel Corporation
... of base 710 such that each latch 734 and 744 may be pivoted inward
toward
coupler region 715 to engage circuit board 352 and outward from
coupler region
...
Automatic clock calibration circuit
US Pat. 6326830 - Filed Dec 29, 2000 - Intel Corporation
Control bus 109 is associated with circuitry (not shown) which decodes
local bus
addresses to provide latch enable signals to clock source 101, ...
Data and strobe repeater having a frequency control unit to re-time
the data ...
US Pat. 6373289 - Filed Dec 26, 2000 - Intel Corporation
... signal by essentially a propagation time of the latch; k) driving
the
latched upstream data signal; and 1) driving the delayed re-timing
signal, ...
Computing system with volatile lock architecture for individual
block ...
US Pat. 6446179 - Filed Dec 26, 2000 - Intel Corporation
In one embodiment of the present invention, the clock inputs to the
registers
302 to 306 are driven by latch control signals. The latch control
signals are
...
Method and apparatus for detecting strobe errors
US Pat. 6715111 - Filed Dec 27, 2000 - Intel Corporation
Because the received strobe 410 does not rise to the high state until
after t=3D4,
the counter is not incremented and the buffer does not latch the value
from ...
Method and apparatus to ensure proper voltage and frequency
configuration ...
US Pat. 6874083 - Filed Dec 22, 2000 - Intel Corporation
... 388) as an enable latch, between the processor 302 and the voltage
regulator
304. ...
Method and apparatus for preventing and recovering from TLB corruption
by ...
US Pat. 6718494 - Filed Dec 22, 2000 - Intel Corporation
Read and latch both data and parity. Check latched data parity.
Invalidate TLB
entry. Invoke Page Walker to reinstall TLB entry. Continue. ...
Mult-mode I/O interface for synchronizing selected control patterns
into ...
US Pat. 6715094 - Filed Dec 20, 2000 - Intel Corporation
Referring again to the serialization state machine 510, the latch
is ... This is
somewhat arbitrary, as the only real requirement is the latch enable
is ...
Method and apparatus for error detection/correction
US Pat. 6711712 - Filed Dec 21, 2000 - Intel Corporation
For this particular embodiment latch stage 345 may comprise staging
latches, ...
Likewise, latch stage 355 may comprise staging latches, data-
signature ...
Frequency phase detector for differentiating frequencies having small
phase ...
US Pat. 6538517 - Filed Dec 19, 2000 - Intel Corporation
In an embodiment, latch keeper 44, a cross-coupled inverter, having
inverter 46
and inverter 48, maintains a value at logic NAND gate 50 and logic
NAND gate ...
Flip flop circuit
US Pat. 6459316 - Filed Dec 8, 2000 - Intel Corporation
327/203 "Power Saving Latch" IBM Technical Disclosure Bulletin, pp
65-66, vol.
... Partovi, H., et al., "Flow-Through Latch and Edge-Triggered Flip-
Flop ...
[APPLICATION] Pipelined compressor circuit
US Pat. 9733482 - Filed Dec 8, 2000 - Intel Corporation
... when a high signal is on the control input of the clocked
inverter, the
latch will retain its value even if decoupled from the remainder of
the circuit,
...
Domino logic with low-threshold NMOS pull-up
US Pat. 6486706 - Filed Dec 6, 2000 - Intel Corporation
But, the speed of such logic is limited by the time it takes to pre-
charge the
dynamic circuit node that provides the data signal to the static CMOS
latch ...
Symbol-based signaling for an electromagnetically-coupled bus system
US Pat. 6697420 - Filed Nov 15, 2000 - Intel Corporation
Pre-charged latch 928 reshapes received pulses for the convenience of
succeeding
... It is possible for pre-charged latch 928 and signal RST to be
in ...
Electromagnetically-coupled bus system
US Pat. 6625682 - Filed Nov 15, 2000 - Intel Corporation
In addition to amplification, amplifiers 920 may latch their outputs
with
appropriate timing signals to provide 35 sufficient pulse widths for
succeeding
...
Telephone system for formatting caller ID information into a form
useable by ...
US Pat. 6463138 - Filed Nov 13, 2000 - Intel Corporation
The data is then moved off the hard disk and put into the memory of
the CPU 882
and then moved through the ISA bus interface 446 and latch 890 via
DMA ...
I/O device testing method and apparatus
US Pat. 6671847 - Filed Nov 8, 2000 - Intel Corporation
Data-out latch and output driver form the data output path for output
data on
node ... Input receiver and data-in latch form the input path for
input data ...
Flip-flop circuit with transmission-gate sampling
US Pat. 6509772 - Filed Oct 23, 2000 - Intel Corporation
In flip-flop 250, signal Q is provided directly by latch node L, and
signal Q*
is provided on node 266 of memory unit 222. In general, function of
flip-flop
...
Dual-port buffer-to-memory interface
US Pat. 6742098 - Filed Oct 3, 2000 - Intel Corporation
At T5n, the primary memory controller transitions DQS again, causing
buffer 122
to latch DI a2. After a delay to allow the inputs to register 128 to
settle, ...
Valid bit generation and tracking in a pipelined processor
US Pat. 6754808 - Filed Sep 29, 2000 - Intel Corporation, Analog
Devices, Inc.
The valid bit output from the decode stage may be stored in a latch in
an
address ... The valid bit may be held in the latch by a latch enable
circuit in
...
Apparatus, method and system for a ratioed NOR logic arrangement
US Pat. 6448818 - Filed Sep 29, 2000 - Intel Corporation
IF is shown an exemplary reset/set (R/S) latch arrangement 1340, which
may be
used for the reset/set latch arrangements 1300 and 1320 of FIG. ...
Glitch detection circuit for outputting a signal indicative of a
glitch on a ...
US Pat. 6745337 - Filed Sep 29, 2000 - Intel Corporation
During use, if there is a glitch on the strobe signal 108, 5 there is
a chance
that the receiving agent (memory controller hub) may latch onto a
wrong data ...
Apparatus, method and system for providing LVS enables together with
LVS data
US Pat. 6323698 - Filed Sep 29, 2000 - Intel Corporation
Also, during this pre-charge phase, an input latch couples an input
data signal
to the domino logic arrangement. During a second phase of the clocking
cycle ...
Universal impedance control for wide range loaded signals
US Pat. 6445316 - Filed Sep 29, 2000 - Intel Corporation
The code 215 is held in latch 235 while compensation controller 210 is
in a
recalibration ... The impedance of buffers is updated when latch 235
is opened.
...
Method and apparatus for a low latency source-synchronous address
receiver ...
US Pat. 6748513 - Filed Sep 20, 2000 - Intel Corporation
... two inputs: one is a source synchronous address strobe directing
the
receiver to latch the address and store data, while the other is a
protocol
signal, ...
Buffering data transfer between a chipset and memory modules
US Pat. 6820163 - Filed Sep 18, 2000 - Intel Corporation
The at least one buffer is then configured to properly latch the data
at 502.
This allows the first and second interfaces to operate independently
but in ...
Buffer to multiply memory interface
US Pat. 6553450 - Filed Sep 18, 2000 - Intel Corporation
... and configuring the at least one buffer to properly latch data
being
transferred between the chipset and the memory modules. ...
Memory interface having source-synchronous command/address signaling
US Pat. 6449213 - Filed Sep 18, 2000 - Intel Corporation
2 includes a latch 30, a first redrive circuit 32 coupled between the
latch and
the ... The latch 30 samples the address/ command signals responsive
to the ...
Storage element with stock node capacitive load
US Pat. 6483363 - Filed Sep 15, 2000 - Intel Corporation
When latch 200 is loading, and the input pass gate is on, no
additional ... 3A
and 3B schematically show the state of latch 200 when it is
loading, ...
Storage element with switched capacitor
US Pat. 6504412 - Filed Sep 15, 2000 - Intel Corporation
20 Various nodes in latch 200 are shown driven by complementary
signals ...
Latch 200 is loaded when pass gate 204 is closed as a result of the
clock signal
...
Digital clock skew detection and phase alignment
US Pat. 6622255 - Filed Sep 13, 2000 - Intel Corporation
A latch made of NAND gates 222 and 223 is preceded by reset circuitry
that is
based upon N-channel devices 226 and 227. When reset is
deasserted, ...
Nonvolatile writeable memory with preemption pin
US Pat. 6633950 - Filed Sep 1, 2000 - Intel Corporation
Claims, Drawing Sheets SUSPEND, PIN WE ~ COMMAND DECODER, ERASE LATCH
PROGRAM
LATCH | __L^j READ STATUS LATCH COMMAND REGISTER COMMAND RESET ...
Apparatus and method for protecting critical resources against soft
errors ...
US Pat. 6654909 - Filed Jun 30, 2000 - Intel Corporation
... the parity and valid bits register 119 stores the parity bit that
is to be
used to compare with the computed 30 parity bit in the result latch
130. ...
Pulsed circuit topology including a pulsed, domino flip-flop
US Pat. 6496038 - Filed Jun 30, 2000 - Intel Corporation
The circuit of claim 1 wherein the latch comprises a set-dominant
latch if the
domino logic gate is an n-type domino logic gate and wherein the
latch ...
Method and apparatus for pulsed clock tri-state control
US Pat. 6346828 - Filed Jun 30, 2000 - Intel Corporation
... tri-state driver sources to drive the tri-state bus; and receiving
the
latched data signal from the tri-state bus and storing it into a
receiver latch
...
Method and apparatus for an integrated circuit having flexible-
ratio ...
US Pat. 7007187 - Filed Jun 30, 2000 - Intel Corporation
8 illustrates one embodiment of the assertion logic and a set/reset
latch of a
writer element. FIG. 9 illustrates one embodiment of the response
logic of a ...
System and method for silent data corruption prevention due to
next ...
US Pat. 6658621 - Filed Jun 30, 2000 - Intel Corporation
U Display Device Bus Decode unit 125 1 7D I /U 150 / ( ) latch
Keyboard ' J73
Reservation 155 Station 175 Hard Copy Latch 173 ...
Global clock self-timed circuit with self-terminating precharge for
high ...
US Pat. 6531897 - Filed Jun 30, 2000 - Intel Corporation
1 also includes a 30 set-dominant latch (SDL) 130, and a clock delay
circuit 132
(which may also be referred to as a latch protection circuit) that
is ...
Dynamically updating impedance compensation code for input and output
drivers
US Pat. 6624659 - Filed Jun 30, 2000 - Intel Corporation
During this time, the p-latch is transparent, allowing the p-code to
pass ...
The p-latch and n-latch enable signals are asserted at a point in the
middle ...
Method and apparatus for integrated flip-flop to support two test
modes
US Pat. 6446229 - Filed Jun 29, 2000 - Intel Corporation
The logic circuit then can be operated in 40 normal fashion and the
result of
the operation is stored in its respective latch. A scan out operation
serially
...
Digital variable-delay circuit having voltage-mixing interpolator
and ...
US Pat. 6348826 - Filed Jun 28, 2000 - Intel Corporation
In test mode, it can also be shifted up to 270 degrees in N increments
to
measure the effective input latch setup and hold timings. ...
Register file scheme
US Pat. 6430083 - Filed Jun 28, 2000 - Intel Corporation
... the feedback paths in the register-file latches may be restored to
"latch"
the swapped contents, that is stabilize the signals in the
latches. ...
Impedance control system for a center tapped termination bus
US Pat. 6356105 - Filed Jun 28, 2000 - Intel Corporation
... set-top boxes, network hubs, wide area network (WAN) switches, or
any other
system which uses a latch type mechanism for other embodiments.
FIG. ...
Method and apparatus for non-volatile memory bit sequence program
controller
US Pat. 6418059 - Filed Jun 26, 2000 - Intel Corporation
Each bit slice 410 may further include a latch 412. Alternatively, a
latch, such
as latch 412' in the alternate embodiment the bit sequence
programming ...
Synchronous interface for a nonvolatile memory
US Pat. 6564285 - Filed Jun 14, 2000 - Intel Corporation
A clock input is a part of the interface. An address latch enable pin
is present
to indicate that a valid address is :o present on the address bus. ...
Core clock correction in a 2/n mode clocking scheme
US Pat. 6268749 - Filed May 31, 2000 - Intel Corporation
The pad cell comprises a pulsed latch 1001 coupled to receive
input ... The
output of this pulsed latch 1001 is coupled to the input of a latch
1002. ...
Method and circuit for loading data and reading data
US Pat. 6421280 - Filed May 31, 2000 - Intel Corporation
The latch enable signals 310, 312, 314 and 316 enable data to be
stored in the
data buffers 320, 322, 324 and 326, respectively. The flip flop
circuits 250 ...
Small aperture latch for use with a differential clock
US Pat. 6362657 - Filed May 31, 2000 - Intel Corporation
Paper white direct view display
US Pat. 6639572 - Filed Apr 10, 2000 - Intel Corporation
The display of claim 5, wherein said array of hinges comprises an
array of
bistable latch hinges that provide the stability mechanism, said
bistable latch
...
Apparatus, method and system for determining application runtimes
based on ...
US Pat. 6564175 - Filed Mar 31, 2000 - Intel Corporation
... ii=3D=97 QUEUE y OUTPUT SIZE-^25^ UNDER 22c/ TRANSACTION
IDENTIFIERS^252 . TEST
' ' ' ^~ IDENTIFIER/FREQ. COUNT LATCH ...
Apparatus, method and system for counting logic events, determining
logic ...
US Pat. 6647349 - Filed Mar 31, 2000 - Intel Corporation
300- BEGIN 310 Initialize Count Latch(es) 320 Add incrementing value
(such as 1
for clocking or output size for throughput) to lower bit range of
count ...
Method, apparatus, and system for high speed data transfer using
source ...
US Pat. 6621760 - Filed Mar 31, 2000 - Intel Corporation
The first delayed receive clock signal is used to latch incoming data
from the
memory unit. Claims, 6 Drawing Sheets BOO 5 RATIO 9/2 * 300MHZ DIVIDE
3 ...
Parallel terminated bus system
US Pat. 6519664 - Filed Mar 30, 2000 - Intel Corporation
The driver cut-off and latch-back circuitry must also be able to
operate from a
very ... Implementations of the latch-back controller circuit, drive
enable ...
System for protecting strobe glitches by separating a strobe signal
into ...
US Pat. 6622256 - Filed Mar 30, 2000 - Intel Corporation
The first delayed strobe 306 is coupled to the latch enable logic 326,
328 in
the WSM 320. The second delayed strobe 308 coupled to the pointer
logic 322, ...
Method and apparatus for modeling and circuits with asynchronous
behavior
US Pat. 6973422 - Filed Mar 20, 2000 - Intel Corporation
Netlist model 27 also includes virtual delay elements 24 and 26, which
are
described as flip-flops that latch the values at 55 inputs in24
and ...
Method and apparatus to reduce power consumption on a bus
US Pat. 6282665 - Filed Mar 6, 2000 - Intel Corporation
One skilled in the art will appreciate that the section 605 may be
designed to
function as a conventional set-reset (SR) latch, the specifics of
which have ...
Multiple input bit-line detection with phase stealing latch in a
memory design
US Pat. 6278627 - Filed Feb 15, 2000 - Intel Corporation
By placing the NFET pair 710 and 711 at the top of the pull down path
the charge
time required is slightly longer but the latch function is more
reliable. ...
Generalized pre-charge clock circuit for pulsed domino gates
US Pat. 6633992 - Filed Dec 30, 1999 - Intel Corporation
Device 100 includes a logic circuit 130, a clock macro 104, a latch
102, two
inverters 122, 124, and an AND gate 120. The logic circuit 130 further
includes
...
Parallel phase locked loops skew measure and dynamic skew and jitter
error ...
US Pat. 6469550 - Filed Dec 30, 1999 - Intel Corporation
The apparatus as in claim 3, wherein the skew measure circuit further
comprises
a reset circuit to reset the first latch :5 and the second latch when
both ...
Method and apparatus for differential strobing
US Pat. 6453373 - Filed Dec 30, 1999 - Intel Corporation
... signal to latch the data. 4Q The use of two strobe signals
(instead of one)
for strobing data eliminates the jittering problem associated with
single ...
Apparatus, method and system for a logic arrangement having
mutually ...
US Pat. 6329857 - Filed Dec 30, 1999 - Intel Corporation
... through the corresponding latch or sense amplifier arrangement
before it is
properly latched or sensed, thereby resulting in corrupted or "lost"
data. ...
Method and apparatus for implementing high speed signals using
differential ...
US Pat. 6697896 - Filed Dec 31, 1999 - Intel Corporation
Storage device 249 also contains latch circuit 240 and latch circuit
242. ... In
one embodiment, storage device 249 contains multiple latch circuits
240-242 ...
Quad pumped bus architecture and protocol
US Pat. 6609171 - Filed Dec 29, 1999 - Intel Corporation
... of the data transfer from the driving agent to any receiver should
be less
than or equal to one bus clock cycle minus the input latch setup
time. ...
Flat-panel display drive using sub-sampled YCBCR color signals
US Pat. 6507350 - Filed Dec 29, 1999 - Intel Corporation
... Color," available from The formulas may be implemented on the flat-
panel
display using known circuitry elements such as active circuitry to
latch the Y,
...
SERDES (serializer/deserializer) time domain multiplexing/
demultiplexing ...
US Pat. 6628679 - Filed Dec 29, 1999 - Intel Corporation
The apparatus of claim 4, each of said N latches and output latch
comprising a
flip-flop. ... A time domain multiplexer apparatus comprising: a first
latch,
...
Shifting an input signal from a high-speed domain to a lower-speed
domain
US Pat. 6668298 - Filed Dec 29, 1999 - Intel Corporation
... and an output of said flip flop 5 serves as said latch output and
is also
inputted to said first input of said multiplexer, and wherein said
second ...
Soft error resistant circuits
US Pat. 6366132 - Filed Dec 29, 1999 - Intel Corporation
3 illustrates a latch circuit 30 according to some embodiments of
the ... 3, a
latch circuit 30 including a storage node N14, a feedback node N18
and, ...
Skew correction circuit
US Pat. 7315599 - Filed Dec 29, 1999 - Intel Corporation
A data receiver comprising: buffers, each buffer to latch a different
data bit
signal; a first circuit to: for each data signal, generate at least
one ...
Processing multiply-accumulate operations in a single cycle
US Pat. 6611856 - Filed Dec 23, 1999 - Intel Corporation
... RECEIVES PACKED-DATA INSTRUCTION MAC CONTROL LOGIC 52 SENDS SIGNAL
TO LATCH
FLIP-FLOPS 6a-6c AND MUXs 8a-8c _y I_ 406 SIXTEEN BITS OF MULTIPLICAND
A ARE ...
Method and apparatus for testing an integrated circuit having an
output-to ...
US Pat. 6693436 - Filed Dec 23, 1999 - Intel Corporation
... the plurality of latches comprising four latches, a first set of
the latches
to latch data at a corresponding latch input in response to a
transition of ...
Pulsed clock signal transfer circuits with dynamic latching
US Pat. 6667645 - Filed Dec 20, 1999 - Intel Corporation
p-first dynamic latch blocks logic signals from propagating through
the rest of
the logic ... According to the invention, only when the dynamic latch
(eg, ...
Backgate biased synchronizing latch
US Pat. 6512406 - Filed Dec 16, 1999 - Intel Corporation
Ifc, when the CLOCK input 113 is low and the DATA input 112 is high,
the latch
circuit output 107 is set high (when the RESET input 102 is
high). ...
Method and apparatus to delay signal latching
US Pat. 6690221 - Filed Dec 3, 1999 - Intel Corporation
... LATCH FIG. 5 L_/ '2 V 13 DATA / 110 FIG. ...
Soft error rate tolerant latch
US Pat. 6380781 - Filed Nov 1, 1999 - Intel Corporation
Detecting states of signals
US Pat. 6298450 - Filed Oct 20, 1999 - Intel Corporation
For example, in one embodiment, the programmable transistors can be
included in
the output latch 100. Alternatively, the programmable transistors can
be ...
Method and apparatus to monitor a characteristic associated with
an ...
US Pat. 6172546 - Filed Oct 8, 1999 - Intel Corporation
By thus selectively activating delay loads in the data path from the
output
latch 100 to the output pad 112, a variable signals the (BO, Bl, B2)
and (CO,
...
Method and apparatus for configuring an I/O buffer having an
initialized ...
US Pat. 6606705 - Filed Sep 15, 1999 - Intel Corporation
11 The output latch function of the voltage divider circuit in
this ...
Alternative embodiments can use other ways of implementing the latch
mechanism.
...
Frequency divider and method
US Pat. 6229357 - Filed Sep 2, 1999 - Intel Corporation
The frequency divider of claim 1 wherein the latch is comprised of
cross-coupled
inverters. 4. The frequency divider of claim 1 further comprising: a
first ...
Apparatus for fast logic transfer of data across asynchronous clock
domains
US Pat. 6172540 - Filed Aug 16, 1999 - Intel Corporation
The clock enabling circuit provides the first clock signal to the
first latch
when the signal indicates occurrence of the triggering edge of the
second ...
Control circuit for clock enable staging
US Pat. 6166564 - Filed Jul 9, 1999 - Intel Corporation
For example, many microprocessors latch data and flip-flop devices
synchronous
... This extra constraint requires additional latch circuits (shown as
dashed
...
Flip-flop circuit
US Pat. 6181180 - Filed Jun 28, 1999 - Intel Corporation
Partovi, H., et al., "Flow-Through Latch and Edge-Triggered Flip-Flop
Hybrid
Elements", IEEE International Solid-State Circuits Conference, 7996
Digest of
...
Reference-free single ended clocked sense amplifier circuit
US Pat. 6137319 - Filed Apr 30, 1999 - Intel Corporation
Sense amplifier 36 includes a clocked tail current source transistor
(Mil), and
differential pair transistors (M12 and M13) a cross-coupled inverters
latch ...
Method and apparatus for stalling OTB domino circuits
US Pat. 6271684 - Filed Apr 8, 1999 - Intel Corporation
2, the input to the domino pipeline arrives from a latch 230 that
receives a ...
An enable signal 543 is applied to the data input of latch 540 with
enable ...
Duty cycle corrector for a random number generator
US Pat. 6643374 - Filed Mar 31, 1999 - Intel Corporation
8 next bit is loaded into latch 304, it will be clocked through latch
306 before
the next time that modulo-2 counter 602 will output count 1 to AND
gate 309 ...
Method and apparatus for generating a reference voltage signal derived
from ...
US Pat. 6278312 - Filed Feb 24, 1999 - Intel Corporation
A latch 326 then receives data from the sense amp 324 for use by other
portions
of the component 302. A control circuit 315 is coupled to control ...
Method and apparatus for generating 2/N mode bus clock signals
US Pat. 6104219 - Filed Oct 13, 1998 - Intel Corporation
A signal (A) is output from latch 1601B of the pad cell 1601 to one
input of an
... The output (C) of AND gate 1603 is coupled to the input of latch
1604, ...
CMOS latch design with soft error immunity
US Pat. 6026011 - Filed Sep 23, 1998 - Intel Corporation
Slaveless synchronous system design
US Pat. 6185720 - Filed Jun 19, 1998 - Intel Corporation
The apparatus also includes a logic coupled to receive the first data
output,
wherein the logic includes a second data output without using a slave
latch ol
...
Apparatus and method for detecting and handling self-modifying
code ...
US Pat. 6405307 - Filed Jun 2, 1998 - Intel Corporation
25 Claims, Drawing Sheets COMPARE incoming store address with contents
of bt3
latch and bt4 latch. ...
Method and apparatus using volatile lock architecture for individual
block ...
US Pat. 6209069 - Filed May 11, 1998 - Intel Corporation
The latch control signals are generated by a group configuration
command takes
effect on the block specified latch control signal 310 that enables
latching ...
Method and apparatus for floating point operations and format
conversion ...
US Pat. 6282554 - Filed Apr 30, 1998 - Intel Corporation
According to this embodiment, floating point unit 300 determines how
to latch an
incoming number by determining the state of the incoming signal
that ...
Fast bi-directional tristateable line driver
US Pat. 6175253 - Filed Mar 31, 1998 - Intel Corporation
... and a latch circuit having an output and having an input connected
to the
buffer circuit output, the latch circuit input having an input voltage
equal ...
Mechanical latch for an electronic cartridge
US Pat. 6208514 - Filed Feb 17, 1998 - Intel Corporation
Field of the Invention The present invention relates to a retention
latch which
secures an electronic cartridge to a guide rail of an electrical
assembly. ...
Method and apparatus for selecting operating voltages in a backplane
bus
US Pat. 5958056 - Filed Nov 28, 1997 - Intel Corporation
Power controller 26 enables control logic 99 to latch data from data
10 15 ...
As shown, control logic 99 is enabled by enable line 141 to latch data
from ...
Flash memory including a mode register for indicating synchronous
or ...
US Pat. 6026465 - Filed Jun 18, 1997 - Intel Corporation
In one embodiment, interface logic 640 will latch and examine all bits
written
to flash memory 640 during write operations and provide this parity
data ...
Method and apparatus for maintaining cache coherency in a computer
system ...
US Pat. 5890200 - Filed Apr 4, 1997 - Intel Corporation
11 12 A latched address bus (addr latch) 544 is coupled to each of the
plurality
... Additionally address bus 540 and addr_ 30 latch bus 544 each
provide an ...
Method and apparatus for accessing a cache using index prediction
US Pat. 5956752 - Filed Dec 16, 1996 - Intel Corporation
The cache memory of claim 5 wherein the first latch output is coupled
to provide
an address input to a memory array. 8. A circuit comprising: a memory
array ...
Core clock correction in a 2/N mode clocking scheme
US Pat. 5834956 - Filed Sep 6, 1996 - Intel Corporation
A signal (A) is output from latch 1601B of the pad cell 1601 to one
input of an
... The output (C) of AND gate 1603 is coupled to the input of latch
1604, ...
Low current reduced area programming voltage detector for flash memory
US Pat. 5594360 - Filed Feb 27, 1996 - Intel Corporation
The latch mode VCC ramp detector 30 also includes a start-up circuit
90 for
initially biasing the node 80 and a drain bias control circuit 100 for
providing
...
Method for eliminating multiple output switching timing skews in a
source ...
US Pat. 5774001 - Filed Dec 20, 1995 - Intel Corporation
The I/O generator generally comprises a latch, combinational
logic, ... The I/O
generator's latch is coupled between the internal processor clock
generated ...
Method and circuitry for preconditioning shorted rows in a
nonvolatile ...
US Pat. 5377147 - Filed Aug 11, 1993 - Intel Corporation
The operation of VPX Select circuitry 554 eludes eight latch and
comparator
circuits 700a-700A, is summarized by Table 2. one for each data
bit, ...
Shift register programming for a programmable logic device
US Pat. 4930098 - Filed Dec 30, 1988 - Intel Corporation
The memory cells are each coupled to its corresponding latch or shift
register
for latching a stored state of the memory cell. Shift registers
provide for ...
Article: 143571There are two other areas where I still see latches being used in ASIC designs: - In clock gating cells to ensure no glitches on the clock. - For large, regular, register files, to minimize area. Cheers, JonArticle: 143572
Gabor <gabor@alacron.com> wrote: (snip) > Xilinx XST ALWAYS encodes state machines one-hot unless you force > it to use your encoding (see synthesis options). Are you sure > that your dynamic portion has a reset term for starting up the > FSM logic? One of my favorite approaches is to add a post-reset > state that just continues onto the idle state. Then when reset > is released all of the states other than idle cannot be reached > until the post-reset state has become inactive, effectively a > synchronous reset release. If you use the state register somewhere else, such as a module output, then it shouldn't convert to one hot. (or it should properly decode the one hot value.) The bug was with Quartus many years ago, I believe fixed while I was still working on that project. It was a simple four state FSM to accept data one byte at a time and output to a 32 bit FIFO. The state variable was two bits, and Quartus gave me the low two bits of the one hot register. Do you mean XST will give you the wrong output in that case? It seems that what Quartus expected was a case statement to select the next state and a separate case statement to do whatever you wanted to do in that state. I wrote mine as a single case statement and, in addition, used the state variable outside the module. -- glenArticle: 143573
Hi, I just had to debug separately a system which usually works connected to the asynchronous parallel bus (address and data busses, read and write strobe). The system was connected to my development box via the JTAG interface (used to configure FPGAs), so I wanted to use the same interface to access the internal registers. I wanted a portable solution, working without any proprietary drivers. Therefore I have used the urJTAG + Python to implement the PC-side. The FPGA side for Xilinx chips has been written in VHDL, using the BSCAN_SPARTAN3 component, however it shouldn't be difficult to port it to Altera chips eg. using the code described here: http://groups.google.pl/group/alt.sources/browse_thread/thread/58acd8b31ea5bd0d (alt.sources "Python+urJTAG code to access Virtual JTAG in Altera FPGAs") I've implemented 3 types of the controller: jtag_bus_ctl_1.vhd - uses two instructions USER1 (to send address and R/W mode) and USER2 (to send/receive data) jtag_bus_ctl_2.vhd - uses only one instruction USER1 and single shift register to send both address+R/W mode and data. This one allows to optimize access by receiving the read data, when the next command is being sent jtag_bus_ctl_3.vhd - like version 2, but with "autoincrement" mode. You can send address once, and then read/write multiple data from consecutive addresses. The source code with more detailed description amd simple Python demos is available here: http://groups.google.pl/group/alt.sources/browse_thread/thread/38186c49dc5cf32e (alt.sources "FPGA internal bus controller driven by JTAG interface ") as PUBLIC DOMAIN code. (remember to select more_options->Show_original, when geting it from Google archive - othervise Python code indenting may be destroyed). I hope that this code may be useful for someone. -- Best regards, WojtekArticle: 143574
kadhiem_ayob wrote: > I am trying to simulate in Modelsim XE web edition a verilog only project > consisting of top level and few components. All components have same time > resolution units and have wire type outputs. The problem is that Modelsim > doesn't recognise the drive of any component's output connected to > another's input. Yet it accepts the drive when connected to an output at > toplevel itself. http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_body.html#8.0%20Module%20Instances
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