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Rudi, Have you read http://www.xilinx.com/support/documentation/user_guides/ug198.pdf page 151, where they refer to the PIPE documents which details this functionality? On page 21 of the gen2 document from Intel, and the next pages. http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf The test equipment reporting a receiver present does a lot of work (based on my reading of the Intel document), and there would be many ways that in the FPGA you might not be performing the required sequence per the standard. AustinArticle: 143801
On Oct 27, 4:23=A0am, austin <aus...@xilinx.com> wrote: > Rudi, > > Have you read > > http://www.xilinx.com/support/documentation/user_guides/ug198.pdf > > page 151, where they refer to the PIPE documents which details this > functionality? > > On page 21 of the gen2 document from Intel, and the next pages. > > http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf > > The test equipment reporting a receiver present does a lot of work > (based on my reading of the Intel document), and there would be many > ways that in the FPGA you might not be performing the required > sequence per the standard. > > Austin Hi Austin, thank you for you reply. I did read ug198 and pipe 2.0 specs. That's what makes it so frustrating ! I feel that I follow both specifications to the letter, and it still does not work. Could there be an undocumented step ? Some assumption that is not obvious ? Thank you ! rudiArticle: 143802
On Oct 26, 6:49 pm, Dave Pollum <vze24...@verizon.net> wrote: > On Oct 26, 3:29 am, Smi <smi...@gmail.com> wrote: > > > Hello > > > Want to write a code in VHDL for aynschronous to synchronous > > communication. From PC i need to take asynchronous data and convert to > > synchronous data in code.. if any one knw abt this let me know its > > very urgent please let me know the details > > Are you talking about a UART? If you are, check on opencores.org > HTH > -Dave Pollum ya UART only ........have u worked on it? if so give some brief ideaArticle: 143803
Hello all,
I am hoping that someone had solved problem similar to mine. I want to run
tcl
script in planAhead to create project, run some implementation and import
the results into the floorplan. So I run these commands:
hdi::run add -name impl_1 -project project_bft_core_hdl -floorplan
floorplan_1 -parentRun synth_2 -part {xc5vsx35tff665-1} -flow {ISE 11}
-strategy {Strategy #1};
hdi::run launch -project project_bft_core_hdl
-runs impl_1 -jobs 2 -scriptsOnly no -allPlacement no -dir
/.../Projects/project_bft_core_hdl/project_bft_core_hdl.runs;
hdi::run import -name impl_1 -project project_bft_core_hdl -placement yes
Unfortunatelly I receive error:
ERROR: Run 'impl_1' appears to not be finished. Unable to import
Is there any way how to force tcl script to wait for the result of the
dhi::run launch?
Thanks for every answer
Jan
From matthieu.d.u.m.m.y.michon@gmail.com Tue Oct 27 00:45:16 2009
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Date: Tue, 27 Oct 2009 09:45:16 +0100
From: Matthieu Michon <matthieu.d.u.m.m.y.michon@gmail.com>
Newsgroups: comp.arch.fpga
Subject: Re: ISe 10.1 nightmare bug
Message-Id: <20091027094516.048badf0.matthieu.d.u.m.m.y.michon@gmail.com>
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On Mon, 26 Oct 2009 12:43:12 -0700 (PDT)
Mawa_fugo <ccon67@netscape.net> wrote:
> On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
> > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> >
> > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t=
he
> > > entire project just corrupted - when "rerun all" it TOOK the topmodule
> > > source from "nowhere" - nomatter how you change your topmodule it
> > > still lock the topmodule source fom that mystery source
> >
> > > Oh my goodness
> >
> > The "Cleanup Project Files" under the "Project" menu can solve many of
> > these problems.
> >
> > kevin
>=20
> Thanks for suggestion - it does something difference when I tried to
> clean the project but it still lock the source from "nowhere"
Hi
I also had to deal with the same kind of issue with ISE 10.1SP3: after chec=
king out a project stored on a version control system (SVN), the top-level =
mark disappeared and the "Set as Top Module" action was disabled. Needless=
to say that I tried all the usuals (amongst other things: "Cleanup Project=
Files", "Check Syntax", removing/adding again the top-level source file) w=
ithout much success.
After a few minutes fiddling around, I tried to change the "Top-Level Sourc=
e Type" project property from HDL to EDIF and back to HDL --define long sho=
ot ;) -- and YGTBK! my top-level came back!
> THis is a night mare
At the very least it must scare some EEs away from FPGA design ;) One a m=
ore serious note, I'm still hoping that five years after the buyout of Hier=
Design, the people behind Planahead didn't get brainwashed and would sugge=
st the rest of the Design Software Division at Xilinx to put some common se=
nse in ISE (such as using --again-- a text format for the project file).
--=20
Matthieu Michon <prenom.nom@gmail.com>
Article: 143804On Oct 27, 10:45=A0am, Matthieu Michon <matthieu.d.u.m.m.y.mic...@gmail.com> wrote: > On Mon, 26 Oct 2009 12:43:12 -0700 (PDT) > > > > > > Mawa_fugo <cco...@netscape.net> wrote: > > On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote: > > > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while,= the > > > > entire project just corrupted - when "rerun all" it TOOK the topmod= ule > > > > source from "nowhere" - nomatter how you change your topmodule it > > > > still lock the topmodule source fom that mystery source > > > > > Oh my goodness > > > > The "Cleanup Project Files" under the "Project" menu can solve many o= f > > > these problems. > > > > kevin > > > Thanks for suggestion - it does something difference when I tried to > > clean the project but it still lock the source from "nowhere" > > Hi > > I also had to deal with the same kind of issue with ISE 10.1SP3: after ch= ecking out a project stored on a version control system (SVN), the top-leve= l mark disappeared and the "Set as Top Module" action was disabled. =A0Need= less to say that I tried all the usuals (amongst other things: "Cleanup Pro= ject Files", "Check Syntax", removing/adding again the top-level source fil= e) without much success. > > After a few minutes fiddling around, I tried to change the "Top-Level Sou= rce Type" project property from HDL to EDIF and back to HDL --define long s= hoot ;) -- and YGTBK! my top-level came back! > > > THis is a night mare > > At the very least it must scare some EEs away from FPGA design =A0;) =A0O= ne a more serious note, I'm still hoping that five years after the buyout o= f Hier Design, the people behind Planahead didn't get brainwashed and would= suggest the rest of the Design Software Division at Xilinx to put some com= mon sense in ISE (such as using --again-- a text format for the project fil= e). > > -- > Matthieu Michon <prenom....@gmail.com>- Hide quoted text - > > - Show quoted text - 11.x uses text format again so at least once Xilinx has listened, well I bet they just had no choice as the binary project file in their implementation is nothing else and pure nightmare AnttiArticle: 143805
Hi finally -- first units of U2TOOL-ICE are shipped to the clients (and are arrived at destination also), general availability will soon follow too, specifications: small white box with short USB cable attached, inside is FT245RQ and SMD module with Silicon Blue ice65L04 module that does configure itself from 2M byte dataflash. FPGA does configure with "bootstrap" configuration that creates Flash access interface to the configuration flash. As ice65L04 support 4 configurations to be choosen using "warmboot" primitive then 3 configurations can be selected by the user. as "user IO" there is one RJ45 jack with 3.3V supplied from USB (separate LDO) and 6 I/O pins. Two LEDs (red and blue) can also be controlled by the FPGA. The gadget can be used as complete FPGA development system, as it can reload new FPGA hardware configurations without any external programming cables. It can also be configured as versatile USB - Interface implementing various functions in the FPGA All schematic and protocol interface documentation will be released. Also many FPGA design will be available with full sources, and ready to download image files. I hope that the general availability will be soon too, ah yes, not to forget, the all gadget is designed by Antti with the "low cost" in mind, so we doing all we can from the manufacturers side to offer this gadget at very low end user price. Ok, I can say it out also now, we are targetting MSRP (manufacturers suggested retail price) of $39 the inside pictures of the gadget are in some last brain issues if someone wants to see what really is inside.. Antti PS due to server crash and hdd clean sweep all my domains are currently either not accessible or show template pages, nothing serious, all we up and running with new content soon!Article: 143806
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-1158463234-1256636389=:16040 Content-Type: TEXT/PLAIN; charset=ISO-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE On Thu, 15 Oct 2009, Rickman posted: |----------------------------------------------------------------------| |"On Oct 15, 7:57=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> | |wrote: | |> | |> So far I have received no response to the email which I sent to | |> announceme...@Altera.com on October 12th, 2009. I am not pleased. | |> | |> Colin Paul Gloster | | | |Did you give them your email address?" | |----------------------------------------------------------------------| Yes. I do not know why Altera does not seem to have pointed this out in this thread, so I reproduce an email from Altera below. Rick Collins posted: |----------------------------------------------------------------------| |" Is this spam or you just don't | |like the fact that it is much harder for them to meet the regulations | |of dozens of countries than it is to only make the offer in the single| |country where most of their business comes from? | | | |[..] | | | |But if you are just complaining that you don't like the way they've | |set up their offer, why waste your time with that thought... like why | |am I wasting my time with *this* thought? | | | |Rick" | |----------------------------------------------------------------------| I do not like the way that the offer was set up. Regards, Colin Paul Gloster On Wed, 21 Oct 2009, Altera emailed: |----------------------------------------------------------------------| |"Dear Colin Paul Gloster: | | | |We apologize for the confusion and inconvenience that the email | |promoting our kit sweepstakes caused you. In your case we did not have| |country information in your record so you received the email. Again, | |my apologies for the mistake. | | | |We also saw your email thread on Net News. Please know that Altera | |does not take email addresses from our tech support site or the Altera| |Forum. All addresses on our email list are "opt-in," which means that | |a box was checked saying that the registrant prefers to receive emails| |from us. | | | |Our records show that you have been a subscriber since 2003, and I | |hope that you have found the information that we've sent you over the | |past 6 years to be useful. However, if you would like to unsubscribe, | |please reply to this email with that information and I'll remove you | |permanently and immediately. | | | |Thank you for your interest in Altera. Please let me know if you have | |any further questions or concerns. | | | |Sincerely, | | | |Sandi Lindenkohl Email Marketing Manager | | | |P.S. The "from" address for our email campaigns receives thousands of | |auto replies per week so it is very difficult to filter out an email | |with this type of question. This is why you did not get a reply right | |away." | |----------------------------------------------------------------------| --8323328-1158463234-1256636389=:16040--Article: 143807
Hi, I inserted some circuit in source code for debug. These code aren't ported as output and is monitored by chipscope. In order not to be optimised by synplify, I use attribute syn_preserve to keep these registers. But synplify still removed these signals, I can't insert these signals into cdc file in ISE. Is there a way to keep these signals so that it can be used in chipscope? for example,Article: 143808
On 10=D4=C227=C8=D5, =CF=C2=CE=E77=CA=B143=B7=D6, skyworld <chenyong20...@g=
mail.com> wrote:
> Hi,
>
> I inserted some circuit in source code for debug. These code aren't
> ported as output and is monitored by chipscope. In order not to be
> optimised by synplify, I use attribute syn_preserve to keep these
> registers. But synplify still removed these signals, I can't insert
> these signals into cdc file in ISE. Is there a way to keep these
> signals so that it can be used in chipscope?
>
> for example,
signal a : std_logic;
signal b : std_logic;
attribute syn_preserve : boolean;
attribute syn_preserve of a : signal is true;
attribute syn_preserve of b: signal is true;
process(clk, reset)
begin
a <=3D ...
b <=3D ...
end
signal a/b are internal signals and not sent to output port. how can I
keep these signals? thanks.
Article: 143809On Oct 27, 12:54=A0am, Smi <smi...@gmail.com> wrote: > On Oct 26, 6:49 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > On Oct 26, 3:29 am, Smi <smi...@gmail.com> wrote: > > > > Hello > > > > Want to write a code in VHDL for aynschronous to synchronous > > > communication. From PC i need to take asynchronous data and convert t= o > > > synchronous data in code.. if any one knw abt this let me know its > > > very urgent please let me know the details > > > Are you talking about a UART? =A0If you are, check on opencores.org > > HTH > > -Dave Pollum > > ya UART only ........have u worked on it? if so give some brief idea Do a Google search on UART FPGA, or like I said, look for UARTs on opencores.org. -Dave PollumArticle: 143810
On Tue, 27 Oct 2009 04:43:25 -0700, skyworld wrote: > Hi, > > I inserted some circuit in source code for debug. These code aren't > ported as output and is monitored by chipscope. In order not to be > optimised by synplify, I use attribute syn_preserve to keep these > registers. But synplify still removed these signals, I can't insert > these signals into cdc file in ISE. Is there a way to keep these signals > so that it can be used in chipscope? > > for example, Rather then rely on syn_preserve I generally use a spare pin and then OR all the signals that I want to protect together and connect the OR to the pin.Article: 143811
Rudi, I do not know. That is the purpose of documentation, to document. One thought I had is that this works by measuring the difference between an open line, and a terminated line, at the transmitter. Such analog measurement techniques only work for an exact fixed length of the PCIe bus connection. If you are using extension cables, or an extension card, the length of the transmission lines may affect the measurement. AustinArticle: 143812
skyworld, The attribute to prevent objects to be removed away is syn_keep. In your VHDL example, simply replace syn_preserve by syn_keep. Note: syn_preserve has a bit of misleading name. This attribute disables sequential optimizations on sequential elements. Such optimizations include redundancy removal (removal of duplicate registers). However, unused registers are still removed away even in presence of syn_preserve. Cheers, - gaelArticle: 143813
On Oct 27, 9:47=A0pm, austin <aus...@xilinx.com> wrote: > Rudi, > > I do not know. =A0That is the purpose of documentation, to document. > > One thought I had is that this works by measuring the difference > between an open line, and a terminated line, at the transmitter. =A0Such > analog measurement techniques only work for an exact fixed length of > the PCIe bus connection. =A0If you are using extension cables, or an > extension card, the length of the transmission lines may affect the > measurement. > > Austin Hi Austin, I feel that in this case the documentation fails to document. The description for Receiver Detect is a) incomplete; and, b) scattered throughout unrelated sections. My understanding is that this logic works by measuring the time it takes to charge the coupling capacitor. (It is present and correct value on my board). Cable length should not matter. Receiver Detection is described starting on page 151 in ug198. It clearly shows a waveform diagram, where I enter powermode 2'b10, and the next cycle assert TXDETECTRX. And some time later, I will get PHYSTATUS, that validates the value on RXSTATUS lines. But than, in table 5-14 (page 111) I find out that TXELECIDLE also must be asserted to initiate Receiver Detection. And again, in other parts of the document, I find that when changing powermode, I need to wait for PHYSTATUS to indicate that power mode has been changed (change completed). I have tried the original description as on page 151, as well, as adding the other bits I found out. And still, I consistently get "No Receiver Detected". The other side has no problem detecting my hardware. Is there somebody who knows this stuff inside out and can shed some light on how to make this work ? Thanks, rudiArticle: 143814
On 26 =D0=BE=D0=BA=D1=82, 17:33, doug <x...@xx.com> wrote: > Alex wrote: > > On 25 =D0=BE=D0=BA=D1=82, 01:46, doug <x...@xx.com> wrote: > > >>Alex wrote: > > >>>On 24 =D0=BE=D0=BA=D1=82, 00:56, doug <x...@xx.com> wrote: > > >>>>Alex wrote: > > >>>>>On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote: > > >>>>>>Nico Coesel wrote: > > >>>>>>>-jg <jim.granvi...@gmail.com> wrote: > > >>>>>>>>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote: > > >>>>>>>>>So, having decided every-cycle precision is not practical, you h= ave to > >>>>>>>>>decide over what time you need this 0.1Hz ? > >>>>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cyc= les of > >>>>>>>>>1.00us, and one cycle of > > >>>>>>>>( oops, Hit the wrong button...) > >>>>>>>>Finishing that example: in a pure digital domain > > >>>>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate > >>>>>>>>99,999 cycles of 1,00us and one cycle 10ns less > >>>>>>>>Frequency is then Cycles.Time =C2=A0=3D3D > > >>>>>>>>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001 > > >>>>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples o= f > >>>>>>>>greater than 100ms, with a 10ns timebase. > >>>>>>>>That certainly is FPGA doable. > > >>>>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for > >>>>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less = than > >>>>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clo= ck > >>>>>>>cycles each frame. > > >>>>>>This works fine for locking to a fixed frequency over a narrow rang= e > >>>>>>and many of us have used it. =C2=A0The deficiency of it is that it = is fine > >>>>>>for digital clocks but is bad for analog signals. =C2=A0For generat= ing > >>>>>>arbitrary frequencies, you are better off using a DDS. =C2=A0The DD= S is even > >>>>>>available as a coregen element for Xilinx (the digital part anyway)= . > > >>>>>Xilinx DDS Compiler seems suitable for my project. > > >>>>You have to decide if the jitter from this is ok for you. The ways > >>>>of reducing the jitter include increasing the clock rate or by > >>>>feeding the output through a d/a converter with a baseband > >>>>filter. The idea is to use the filter to do the interpolation of > >>>>the zero crossings. This is one of the real nice features of the > >>>>Analog Devices parts. You can clock at hundreds of MHz and for > >>>>low frequency outputs, the jitter is effectively zero. > > >>>>You never told us what kind of output you really want. A digital > >>>>clock? =C2=A0An audio test signal? =C2=A0What are the distortion and > >>>>purity specs? > > >>>Hi doug, > > >>>I actually have not decided yet on distortion and purity specs.. > >>>The output has to be a train of amplitude modulated RF pulses whose > >>>amplitude, waveform, phase, frequency could be set specifically for > >>>each pulse. Frequency can be in range from 100 kHz to about 50 MHz > >>>(adjustable in steps equal to 0.1 Hz). > > >>Your life will be a lot simpler if you just use the Analog Devices > >>parts. The AD9954 or AD9956 will do most of what you want. You will > >>need an external D/A for the amplitude control. > > > Hi doug, > > > As a biginner I wonder - what is main difference between design > > methods used in Analog Device line of products and FPGA-based > > solutions? As I understand, Analog Device products are all signal > > processors, i.e. their hardware cannot be changed meanwhile FPGA-based > > solutions allow re/programming of hardware and software as well. Is my > > understanding correct? > > Yes, but a bit misleading. The FPGA consists of a large array of > similiar pieces which can be arranged to do what you want. The AD > parts are dedicated chips which have sections which can be > made from and FPGA and sections which cannot. The D/A converter > in the AD parts is an analog device which cannot be built > in an FPGA. =C2=A0Also, the AD devices work at a higher clock rate > than you will get in an inexpensive FPGA. You hopefully are just > doing a school project where the experience will do you some > goog rather than trying to make a commercial product. Hi doug, Thank you very much for reply. Well, what tutorial or book you would suggest to read as a start with DDS using AD parts?Article: 143815
On Tue, 27 Oct 2009 09:13:48 -0700 (PDT) Alex <victous@gmail.com> wrote: > [megasnip] > > Hi doug, > > Thank you very much for reply. > Well, what tutorial or book you would suggest to read as a start with > DDS using AD parts? Just go over to Analog Devices's site and follow over to their DDS chips. Unless the lastest site redesign's done even more horrible things than I've found, there should be a link to their DDS primer, which I recall as actually being quite good. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 143816
On 26 =CF=CB=D4, 18:51, austin <aus...@xilinx.com> wrote: > Implementing a full DDFS in the FPGA, with sine lookup table AND D/A > converter, > > Is only required when you want (need) a sine wave. > > If you want (need) a regular clock, then taking the carry out of the > accumulator/register is just fine. > > Yes, the adjustment is one whole clock period, so the peak to peak > jitter is the same as the clock period of the DDFS. > > As an example, there is often a "real time clock" project for various > simple FPGA boards, that use the on-board crystal oscillator. =9AGiven > the crystal oscillator is +/- 50 ppm (or worse), the clock will > probably gain, or lose time in 24 hours, such that you will notice it > is not keeping very good time. > > An exercise is to replace the "one second" clock to the real time > clock (for seconds, minutes, hours, day, etc.) with a 36 bit DDFS > running from 50 MHz. =9ANow, to adjust the one second time click, you > can increment, or decrement, the phase accumulator constant (frequency > setting) until you are as close as how have the patience to play with > it. =9AI did this when I took the FPGA class here at Xilinx ten years > ago. > > I used DDFS extensively to produce network clocks in the synchronous > network hierarchy products I alluded to earlier. =9AI used a 48 bit > DDFS, as I wanted the synthesizer step size to be far less than the > stratum 1 reference accuracy (+/- 1E-11 for cesium/GPS, and 3.5E-15 > for lsb of 48 bit DDFS). > > The 48 bit DDFS was at the heart of the entire product line (inside a > Xilinx FPGA). > > Since this was for the network, and jitter is really important, I > would take the output of the DDFS, send it outside the FPGA, to a PLL > using a VCXO, which had a ten to thirty second time constant (pole) in > the feedback loop. The result was immeasurable jitter on the T1, or E1 > clock references (the only jitter present was from the data itself, > and the framing pattern). > > As is often the case, one doesn't need everything in the Analog > Devices DDS chip (but it is incredibly convenient, and a very good > choice if you are building a variable frequency oscillator for a radio > receiver!). > > http://www.nitehawk.com/rasmit/vna_dds/dds-x_v1_6.pdf > > You could do the same thing with a FPGA, but you would need an > external D/A converter (as well as all the analog filtering which the > AD DDS also requires). Hi austin, Thank you for very helpful reply! :-)Article: 143817
On 27 =CF=CB=D4, 18:16, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Tue, 27 Oct 2009 09:13:48 -0700 (PDT) > > Alex <vict...@gmail.com> wrote: > > [megasnip] > > > Hi doug, > > > Thank you very much for reply. > > Well, what tutorial or book you would suggest to read as a start with > > DDS using AD parts? > > Just go over to Analog Devices's site and follow over to their DDS > chips. Unless the lastest site redesign's done even more horrible > things than I've found, there should be a link to their DDS primer, > which I recall as actually being quite good. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Well, maybe materials at their site are not the best to start from for a beginner. For example, when I had started to learn FPGA with Xilinx Microblaze board the best (for me) tutorial I had found was not Xilix' materials but Dennis Silage's book "Embedded Design Using Programmable Gate Array".Article: 143818
hi all, i am using spartan 3e starter kit and i want to save the data captured from onboard adc(14 bit word) to a text file...at the moment i use edk and write my results on the screen through rs232 using microblaze...how i can save the data in a text file? i tried by using fprintf but i get the following errors: TestApp_Memory_microblaze_0/src/TestApp_Memory.c:53: warning: assignment makes pointer from integer without a cast /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: region ilmb_cntlr_dlmb_cntlr is full (TestApp_Memory_microblaze_0/executable.elf section .text) /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .init [00000050 -> 00000077] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .fini [00000078 -> 00000097] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .rodata [00000098 -> 00000a23] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .sdata2 [00000a24 -> 00000a27] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .data [00000a28 -> 00000f5b] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .ctors [00000f5c -> 00000f63] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .dtors [00000f64 -> 00000f6b] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .eh_frame [00000f6c -> 00000f6f] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .jcr [00000f70 -> 00000f73] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .bss [00000f78 -> 00000feb] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .heap [00000fec -> 000011ef] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: section .stack [000011f0 -> 000015ef] overlaps section .text [00000050 -> 00010627] /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: TestApp_Memory_microblaze_0/executable.elf: section .text lma 0x50 overlaps previous sections /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: TestApp_Memory_microblaze_0/executable.elf: section .fini lma 0x78 overlaps previous sections /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld: TestApp_Memory_microblaze_0/executable.elf: section .rodata lma 0x98 overlaps previous sections /opt/Xilinx/11.1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/crtend.o:(.init+0x0): relocation truncated to fit: R_MICROBLAZE_32_PCREL_LO against `.text' collect2: ld returned 1 exit status make: *** [TestApp_Memory_microblaze_0/executable.elf] Error 1 Done! Any suggestions? Is it possible to do it using vhdl?Article: 143819
On 27 =D0=BE=D0=BA=D1=82, 19:31, doug <x...@xx.com> wrote: > Alex wrote: > > On 27 =C3=8F=C3=8B=C3=94, 18:16, Rob Gaddi <rga...@technologyhighland.c= om> wrote: > > >>On Tue, 27 Oct 2009 09:13:48 -0700 (PDT) > > >>Alex <vict...@gmail.com> wrote: > > >>>[megasnip] > > >>>Hi doug, > > >>>Thank you very much for reply. > >>>Well, what tutorial or book you would suggest to read as a start with > >>>DDS using AD parts? > > >>Just go over to Analog Devices's site and follow over to their DDS > >>chips. Unless the lastest site redesign's done even more horrible > >>things than I've found, there should be a link to their DDS primer, > >>which I recall as actually being quite good. > > >>-- > >>Rob Gaddi, Highland Technology > >>Email address is currently out of order > > > Well, maybe materials at their site are not the best to start from for > > a beginner. > > > For example, when I had started to learn FPGA with Xilinx Microblaze > > board the best (for me) tutorial I had found was not Xilix' materials > > but Dennis Silage's book "Embedded Design Using Programmable Gate > > Array". > > Rob's advice is excellent and what I was going to suggest. The basic > idea of the dds is very simple as it is just a phase accumulator whose > time to rollover is a function of the phase step. This is why you get > such great resolution. =C2=A0The details of noise and jitter and ways aro= und > those are what take up all the work. Okay, then I will start from their site. Thank you!Article: 143820
Alex wrote: > On 27 ΟΛΤ, 18:16, Rob Gaddi <rga...@technologyhighland.com> wrote: > >>On Tue, 27 Oct 2009 09:13:48 -0700 (PDT) >> >>Alex <vict...@gmail.com> wrote: >> >>>[megasnip] >> >>>Hi doug, >> >>>Thank you very much for reply. >>>Well, what tutorial or book you would suggest to read as a start with >>>DDS using AD parts? >> >>Just go over to Analog Devices's site and follow over to their DDS >>chips. Unless the lastest site redesign's done even more horrible >>things than I've found, there should be a link to their DDS primer, >>which I recall as actually being quite good. >> >>-- >>Rob Gaddi, Highland Technology >>Email address is currently out of order > > > Well, maybe materials at their site are not the best to start from for > a beginner. > > For example, when I had started to learn FPGA with Xilinx Microblaze > board the best (for me) tutorial I had found was not Xilix' materials > but Dennis Silage's book "Embedded Design Using Programmable Gate > Array". Rob's advice is excellent and what I was going to suggest. The basic idea of the dds is very simple as it is just a phase accumulator whose time to rollover is a function of the phase step. This is why you get such great resolution. The details of noise and jitter and ways around those are what take up all the work.Article: 143821
On Oct 27, 2:16=A0pm, Dave Pollum <vze24...@verizon.net> wrote: > On Oct 27, 12:54=A0am, Smi <smi...@gmail.com> wrote: > > > > > On Oct 26, 6:49 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > > On Oct 26, 3:29 am, Smi <smi...@gmail.com> wrote: > > > > > Hello do they do not teach politeness in school anymore those days?? no please, no care for syntax, only "do my homework quickly and i do not want to search by myself"... > > > > > Want to write a code in VHDL for aynschronous to synchronous > > > > communication. From PC i need to take asynchronous data and convert= to > > > > synchronous data in code.. if any one knw abt this let me know its > > > > very urgent please let me know the details > > > > Are you talking about a UART? =A0If you are, check on opencores.org > > > HTH > > > -Dave Pollum > > > ya UART only ........have u worked on it? if so give some brief idea > > Do a Google search on UART FPGA, or like I said, look for UARTs on > opencores.org. > -Dave PollumArticle: 143822
> > >> THis is a night mare > > > At the very least it must scare some EEs away from FPGA design ;) If that is a nocturnal female horse it's not very scary :)Article: 143823
On 10=E6=9C=8827=E6=97=A5, =E4=B8=8B=E5=8D=889=E6=97=B631=E5=88=86, General= Schvantzkoph <schvantzk...@yahoo.com> wrote: > On Tue, 27 Oct 2009 04:43:25 -0700, skyworld wrote: > > Hi, > > > I inserted some circuit in source code for debug. These code aren't > > ported as output and is monitored by chipscope. In order not to be > > optimised by synplify, I use attribute syn_preserve to keep these > > registers. But synplify still removed these signals, I can't insert > > these signals into cdc file in ISE. Is there a way to keep these signal= s > > so that it can be used in chipscope? > > > for example, > > Rather then rely on syn_preserve I generally use a spare pin and then OR > all the signals that I want to protect together and connect the OR to the > pin. Hi, thanks for your reply. This is a big design and I don't have an option to connect debug signals to a pin. That is the reason why I use chipscope and use those annoying attributes.Article: 143824
On 10=D4=C227=C8=D5, =CF=C2=CE=E710=CA=B149=B7=D6, Gael Paul <gael.p...@gma= il.com> wrote: > skyworld, > > The attribute to prevent objects to be removed away is syn_keep. In > your VHDL example, simply replace syn_preserve by syn_keep. > > Note: syn_preserve has a bit of misleading name. This attribute > disables sequential optimizations on sequential elements. Such > optimizations include redundancy removal (removal of duplicate > registers). However, unused registers are still removed away even in > presence of syn_preserve. > > Cheers, > > - gael Hi, thanks for your reply. To my understanding, syn_keep is used to keep wire signals and syn_preserve is used to keep sequential signals. The signals I want to keep is generated in process(clk, reset), so it is a sequential one and should use syn_preserve. Why you think syn_keep should work? and why "unused registers are still removed away even in presence of syn_preserve" (the results show you're right here)? If so, it makes no sense to "generate" this attribute for synplify. Thanks.
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