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I am interested but this is very difficult. expecially doing it via the web. How do you know the other people are competent ? How do you know they can deliver ? How do I know you can do your part ? It's possible but highly unlikely. "nobody" <cydrollinger@gmail.com> wrote in message news:af91b38e-f167-4ffd-9c55-ae711fff2d05@z3g2000prd.googlegroups.com... > Whoa! let me reign this coach back! I am one man, educated in the > Gallatin Valley with an MSEE. I am having trouble keeping my doors > open in case a client who happens to have cash needs my ability to > solve the problem. Talking about scientists of world caliber and > mathematicians having advanced formulas needing to be calculated is > not even in the stadium of where I was thinking about playing, > period. > There exists problems needing solutions to which I have the skill set, > but pairing these items is not something I have had success. I exist > and I realize their are others that are experiencing the same, with > slightly or wildly different skill sets. Alone I can get things done > and have for a small set of clients, but together, even world wide, > with the internet we could do much more. Let me provide one scenario > that might be a quick and easy idea. I have an account on GURU.com > which tries to pair work to workers, but I look like every other > individual on the sight, India, Canada, and Wherever, so why choose > me? Now if a collection of individuals got together and developed an > account it looks more like a firm many hands producing on the capital > someone spends to get the job done. That is actually the way it works > together we get the job done quick and capable. But that is one idea > among one individual, now put several individuals together and see > what we can get done.Article: 143701
I assume the original poster was targeting commercial ventures ? Some history ... This has been attempted at OpenCOres.org. When I was still contributing to OpenCores (some 10 years ago), I too had this ideological view of a community of like minded people who would attempt to solve various problems. Very quickly, we realized that it was virtually impossible to do this in a "non-profit" way. One problem we faced where quality tools. We did receive a very kind donation from Cadance, in form of licenses for their NC-Verilog suite, I am still very grateful for that, even though the licenses where only very short time. Also, support became an issue when some users demanded support and bug fixes in a timely manner and to their satisfaction. There where attempts to create a "paid for" group. Flextronics Semiconductor retained a bunch of developers from OpenCores to develop free IPs, which it would use in it's SoC. That however, created somewhat of a conflict of interest. Even though Flextronics tried to be neutral, and let the developers do what they wanted, it was not realistic and eventually failed as well. The only way a co-op as suggested by the OP could work (IMHO) is if it is commercial with clear legal agreements and properly structured. These days I am actually implementing a structure as described by the OP. In my case, I have no desire to grow my company beyond what I can manage by myself. Never the less, often times my workload is far beyond of what I can handle alone, and I sub-contract excess work. So to take the OPs idea, what might be a useful thing to have is a database of various people with their capabilities ... Cheers, rudiArticle: 143702
Mike Treseler wrote: > Tier Logic wrote: > >> My favorite posts on here are the "Can you do my homework for me?" >> posts. > > or: > > "I have to do brain surgery using vhdl. Any ideas?" ;) Start reading through /all/ the VHDL technical committee public documents. Once your brain has melted and dribbled out your ears, surgery should be easy :-)Article: 143703
Hi All, I have noticed that FPGA board producers specify stability of clock on their FPGA boards but do not say anything about on what time scale this stability is given. For example, stability of clock on my Xilinx Spartan-3E 1600E Microblaze Development Board is specified as 50 ppm but how I could find out for what time scale this stability? Thank you.Article: 143704
On Oct 22, 8:49=A0am, Alex <vict...@gmail.com> wrote:
> Hi All,
>
> I have noticed that FPGA board producers specify stability of clock on
> their FPGA boards but do not say anything about on what time scale
> this stability is given.
>
> For example, stability of clock on my Xilinx Spartan-3E 1600E
> Microblaze Development Board is specified as 50 ppm but how I could
> find out for what time scale this stability?
>
> Thank you.
Hi Alex,
The Xilinx documentation probably got its information direct from the
oscillators' data sheets (e.g. http://www.spezial.cz/pdf/sg8002jf.pdf,
http://www.datasheetcatalog.org/datasheet/epson/SG8002DB.pdf). But
they don't go into any more detail about the timescale either
(although they do give the temperature range over which the
characterization is valid, as well as some stats on ageing
degredation). You could ask Epson support directly, I suppose, or
perhaps try also posting in sci.electronics.design.
There might be a standard methodology or rule of thumb for these
specifications, but I'm afraid I don't know what it is! But I would be
surprised if you ever needed to worry about 50ppm frequency drift in
an FPGA application. The DLL jitter will be an order of magnitude
greater than that...
Cheers,
-Ben-
Article: 143705May be he should trying 911! help or twitter would be a better option. On Oct 22, 11:48=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > Mike Treseler wrote: > > Tier Logic wrote: > > >> My favorite posts on here are the "Can you do my homework for me?" > >> posts. > > > or: > > > =A0"I have to do brain surgery using vhdl. Any ideas?" ;) > > Start reading through /all/ the VHDL technical committee public > documents. =A0Once your brain has melted and dribbled out your ears, > surgery should be easy :-)Article: 143706
Alex Sometimes you might find it easier to search for a particular clock generator chip. For instance the ICS8442 that we use in an add-on module and some of our development boards has a very good LVDS output and can go up to 700MHz. A number of board manufacturers have this clock generator on their boards. We also use the Cypress clock clock generator CY7C22394 on some products which isn't so good as the ICS8442 but much more flexible in frequency output. We also have a high stability oscillator option on our Mulldonnoch2 product http://www.enterpoint.co.uk/oem_industrial/mulldonnoch2.html. This particular product takes the form of an industrial EBX format motherboard but is still good as a development board. For development boards long term stability isn't often a much asked for parameter and that is probably why most companies don't particularly list it. Not specifying also allows some sourcing flexibility and avoids having to change board documentation as well. John Adair Enterpoint Ltd. On 22 Oct, 08:49, Alex <vict...@gmail.com> wrote: > Hi All, > > I have noticed that FPGA board producers specify stability of clock on > their FPGA boards but do not say anything about on what time scale > this stability is given. > > For example, stability of clock on my Xilinx Spartan-3E 1600E > Microblaze Development Board is specified as 50 ppm but how I could > find out for what time scale this stability? > > Thank you.Article: 143707
Hi Ben, Thank you for reply. I actually worry about clock's time stability because I want to design FPGA-based oscillator whose frequency can be set in 0.1 Hz steps. Whether 50 ppm clock's stability is good enough to be used for such design?Article: 143708
On 22 =CF=CB=D4, 15:17, John Adair <g...@enterpoint.co.uk> wrote: > Alex > > Sometimes you might find it easier to search for a particular clock > generator chip. For instance the ICS8442 that we use in an add-on > module and some of our development boards has a very good LVDS output > and can go up to 700MHz. A number of board manufacturers have this > clock generator on their boards. > > We also use the Cypress clock clock generator CY7C22394 on some > products which isn't so good as the ICS8442 but much more flexible in > frequency output. > > We also have a high stability oscillator option on our Mulldonnoch2 > producthttp://www.enterpoint.co.uk/oem_industrial/mulldonnoch2.html. > This particular product takes the form of an industrial EBX format > motherboard but is still good as a development board. > > For development boards long term stability isn't often a much asked > for parameter and that is probably why most companies don't > particularly list it. Not specifying also allows some sourcing > flexibility and avoids having to change board documentation as well. > > John Adair > Enterpoint Ltd. > Hi John, Thank you for reply and suggestion. I am not sure yet what to use - either a particular clock chip with improved stability or FPGA-board's clock. The latter option is certainly a cheaper one but whether it's good enough for my project or not?Article: 143709
Xilinx users, I have seemingly contradictory desires: a 64-bit OS and the ability to run all of the Xilinx tools, including AccelDSP. The official Xilinx list of supported OSes shows only the 32-bit version of XP as supporting everything. http://www.xilinx.com/ise/ossupport/index.htm Is it possible to run the Xilinx tools under a Windows-based 64-bit OS? Would I see benefits from the increased memory that 64-bit OSes provide? Thank you, StephenArticle: 143710
On Thu, 22 Oct 2009 06:17:31 -0700, stephen.craven@gmail.com wrote: > Xilinx users, > > I have seemingly contradictory desires: a 64-bit OS and the ability to > run all of the Xilinx tools, including AccelDSP. The official Xilinx > list of supported OSes shows only the 32-bit version of XP as supporting > everything. > http://www.xilinx.com/ise/ossupport/index.htm > > Is it possible to run the Xilinx tools under a Windows-based 64-bit OS? > > Would I see benefits from the increased memory that 64-bit OSes provide? > > Thank you, > Stephen It depends on the size of the FPGAs that you are targeting. The larger FPGAs require much more memory then a 32 bit OS has access to. The Linux version supports 64 bit Linux and has done so for years.Article: 143711
Hi all, Just a quick email to tell you that the SCLive 3.0 release candidate is out. It now has Icarus Verilog, GHDL and SystemC 2.2 + TLM + SCV pre- installed with tutorials. You can have a look at the screen shots here: http://sclive.wordpress.com/2009/09/01/sclive-3-0-release-candidate-screenshots/ For a more detailed description you can go here: http://sclive.wordpress.com/user-guide/ Voila, David CabanisArticle: 143712
On 22 =CF=CB=D4, 18:19, doug <x...@xx.com> wrote: > Alex wrote: > > Hi Ben, > > > Thank you for reply. > > > I actually worry about clock's time stability because I want to design > > FPGA-based oscillator whose frequency can be set in 0.1 Hz steps. > > Whether 50 ppm clock's stability is good enough to be used for such > > design? > > You need to look at the difference between accuracy and resolution and > stability. =9AA DDS will give you a resolution proportional to the number > of bits in the accumulator. The accuracy of the divide ratio is > absolute. The accuracy of the output frequency is proportional to the > accuracy of the oscillator. =9AIf you output a 10MHz signal with a > reference oscillator whose stability over temperature and time is 50ppm, > the output frequency can vary by 500Hz. At a couple of ppm per degree, > the frequency would wander perhaps 20Hz per degree. This means a .1Hz > resolution is not very useful. =9AFor this to be meaninful, you would > need a stability of .01ppm. =9AIf, however, you are doing this at 20KHz, > then the .1Hz corresponds to 5ppm and it is not so awful to use the > 50ppm stability oscillator. Hi Doug, Thank you for your reply. I've got it - in order to achieve frequency resolution of 0.1Hz I will need to use a particular external clock whose stability is much better that that of an on-board clock. Ben Jones wrote: >But I would be surprised if you ever needed to worry about 50ppm frequency= drift in >an FPGA application. The DLL jitter will be an order of magnitude greater = than that... Hence, I am interested - if I will use a clock with, for example, 0.001ppm time stability then would it be possible to generate few MHz frequency in 0.1Hz steps? Would DLL jitter prevent this or not? (I am going to use Spartan3E 1600E Microblaze Development Kit).Article: 143713
Alex wrote: > Hi Ben, > > Thank you for reply. > > I actually worry about clock's time stability because I want to design > FPGA-based oscillator whose frequency can be set in 0.1 Hz steps. > Whether 50 ppm clock's stability is good enough to be used for such > design? You need to look at the difference between accuracy and resolution and stability. A DDS will give you a resolution proportional to the number of bits in the accumulator. The accuracy of the divide ratio is absolute. The accuracy of the output frequency is proportional to the accuracy of the oscillator. If you output a 10MHz signal with a reference oscillator whose stability over temperature and time is 50ppm, the output frequency can vary by 500Hz. At a couple of ppm per degree, the frequency would wander perhaps 20Hz per degree. This means a .1Hz resolution is not very useful. For this to be meaninful, you would need a stability of .01ppm. If, however, you are doing this at 20KHz, then the .1Hz corresponds to 5ppm and it is not so awful to use the 50ppm stability oscillator.Article: 143714
.1 Hz resolution is something easily achieved, A simple 50 ppm crystal oscillator means +/- 50 Hz for every megahertz, absolute worst case, over all time, over the rated temperature range. It says nothing about the time scale, as you say. Stability over time is a well studied field, and you should go to the NIST (National Institute of Time and Standards) to read all about it. I went to "time school" there, so I am an "expert"... Such an oscillator can easily be used through a direct digital frequency synthesizer to generate frequencies in .1 Hz steps, or even smaller. http://www.cxrlarus.com/Data/Articles/Timingiseverything/index.htm You are looking for MTIE (TDEV) which is the amount you vary in any period of time. Such small inexpensive oscillators do not characterize for this, but more expensive units do. For example, in 10 seconds, no more than 100 ns drift is tolerated by SONET networks. http://www.us.anritsu.com/downloads/files/Tech_Note_CMA5000_XTA_Wander_V1.pdf figure 7 Crystals, even inexpensive ones, usually do not drift by this much is so short a time. So, when you turn it on, it will be +/-50 ppm from its marking. After 10 seconds, its phase will not have drifted much (frequency will be the same as when it started). As the temperature changes, it will vary in frequency. If you care about absolute accuracy, then you will need a cesium clock (1E-11 absolute accuracy). However, even cesium clocks have MTIE charts, and they also vary in phase over time by some tens of nanoseconds, to hundreds of nanoseconds in a day. But, their frequency will always be +/1 1E-11 from whatever its output is (typically 10 MHz). A Rubidium clock will start up at the frequency it "likes" (each rubidium cell is different),, but then it will stay where it is, again about 1E-10. No absolute, but really good (small) variation with time. An ovenized crystal resonator (HP made some really good ones) is about 1E-9. Your inexpensive crystal is 50E-6. So, do you want absolute accuracy? Get a cesium reference. There are GPS clocks which also provide absolute accuracy, too. Or, do you want adjustability (tuning)? Use an inexpensive crystal, synthesize what you want. AustinArticle: 143715
doug <xx@xx.com> wrote:
>
>
>Alex wrote:
>
>> Hi Ben,
>>
>> Thank you for reply.
>>
>> I actually worry about clock's time stability because I want to design
>> FPGA-based oscillator whose frequency can be set in 0.1 Hz steps.
>> Whether 50 ppm clock's stability is good enough to be used for such
>> design?
>
>You need to look at the difference between accuracy and resolution and
>stability. A DDS will give you a resolution proportional to the number
>of bits in the accumulator. The accuracy of the divide ratio is
>absolute. The accuracy of the output frequency is proportional to the
>accuracy of the oscillator. If you output a 10MHz signal with a
>reference oscillator whose stability over temperature and time is 50ppm,
>the output frequency can vary by 500Hz. At a couple of ppm per degree,
>the frequency would wander perhaps 20Hz per degree. This means a .1Hz
>resolution is not very useful. For this to be meaninful, you would
>need a stability of .01ppm. If, however, you are doing this at 20KHz,
>then the .1Hz corresponds to 5ppm and it is not so awful to use the
>50ppm stability oscillator.
Sorry, but this is all wrong!
If you take a 10MHz oscillator with 50ppm drift and divide the output
by 1000, the output will still have 50ppm drift. At 10MHz the drift is
500Hz, at 10kHz the drift is 0.5Hz.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143716Hi, I have just started out with some VHDL in school and would like to have something at home to play with. I'm not sure of CPLD vs FPGA for my use, but CPLD feel more suited for smaller projects I guess. My question is how Linux is supported as developmentplatform? (I have linux on my computers at home and want to be able to us them as hostsystem, at school we use some older version of a program called warp) I have looked at some of Xilinks and Alteras homepages and it seams that they have software for Linux. But it would be good to hear from someone with experince how the different software packages work? (if some company have better software than other, or someones software is better for the Linux platform) I'm just not sure where to start and some genereal tips on Linux and CPLD/FPGAs would also be good to hear... :) Regards, RobertArticle: 143717
austin <austin@xilinx.com> wrote: ... > Your inexpensive crystal is 50E-6. > So, do you want absolute accuracy? Get a cesium reference. There are > GPS clocks which also provide absolute accuracy, too. > Or, do you want adjustability (tuning)? Use an inexpensive crystal, > synthesize what you want. TXCOs should also be named here -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143718
On 22 =CF=CB=D4, 18:31, austin <aus...@xilinx.com> wrote: > .1 Hz resolution is something easily achieved, > > A simple 50 ppm crystal oscillator means +/- 50 Hz for every > megahertz, absolute worst case, over all time, over the rated > temperature range. > > It says nothing about the time scale, as you say. > > Stability over time is a well studied field, and you should go to the > NIST (National Institute of Time and Standards) to read all about it. > > I went to "time school" there, so I am an "expert"... > > Such an oscillator can easily be used through a direct digital > frequency synthesizer to generate frequencies in .1 Hz steps, or even > smaller. > > http://www.cxrlarus.com/Data/Articles/Timingiseverything/index.htm > > You are looking for MTIE (TDEV) which is the amount you vary in any > period of time. =9ASuch small inexpensive oscillators do not > characterize for this, but more expensive units do. > > For example, in 10 seconds, no more than 100 ns drift is tolerated by > SONET networks. > > http://www.us.anritsu.com/downloads/files/Tech_Note_CMA5000_XTA_Wande... > > figure 7 > > Crystals, even inexpensive ones, usually do not drift by this much is > so short a time. > > So, when you turn it on, it will be +/-50 ppm from its marking. =9AAfter > 10 seconds, its phase will not have drifted much (frequency will be > the same as when it started). > > As the temperature changes, it will vary in frequency. > > If you care about absolute accuracy, then you will need a cesium clock > (1E-11 absolute accuracy). =9AHowever, even cesium clocks have MTIE > charts, and they also vary in phase over time by some tens of > nanoseconds, to hundreds of nanoseconds in a day. =9ABut, their > frequency will always be +/1 1E-11 from whatever its output is > (typically 10 MHz). > > A Rubidium clock will start up at the frequency it "likes" (each > rubidium cell is different),, but then it will stay where it is, again > about 1E-10. =9ANo absolute, but really good (small) variation with > time. > > An ovenized crystal resonator (HP made some really good ones) is about > 1E-9. > > Your inexpensive crystal is 50E-6. > > So, do you want absolute accuracy? =9AGet a cesium reference. =9AThere ar= e > GPS clocks which also provide absolute accuracy, too. > > Or, do you want adjustability (tuning)? =9AUse an inexpensive crystal, > synthesize what you want. > > Austin Hi Austin, Thank you for reply. It's helpful indeed. But what about DLL jitter? Could it spoil stability of frequency derived from absolutely accurate clock?Article: 143719
Scorpiion <Robert.nr1@gmail.com> wrote: > Hi, I have just started out with some VHDL in school and would like to have > something at home to play with. I'm not sure of CPLD vs FPGA for my use, > but CPLD feel more suited for smaller projects I guess. My question is how > Linux is supported as developmentplatform? (I have linux on my computers at > home and want to be able to us them as hostsystem, at school we use some > older version of a program called warp) > I have looked at some of Xilinks and Alteras homepages and it seams that > they have software for Linux. But it would be good to hear from someone > with experince how the different software packages work? (if some company > have better software than other, or someones software is better for the > Linux platform) > I'm just not sure where to start and some genereal tips on Linux and > CPLD/FPGAs would also be good to hear... :) If you really want to learn, use CPLDs. They have few resources and few kind of resources, and so to implement something you soon hit their size limit with deficiencies of your coding and solution approach and to squeeze your project in the CPLD, you need to learn a lot. If you want to implement bigger things, FPGA soon gets easier and cheaper. You can even learn a much more with them, have they have zillions of different resources to learn and understand. Other things to consider: - Number of supply voltages needed(One for XC95 versus 2 for XC2C/XC3SA versus 3 for other XC3S) - Voltage tolerance needed (only XC95XV is (limited ) 5-Volt tolerant - Is the toolchain available for linux. At what costs. To my knowledge, Altera doesn't offer a free Linx version. - Size of your project: If you need more than about 140 registers, XC3SA with SPI Flash soon gets to similar costs to a decent sized CPLD. - Where do go get help. If you decide for e,g. FPGA but for friends use CPLD, help is harder to get. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143720
I use the Xilinx ISE WebPack under Linux for CPLD and FPGA work, although I have my own hardware solutions for programming the physical devices.Article: 143721
Nico Coesel wrote: > doug <xx@xx.com> wrote: > > >> >>Alex wrote: >> >> >>>Hi Ben, >>> >>>Thank you for reply. >>> >>>I actually worry about clock's time stability because I want to design >>>FPGA-based oscillator whose frequency can be set in 0.1 Hz steps. >>>Whether 50 ppm clock's stability is good enough to be used for such >>>design? >> >>You need to look at the difference between accuracy and resolution and >>stability. A DDS will give you a resolution proportional to the number >>of bits in the accumulator. The accuracy of the divide ratio is >>absolute. The accuracy of the output frequency is proportional to the >>accuracy of the oscillator. If you output a 10MHz signal with a >>reference oscillator whose stability over temperature and time is 50ppm, >>the output frequency can vary by 500Hz. At a couple of ppm per degree, >>the frequency would wander perhaps 20Hz per degree. This means a .1Hz >>resolution is not very useful. For this to be meaninful, you would >>need a stability of .01ppm. If, however, you are doing this at 20KHz, >>then the .1Hz corresponds to 5ppm and it is not so awful to use the >>50ppm stability oscillator. > > > Sorry, but this is all wrong! No, is is just fine. > > If you take a 10MHz oscillator with 50ppm drift and divide the output > by 1000, the output will still have 50ppm drift. At 10MHz the drift is > 500Hz, at 10kHz the drift is 0.5Hz. You misread the statement above. It does not refer to a 10MHz oscillator, it refers to a 10MHz output. >Article: 143722
DLL jitter, Is +/- ~ 50 ps about the input frequency. It has no effect on frequency, whatsoever. What goes in to a DLL (DCM), comes out. It is a delay line, with taps. What goes in MUST come out (at exactly the same frequency, with a small amount of added jitter). The DFS (frequency synthesizer) part of the DCM has a bit more jitter (nominally 3 times the tap size, + and -), its output frequency is also exact (by the M/D ratio specified). AustinArticle: 143723
Alex wrote: > On 22 ΟΛΤ, 18:19, doug <x...@xx.com> wrote: > >>Alex wrote: >> >>>Hi Ben, >> >>>Thank you for reply. >> >>>I actually worry about clock's time stability because I want to design >>>FPGA-based oscillator whose frequency can be set in 0.1 Hz steps. >>>Whether 50 ppm clock's stability is good enough to be used for such >>>design? >> >>You need to look at the difference between accuracy and resolution and >>stability. A DDS will give you a resolution proportional to the number >>of bits in the accumulator. The accuracy of the divide ratio is >>absolute. The accuracy of the output frequency is proportional to the >>accuracy of the oscillator. If you output a 10MHz signal with a >>reference oscillator whose stability over temperature and time is 50ppm, >>the output frequency can vary by 500Hz. At a couple of ppm per degree, >>the frequency would wander perhaps 20Hz per degree. This means a .1Hz >>resolution is not very useful. For this to be meaninful, you would >>need a stability of .01ppm. If, however, you are doing this at 20KHz, >>then the .1Hz corresponds to 5ppm and it is not so awful to use the >>50ppm stability oscillator. > > > Hi Doug, > > Thank you for your reply. > > I've got it - in order to achieve frequency resolution of 0.1Hz I will > need to use a particular external clock whose stability is much better > that that of an on-board clock. > > Ben Jones wrote: > >>But I would be surprised if you ever needed to worry about 50ppm frequency drift in >>an FPGA application. The DLL jitter will be an order of magnitude greater than that... > > > Hence, I am interested - if I will use a clock with, for example, > 0.001ppm time stability then would it be possible to generate few MHz > frequency in 0.1Hz steps? Would DLL jitter prevent this or not? (I am > going to use Spartan3E 1600E Microblaze Development Kit). Jitter and stability are two different things. Jitter makes noise on the signal. But, generating a signal in an FPGA is not going to be quiet anyway as it is not meant for clean signals. Even running a clock just thru the FPGA will make it much too noisy for certain communications work. We found this out the hard way years ago.Article: 143724
Scorpiion wrote: > Hi, I have just started out with some VHDL in school and would like to have > something at home to play with. I'm not sure of CPLD vs FPGA for my use, > but CPLD feel more suited for smaller projects I guess. My question is how > Linux is supported as developmentplatform? (I have linux on my computers at > home and want to be able to us them as hostsystem, at school we use some > older version of a program called warp) webpack ISE 10.1 works under Fedora 8 and 11 (still checking that out). For the free version you get the 32 bit version. It will work on a 64 bit system. I do that already. To use 64 bit version of webpack you need to pay for licenses etc. You may have to pay for the full version to use the larger/newer fpga's. The ISIM simulator does work under linux. I have no knowledge of VHDL simulators for linux. The officially supported o/s is RHEL and I think vista. Support for the design process I don't know. Andy > > I have looked at some of Xilinks and Alteras homepages and it seams that > they have software for Linux. But it would be good to hear from someone > with experince how the different software packages work? (if some company > have better software than other, or someones software is better for the > Linux platform) > > I'm just not sure where to start and some genereal tips on Linux and > CPLD/FPGAs would also be good to hear... :) > > Regards, Robert > >
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