Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi Antti,
I liked the article about the sine generator algorithm very much.
It was a little disappointing that you just provided code in some
software language (is it Java?) rather than a HDL.
After some testing in matlab I wrote some behavioral code in VHDL as a
testbench for the algorithm.
So here it is:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY tb_simplesine IS
END tb_simplesine;
ARCHITECTURE testbench OF tb_simplesine IS
SIGNAL alpha : std_logic_vector(23 DOWNTO 0);
SIGNAL beta : std_logic_vector(23 DOWNTO 0);
--SIGNAL mult : std_logic_vector(47 DOWNTO 0);
--SIGNAL n1 : std_logic_vector(23 DOWNTO 0);
--SIGNAL n2 : std_logic_vector(23 DOWNTO 0);
--SIGNAL sine : std_logic_vector(23 DOWNTO 0);
SIGNAL reset : std_logic;
SIGNAL clock : std_logic;
SIGNAL simulation_done : boolean := false;
SIGNAL load : std_logic;
BEGIN -- testbench
-- purpose: simple sine wave generator
-- type : sequential
-- inputs : clock, reset, alpha, beta
-- outputs: sine
sinegen: PROCESS (clock, reset)
VARIABLE alfa : std_logic_vector(23 DOWNTO 0);
VARIABLE mult : std_logic_vector(47 DOWNTO 0);
variable n1 : std_logic_vector(23 DOWNTO 0);
variable n2 : std_logic_vector(23 DOWNTO 0);
VARIABLE sine : std_logic_vector(23 DOWNTO 0);
BEGIN -- PROCESS sinegen
IF reset = '0' THEN -- asynchronous reset (active
low)
mult := (OTHERS => '0');
sine := (OTHERS => '0');
n1 := (OTHERS => '0');
n2 := (OTHERS => '0');
alfa := (OTHERS => '0');
ELSIF clock'event AND clock = '1' THEN -- rising clock edge
IF load='1' THEN
n2 := beta; --use in port later
alfa := alpha; --use in port later
ELSE
mult := alfa * n1;
sine := mult(45 DOWNTO 45-24) - n2;
n2 := n1;
n1 := sine;
END IF;
END IF;
END PROCESS sinegen;
-- purpose: generate clocks
-- type : combinational
-- inputs :
-- outputs: clock
clock_gen: PROCESS
BEGIN -- PROCESS clock_gen
IF NOT simulation_done THEN
clock <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
ELSE
wait;
END IF;
END PROCESS clock_gen;
-- purpose: test the algorithm above
-- type : sequential
-- inputs : clock
-- outputs:
testrun: PROCESS
BEGIN -- PROCESS testrun
reset <= '1';
load <= '0';
alpha <= B"01_1111111011100111010110"; -- 1_9957177 24 bit
fixedpoint
beta <= B"11_1110111101000001110000"; -- -_065403
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '0' ;
reset <= '0';
load <= '1';
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '1' ;
load <= '0';
FOR i IN 0 TO 400 LOOP
WAIT until clock'event AND clock = '1' ;
END LOOP; -- i
simulation_done <= true;
wait;
END PROCESS testrun;
END testbench;
And in modelsim you can nicely view the sine waves using format/analog
(automatic)
Have a nice simulation
Eilert
Article: 143326On Thu, 01 Oct 2009 16:57:00 -0700, Peter Alfke wrote: > Phil, please do not blame your bad habits on Xilinx, always a strong > advocate of synchronous design methods. Peter Alfke, formerly associated > with Xilinx. I wasn't blaming my bad habits on Xilinx -- just commenting on how some of the ISE3 manual examples cause flip-flop inference, and one or two that I've copy-pasted just plain don't work as advertised. But I will say one thing: providing a free Linux version of the IDE gets them significant points over Altera. AIUI the Linux version of Quartus Web Edition has been canned, while ISE Webpack was still available in a Linux version last time I checked. It's just a shame the distributors I use don't carry Xilinx FPGA parts. I can get small Altera CPLDs, Altera FPGAs or Xilinx CPLDs, but not any Xilinx FPGAs or (large) Altera CPLDs. Very annoying.Article: 143327
On Thu, 01 Oct 2009 16:57:00 -0700, Peter Alfke wrote: > Phil, please do not blame your bad habits on Xilinx, always a strong > advocate of synchronous design methods. Peter Alfke, formerly associated > with Xilinx. I wasn't blaming my bad habits on Xilinx -- just commenting on how some of the ISE3 manual examples cause flip-flop inference, and one or two that I've copy-pasted just plain don't work as advertised. But I will say one thing: providing a free Linux version of the IDE gets them significant points over Altera. AIUI the Linux version of Quartus Web Edition has been canned, while ISE Webpack was still available in a Linux version last time I checked. It's just a shame the distributors I use don't carry Xilinx FPGA parts. I can get small Altera CPLDs, Altera FPGAs or Xilinx CPLDs, but not any Xilinx FPGAs or (large) Altera CPLDs. Very annoying.Article: 143328
On Oct 2, 5:35=A0am, Philip Pemberton <usene...@philpem.me.uk> wrote: > On Thu, 01 Oct 2009 16:57:00 -0700, Peter Alfke wrote: > > Phil, please do not blame your bad habits on Xilinx, always a strong > > advocate of synchronous design methods. Peter Alfke, formerly associate= d > > with Xilinx. > > I wasn't blaming my bad habits on Xilinx -- just commenting on how some > of the ISE3 manual examples cause flip-flop inference, and one or two > that I've copy-pasted just plain don't work as advertised. > > But I will say one thing: providing a free Linux version of the IDE gets > them significant points over Altera. AIUI the Linux version of Quartus > Web Edition has been canned, while ISE Webpack was still available in a > Linux version last time I checked. > > It's just a shame the distributors I use don't carry Xilinx FPGA parts. I > can get small Altera CPLDs, Altera FPGAs or Xilinx CPLDs, but not any > Xilinx FPGAs or (large) Altera CPLDs. Very annoying. Have you looked at buying from Digikey? John ProvidenzaArticle: 143329
On Oct 2, 1:28=A0pm, backhus <goo...@twinmail.de> wrote: > Hi Antti, > I liked the article about the sine generator algorithm very much. > It was a little disappointing that you just provided code in some > software language (is it Java?) rather than a HDL. > > After some testing in matlab I wrote some behavioral code in VHDL as a > testbench for the algorithm. > So here it is: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.std_logic_arith.ALL; > USE ieee.std_logic_signed.ALL; > > ENTITY tb_simplesine IS > END tb_simplesine; > > ARCHITECTURE testbench OF tb_simplesine IS > > =A0 SIGNAL alpha : std_logic_vector(23 DOWNTO 0); > =A0 SIGNAL beta : std_logic_vector(23 DOWNTO 0); > =A0 --SIGNAL mult : std_logic_vector(47 DOWNTO 0); > =A0 --SIGNAL n1 : std_logic_vector(23 DOWNTO 0); > =A0 --SIGNAL n2 : std_logic_vector(23 DOWNTO 0); > =A0 --SIGNAL sine : std_logic_vector(23 DOWNTO 0); > > =A0 SIGNAL reset : std_logic; > =A0 SIGNAL clock : std_logic; > =A0 SIGNAL simulation_done : boolean :=3D false; > =A0 SIGNAL load : std_logic; > > =A0 BEGIN =A0-- testbench > > =A0 -- purpose: simple sine wave generator > =A0 -- type =A0 : sequential > =A0 -- inputs : clock, reset, alpha, beta > =A0 -- outputs: sine > =A0 sinegen: PROCESS (clock, reset) > =A0 =A0 VARIABLE alfa : std_logic_vector(23 DOWNTO 0); > =A0 =A0 VARIABLE mult : std_logic_vector(47 DOWNTO 0); > =A0 =A0 variable n1 : std_logic_vector(23 DOWNTO 0); > =A0 =A0 variable n2 : std_logic_vector(23 DOWNTO 0); > =A0 =A0 VARIABLE sine : std_logic_vector(23 DOWNTO 0); > > =A0 BEGIN =A0-- PROCESS sinegen > =A0 =A0 IF reset =3D '0' THEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- asynchro= nous reset (active > low) > =A0 =A0 =A0 mult :=3D (OTHERS =3D> '0'); > =A0 =A0 =A0 sine :=3D (OTHERS =3D> '0'); > =A0 =A0 =A0 n1 :=3D (OTHERS =3D> '0'); > =A0 =A0 =A0 n2 :=3D (OTHERS =3D> '0'); > =A0 =A0 =A0 alfa :=3D (OTHERS =3D> '0'); > > =A0 =A0 ELSIF clock'event AND clock =3D '1' THEN =A0-- rising clock edge > =A0 =A0 =A0 =A0IF load=3D'1' THEN > =A0 =A0 =A0 =A0 =A0n2 :=3D beta; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-= -use in port later > =A0 =A0 =A0 =A0 =A0alfa :=3D alpha; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --use= in port later > =A0 =A0 =A0 =A0ELSE > =A0 =A0 =A0 =A0 =A0mult :=3D alfa * n1; > =A0 =A0 =A0 =A0 =A0sine :=3D mult(45 DOWNTO 45-24) - n2; > =A0 =A0 =A0 =A0 =A0n2 :=3D n1; > =A0 =A0 =A0 =A0 =A0n1 :=3D sine; > =A0 =A0 =A0 =A0END IF; > > =A0 =A0 END IF; > =A0 END PROCESS sinegen; > > -- purpose: generate clocks > -- type =A0 : combinational > -- inputs : > -- outputs: clock > clock_gen: PROCESS > BEGIN =A0-- PROCESS clock_gen > =A0 IF NOT simulation_done THEN > =A0 =A0 clock <=3D '1'; > =A0 =A0 WAIT FOR 50 ns; > =A0 =A0 =A0clock <=3D '0'; > =A0 =A0 WAIT FOR 50 ns; > =A0 ELSE > =A0 =A0 wait; > =A0 END IF; > END PROCESS clock_gen; > > -- purpose: test the algorithm above > -- type =A0 : sequential > -- inputs : clock > -- outputs: > testrun: PROCESS > BEGIN =A0-- PROCESS testrun > =A0 reset <=3D '1'; > =A0 load =A0<=3D '0'; > =A0 alpha <=3D B"01_1111111011100111010110"; -- 1_9957177 24 bit > fixedpoint > =A0 beta <=3D =A0B"11_1110111101000001110000"; =A0-- -_065403 > =A0 WAIT until =A0 clock'event AND clock =3D '1' ; > =A0 WAIT until =A0 clock'event AND clock =3D '1' ; > =A0 WAIT until =A0 clock'event AND clock =3D '0' ; > =A0 reset <=3D '0'; > =A0 load <=3D '1'; > =A0 WAIT until =A0 clock'event AND clock =3D '1' ; > =A0 WAIT until =A0 clock'event AND clock =3D '1' ; > =A0 load =A0<=3D '0'; > =A0 FOR i IN 0 TO 400 LOOP > =A0 =A0 =A0 =A0 WAIT until =A0 clock'event AND clock =3D '1' ; > =A0 END LOOP; =A0-- i > =A0 simulation_done <=3D true; > =A0 wait; > > END PROCESS testrun; > > END testbench; > > And in modelsim you can nicely view the sine waves using format/analog > (automatic) > > Have a nice simulation > =A0 Eilert Hi nice, I did not have VHDL code, the reason why I "trapped" into was that i was doing simulation tests for AL3101 and TAS3108 IP cores, and then i looked the DSP asm examples for the "tone generator" and found that 1) AL3101 used for single change generator about 220 cycles from 1024 available (sin approx with polynome) while 2) TAS3108 code used exactly 5 DSP instruction ah, Kolja sorry I was so much in a rush, i forgot to mention that you told me the trick of tonegen with DSP sorry again.. its seems my low blood pressure is lowering again (weakness) my 5 year old daugher just told me i need take vaccation! well i hope that times comes too.. a nice weekend to all AnttiArticle: 143330
Thanks for your response. Finally, I have found a solution for my problem without use Impact. I explain for those who don't know this solution : - Download Xilinx bitstream to Flah memory SD Card with Altium Designer - bootstrap the daughter board FPGA from SD Card It explains in the following document "TR0149 Technical Reference for Altium's Xilinx Spartan-3 Daughter Board DB30.pdf" p68. I haven't tested it yet but I think it works. Cyrille Chevrot --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143331
Hello group, I am about to start working with ML410 which is V4 Xilinx board, so far I have used Altera and Spartan 3E for academic works. I will appreciate it if you could guide me: 1) where to start and what I should know in advance. 2) I have a UCF file which defines some constraints on Spartan 3E, can I use it on this board too or connections are different? Regards, AmitArticle: 143332
On Oct 2, 11:05=A0pm, akohan <amit.ko...@gmail.com> wrote: > Hello group, > > I am about to start working with ML410 which is V4 Xilinx board, so > far I have used Altera and Spartan 3E for academic works. I will > appreciate it if you could guide me: > > 1) where to start and what I should know in advance. > > 2) I have a UCF file which defines some constraints on Spartan 3E, can > I use it on this board too or =A0connections are different? > > Regards, > Amit One thing I forgot to ask do I need using Linux or Windows for embedded coding with C?Article: 143333
The logic function bits (LUT, DFF, MUX ...) for a column of 16 CLBs are in 4 continuous frames (LUT function are in frame 1, 3; DFF bits are in frame 0, 2). I'm make some change in the LUT truth tables (with fpga_editor or ise or whatever) and these changes affect frames 1 and 3. Actually, my logic change will turn off 4 LEDs. I can make bitgen to generate a partial bitstream file. I can then download this pr bit file using impact or ICAP. This works - and the pr bit file only write to frame 1 and 3. I tried another approach: I read back the configuration bits of the 4 frames from ICAP, I made modification to the bits of frame 1 and frame 3 - I know how to change the internal bits for LUT and they look exactly the same as the bits in the pr bit file generated by bitgen. Then I write the 4 frames back through ICAP and interesting cases occurs: 1) if I only write frame 1 and 3, this is essentially the same as downloading the pr bit file, and the logic change is perfect; all LEDs are off. 2) if I write the 4 frames in the oder frame 0, 1, 2, 3, hoops ... LED 3 and 4 are on! And even downloading the pr bit file again can't turn them off. Something weird happens! Yet, from ICAP read back, the LUT bits are changed ... 3) if I write 4 frames 0, 1, 2, (3), where frame (3) is not modified, LED 1 & 3 are on and 2 & 4 are off - make sense; 4) if I write 4 frames 0, (1), 2, 3, where frame (1) is not modified, LED 2 & 4 are on and 1 & 3 are off - make sense; ...... x) if I write 4 frames in the order 1, 3, 0, 2, again it works. I spent a whole day to look for reasoning behind this ... but it just seems non-sense. While, a fix for 4 frames of CLB logic bits could be just write frame 1&3 together and frame 0&2 together; but how about the other 18 frames of CLB routing bits? How to debug similar weird case and get a fix?Article: 143334
On Sep 30, 10:15=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > LucienZ wrote: > > Hi everyone, I am a master student and this is my first post in this > > group. My research group is looking for a multicore embedded platform > > for deploying an in-house developed computer vision algorithm. I've > > checked some available development boards and now still weigh the > > ideas in my mind. > > I might verify that the algorithm is amenable > to parallel processing by borrowing a rack > of servers before I took on building > the same thing on an fpga. > > =A0 =A0 =A0-- Mike Treseler Thanks for your advice Mike! There are some obvious sections in the algorithm that I believe can be parallelized e.g. for-loops that process each line (independent on other lines) of the pixel matrix. I also plan to do some verification work before a real implementation on FPGAs. But server racks may not be easily accessible for me. So I am thinking about some tools like Pthread or OpenMP... (not used before). Do you have more suggestions for doing such a verification work?Article: 143335
On Oct 1, 8:53=A0pm, Jon <j...@beniston.com> wrote: > > But I've seen > > one design article (carried out at NXP, the Netherlands) that claims > > they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4 > > FPGA chip. I am wondering what technologies enable this > > implementation. > > The same technologies that enable any other CPU to be put on an FPGA. > The ARM926EJ-S is no different, except that it will be a lot bigger > and a lot slower, than other FPGA specific CPUs. > > > 1. How to implement one or more such ARM926EJ-S cores on a FPGA chip > > Talk to ARM, but you probably can't afford it. > > Jon Thank you Jon. In my understanding, 'hard' processor cores on an FPGA are not using the FPGA fabric. They are made on the same die with FPGA fabrics by FPGA vendors e.g. PowerPC cores on Virtex products. Here the FPGA fabric is working as glue logics for interconnections or customized peripherals. Here I guess the PowerPC core on Virtex is not the same concept like Microblaze cores on Virtex. Am I right? So far I did not see a FPGA chip on market that contains a hardened ARM core on the same chip, and that is why I am asking this question. In your answer, what do you mean by 'FPGA specific CPUs'? And can you tell me more words on your mentioned 'technologies'?Article: 143336
On Oct 1, 9:12=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Oct 1, 9:53=A0pm, Jon <j...@beniston.com> wrote: > > > > But I've seen > > > one design article (carried out at NXP, the Netherlands) that claims > > > they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4 > > > FPGA chip. I am wondering what technologies enable this > > > implementation. > > > The same technologies that enable any other CPU to be put on an FPGA. > > The ARM926EJ-S is no different, except that it will be a lot bigger > > and a lot slower, than other FPGA specific CPUs. > > > > 1. How to implement one or more such ARM926EJ-S cores on a FPGA chip > > > Talk to ARM, but you probably can't afford it. > > > Jon > > http://www.elektroniknet.de/home/embeddedsystems/news/n/d/ohne-lizenz... Thank you too Antti. My Deutsch is poor...but I may have seen this product here: http://www.ge-research.com/arm_microcontroller.html I think they are the same thing. This is ideal for some microcontroller ASIC prototyping, but may not be very suitable for us. First I can only access the Cortex-M3 pins on one Altera FPGA, but not be able to deploy several Cortex-M3 cores on one FPGA (right?). Another thing is that I think it is too slow (50MHz) to be used for video processing.Article: 143337
On Oct 2, 6:39=A0pm, intermilan <wenwei...@gmail.com> wrote: <snip> > I spent a whole day to look for reasoning behind this ... but it just > seems non-sense. > Or you're not understanding all that you think you do. > How to debug similar weird case and get a fix? 1. Stop hacking the configuration data bitstream 2. Write source code 3. Use a simulator and timing analysis to insure that your design is correct 4. Use the synthesis tools to go from source code to configuration data bitstream. If you follow this flow, you'll find that you have more time in your day to do better things than trying to modify configuration data bitstreams. KJArticle: 143338
On Oct 3, 3:37=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > On Oct 1, 9:12=A0pm, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Oct 1, 9:53=A0pm, Jon <j...@beniston.com> wrote: > > > > > But I've seen > > > > one design article (carried out at NXP, the Netherlands) that claim= s > > > > they have implemented two ARM926EJ-S processors on a Xilinx Virtex = 4 > > > > FPGA chip. I am wondering what technologies enable this > > > > implementation. > > > > The same technologies that enable any other CPU to be put on an FPGA. > > > The ARM926EJ-S is no different, except that it will be a lot bigger > > > and a lot slower, than other FPGA specific CPUs. > > > > > 1. How to implement one or more such ARM926EJ-S cores on a FPGA chi= p > > > > Talk to ARM, but you probably can't afford it. > > > > Jon > > >http://www.elektroniknet.de/home/embeddedsystems/news/n/d/ohne-lizenz... > > Thank you too Antti. My Deutsch is poor...but I may have seen this > product here:http://www.ge-research.com/arm_microcontroller.html > I think they are the same thing. > > This is ideal for some microcontroller ASIC prototyping, but may not > be very suitable for us. First I can only access the Cortex-M3 pins on > one Altera FPGA, but not be able to deploy several Cortex-M3 cores on > one FPGA (right?). Another thing is that I think it is too slow > (50MHz) to be used for video processing. cortex m3 is easy obtainable a license for 1000 instances cost 2500 $ this IS common knowledge i assumed you know this AnttiArticle: 143339
LucienZ <lucien.zhang@gmail.com> wrote:
>On Oct 1, 9:12=A0pm, "Antti.Luk...@googlemail.com"
><antti.luk...@googlemail.com> wrote:
>> On Oct 1, 9:53=A0pm, Jon <j...@beniston.com> wrote:
>>
>> > > But I've seen
>> > > one design article (carried out at NXP, the Netherlands) that claims
>> > > they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4
>> > > FPGA chip. I am wondering what technologies enable this
>> > > implementation.
>>
>> > The same technologies that enable any other CPU to be put on an FPGA.
>> > The ARM926EJ-S is no different, except that it will be a lot bigger
>> > and a lot slower, than other FPGA specific CPUs.
>>
>> > > 1. How to implement one or more such ARM926EJ-S cores on a FPGA chip
>>
>> > Talk to ARM, but you probably can't afford it.
>>
>> > Jon
>>
>> http://www.elektroniknet.de/home/embeddedsystems/news/n/d/ohne-lizenz...
>
>Thank you too Antti. My Deutsch is poor...but I may have seen this
>product here: http://www.ge-research.com/arm_microcontroller.html
>I think they are the same thing.
>
>This is ideal for some microcontroller ASIC prototyping, but may not
>be very suitable for us. First I can only access the Cortex-M3 pins on
>one Altera FPGA, but not be able to deploy several Cortex-M3 cores on
>one FPGA (right?). Another thing is that I think it is too slow
>(50MHz) to be used for video processing.
I very much doubt you'll get an ARM core inside an FPGA that runs fast
enough. FPGAs are lousy at 'simulating' processors. Especially if you
look at the MIPS per $. Implementing multiple ARM cores in an FPGA is
definitily the wrong direction to solve your problem.
If you want raw processing power, you should look into a PC platform
or implement the algorithm in an FPGA directly IF there isn't a
processor available that can do the job. I guess the project isn't big
enough to go for an ASIC.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143340On Oct 2, 8:36=A0pm, LucienZ <lucien.zh...@gmail.com> wrote: > On Oct 1, 8:53=A0pm, Jon <j...@beniston.com> wrote: > > > > But I've seen > > > one design article (carried out at NXP, the Netherlands) that claims > > > they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4 > > > FPGA chip. I am wondering what technologies enable this > > > implementation. > > > The same technologies that enable any other CPU to be put on an FPGA. > > The ARM926EJ-S is no different, except that it will be a lot bigger > > and a lot slower, than other FPGA specific CPUs. > > > > 1. How to implement one or more such ARM926EJ-S cores on a FPGA chip > > > Talk to ARM, but you probably can't afford it. > > > Jon > > Thank you Jon. In my understanding, 'hard' processor cores on an FPGA > are not using the FPGA fabric. They are made on the same die with FPGA > fabrics by FPGA vendors e.g. PowerPC cores on Virtex products. Here > the FPGA fabric is working as glue logics for interconnections or > customized peripherals. Here I guess the PowerPC core on Virtex is not > the same concept like Microblaze cores on Virtex. Am I right? > > So far I did not see a FPGA chip on market that contains a hardened > ARM core on the same chip, and that is why I am asking this question. > > In your answer, what do you mean by 'FPGA specific CPUs'? And can you > tell me more words on your mentioned 'technologies'? Hard processor cores in an FPGA are essentially similar to the same processor core in an ASIC and probably have similar performance. They also increase the price of an FPGA by more than you would typically spend for the standard processor in a chip by itself. FPGA-specific processors like NIOS and MicroBlaze were designed for implementation in an FPGA and theerfore typically perform better in that FPGA than a market-standard device like ARM. The measure of performance usually includes the percentage of the FPGA fabric used, so in other words you'd have a much easier time placing 4 MicroBlazes in a Virtex 5 than 4 ARM cores. Finally there are other devices out there that start from a fairly high performance processor but provide some form of FPGA-like additional fabric to extend your instruction set. Check out Stretch (http://www.stretchinc.com) for an example of this. Also for general purpose image processing you could use a farm of DSP's that were designed to connect together like sharc chips from Analog Devices. Another approach that woks fairly well is to use "media processors" designed for set-top boxes, which can be very inexpensive. An example would be the PNX15xx series from NXP. In the end the performance of any multiprocessor approach will be limited by the interconnect speed and your ability to divide up the process with the least interconnect bandwidth requirements. Regards, GaborArticle: 143341
At the moment I am running webpack OK using fedore core 8 (64 bit quad core). This operating system is getting a bit old and am wondering if moving to a more modern fedora will work *without* changing webpack? What is the latest version of fedora that you have managed to run this version of webpack on? I know fedora is not a supported o/s so I'm not checking the Xilinx website. Thanks in advance. AndyArticle: 143342
LucienZ wrote:
> Do you have more suggestions for doing such a verification work?
I use python to test algorithms.
It's free and easy to use.
-- Mike Treseler
Article: 143343
LucienZ <lucien.zhang@gmail.com> wrote:
>On Sep 30, 10:15=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
>> LucienZ wrote:
>> > Hi everyone, I am a master student and this is my first post in this
>> > group. My research group is looking for a multicore embedded platform
>> > for deploying an in-house developed computer vision algorithm. I've
>> > checked some available development boards and now still weigh the
>> > ideas in my mind.
>>
>> I might verify that the algorithm is amenable
>> to parallel processing by borrowing a rack
>> of servers before I took on building
>> the same thing on an fpga.
>>
>> =A0 =A0 =A0-- Mike Treseler
>
>Thanks for your advice Mike! There are some obvious sections in the
>algorithm that I believe can be parallelized e.g. for-loops that
>process each line (independent on other lines) of the pixel matrix. I
>also plan to do some verification work before a real implementation on
>FPGAs. But server racks may not be easily accessible for me. So I am
>thinking about some tools like Pthread or OpenMP... (not used before).
>
>Do you have more suggestions for doing such a verification work?
Why does verification takes a rack of servers? You can verify at any
speed. Just create an input dataset to test the extremes, process it
and examine the output. You can use the same dataset you created to
verify an FPGA implementation as well.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143344On Fri, 02 Oct 2009 07:38:53 -0700, johnp wrote: > Have you looked at buying from Digikey? Yep, but they insist on a Spanish Inquisition-style questioning whenever I order anything more unusual than a resistor or an opamp. Usually that culminates in an email saying something along the lines of "we've cancelled your order because we think you're going to do something naughty with these parts." I managed to get a couple of CPLDs out of them (my stock of XC95288XLs came from them) and an Altera DE1 dev board, but every time I've tried to get "raw" FPGA chips my order has been canned. -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "09" with the last two digits of the current year.Article: 143345
Philip Pemberton <usenet09@philpem.me.uk> wrote:
>On Thu, 01 Oct 2009 19:31:22 +0000, glen herrmannsfeldt wrote:
>
>> It sounds like you need a FIFO, and are attempting to make one out of
>> the SRAM. The FPGA tools usually know how to make a FIFO, at least when
>> using the FPGA BRAM (block RAM). Also, the BRAM are dual port, which
>> makes FIFO design easier.
>
>While a FIFO would be easier, it probably wouldn't have the storage
>capacity required.
>
The nice thing about FIFOs is that they can be cascaded very easely.
The first FIFO is an internal memory, the second FIFO is the SRAM.
With some management logic you can have an infinite number of FIFOs
inside an SRAM. Many years ago I did a design which had 4 or 5 FIFOs /
databuffers inside one SRAM.
Like others said keep everything in one clock domain as much as
possible. If the microcontroller has some form of synchronous bus (you
could forward the clock from the microcontroller to the FPGA to
achieve this) things will be much easier.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143346On 3 Okt., 03:21, KJ <kkjenni...@sbcglobal.net> wrote: > If you follow this flow, you'll find that you have more time in your > day to do better things than trying to modify configuration data > bitstreams. Or just use srl16 to change the LUT content. KoljaArticle: 143347
On Oct 3, 11:10=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > LucienZ <lucien.zh...@gmail.com> wrote: > >On Sep 30, 10:15=3DA0pm, Mike Treseler <mtrese...@gmail.com> wrote: > >> LucienZ wrote: > >> > Hi everyone, I am a master student and this is my first post in this > >> > group. My research group is looking for a multicore embedded platfor= m > >> > for deploying an in-house developed computer vision algorithm. I've > >> > checked some available development boards and now still weigh the > >> > ideas in my mind. > > >> I might verify that the algorithm is amenable > >> to parallel processing by borrowing a rack > >> of servers before I took on building > >> the same thing on an fpga. > > >> =3DA0 =3DA0 =3DA0-- Mike Treseler > > >Thanks for your advice Mike! There are some obvious sections in the > >algorithm that I believe can be parallelized e.g. for-loops that > >process each line (independent on other lines) of the pixel matrix. I > >also plan to do some verification work before a real implementation on > >FPGAs. But server racks may not be easily accessible for me. So I am > >thinking about some tools like Pthread or OpenMP... (not used before). > > >Do you have more suggestions for doing such a verification work? > > Why does verification takes a rack of servers? You can verify at any > speed. Just create an input dataset to test the extremes, process it > and examine the output. You can use the same dataset you created to > verify an FPGA implementation as well. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- Thank you very much Nico and gabor for your enlightening words. It is not mandatory for me to implement ARM cores on a FPGA chip. Just like gabor said, MicroBlaze and Nios could perform better than soft ARMs. I might also start with customized hardware design using HDL, for better performance on FPGAs. But I think the algorithms will evolve, so this approach is not flexible nor scalable enough. Moreover I also want to contribute something to the multicore architecture research; all these make me think of a processor-based design. After my prototyping there is indeed an ASIC (or say ASSP) plan (an ASIC designer will come in 2010). And I also hope he/she can inherit more from my experience. So far the bridging between FPGA prototyping and ASIC design is still not very clear to me. If I start with soft processor cores on FPGA, then I also hope to see an ASIC equivalence (architecture, instruction set etc.). My premature thought is that, if I can prototype a FPGA solution with the performance of 10 frames per second, when it goes to ASIC, we can expect a 20-fps result (possible ???). That's why the popularity of ARM makes me think about ARM cores on FPGA. I agree Microblaze and Nios perform better on FPGAs, but I doubt the availability of their ASIC implementation. Gabor says "Hard processor cores in an FPGA are essentially similar to the same processor core in an ASIC", I agree, and I am looking for the cores available for both FPGA and ASIC. But do they also "probably have similar performance"? I think ASICs can run much faster than FPGAs and I expect a nice speedup when it comes out from our foundry.Article: 143348
> cortex m3 > is easy obtainable a license for 1000 instances cost 2500 $ > > this IS common knowledge i assumed you know this > > Antti Is that Cortex-M3 license targeting ASIC fabrication or what? Sorry for not sharing the common knowledge; I am really a dummy here...Article: 143349
On Oct 4, 7:55=A0pm, LucienZ <lucien.zh...@gmail.com> wrote: > > cortex m3 > > is easy obtainable a license for 1000 instances cost 2500 $ > > > this IS common knowledge i assumed you know this > > > Antti > > Is that Cortex-M3 license targeting ASIC fabrication or what? > Sorry for not sharing the common knowledge; I am really a dummy here... not that is for 1000 instances in Altera Cyclone III asic licenses are different Antti
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z