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This is likely to be a problem. Basically the protection diode on the i/o cell will act as a short circuit to a 3.3V signal unless some protection is added. Some details in http://www.xilinx.com/support/answers/= 10835.htm. John Adair Enterpoint Ltd. - Home of Raggedstone1. The PCI Development Board. On 24 Oct, 18:53, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I have a pcb with a Virtex 5 and a programmable clock generator. I want t= o > use an LVDS clcok signal from the clock gen to the fpga. The problem is > that the clock generators default output is two 3.3V signals. The fpga ba= nk > is connected to 1.8V. I would like to know if this will be a problem havi= ng > a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to b= e > LVDS output it should be ok but there is a brief period with the other > signals. > > Thanks > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.comArticle: 143776
On 25 =D0=BE=D0=BA=D1=82, 01:46, doug <x...@xx.com> wrote: > Alex wrote: > > On 24 =D0=BE=D0=BA=D1=82, 00:56, doug <x...@xx.com> wrote: > > >>Alex wrote: > > >>>On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote: > > >>>>Nico Coesel wrote: > > >>>>>-jg <jim.granvi...@gmail.com> wrote: > > >>>>>>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote: > > >>>>>>>So, having decided every-cycle precision is not practical, you hav= e to > >>>>>>>decide over what time you need this 0.1Hz ? > >>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycle= s of > >>>>>>>1.00us, and one cycle of > > >>>>>>( oops, Hit the wrong button...) > >>>>>>Finishing that example: in a pure digital domain > > >>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate > >>>>>>99,999 cycles of 1,00us and one cycle 10ns less > >>>>>>Frequency is then Cycles.Time =C2=A0=3D3D > > >>>>>>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001 > > >>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of > >>>>>>greater than 100ms, with a 10ns timebase. > >>>>>>That certainly is FPGA doable. > > >>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for > >>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less th= an > >>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock > >>>>>cycles each frame. > > >>>>This works fine for locking to a fixed frequency over a narrow range > >>>>and many of us have used it. =C2=A0The deficiency of it is that it is= fine > >>>>for digital clocks but is bad for analog signals. =C2=A0For generatin= g > >>>>arbitrary frequencies, you are better off using a DDS. =C2=A0The DDS = is even > >>>>available as a coregen element for Xilinx (the digital part anyway). > > >>>Xilinx DDS Compiler seems suitable for my project. > > >>You have to decide if the jitter from this is ok for you. The ways > >>of reducing the jitter include increasing the clock rate or by > >>feeding the output through a d/a converter with a baseband > >>filter. The idea is to use the filter to do the interpolation of > >>the zero crossings. This is one of the real nice features of the > >>Analog Devices parts. You can clock at hundreds of MHz and for > >>low frequency outputs, the jitter is effectively zero. > > >>You never told us what kind of output you really want. A digital > >>clock? =C2=A0An audio test signal? =C2=A0What are the distortion and > >>purity specs? > > > Hi doug, > > > I actually have not decided yet on distortion and purity specs.. > > The output has to be a train of amplitude modulated RF pulses whose > > amplitude, waveform, phase, frequency could be set specifically for > > each pulse. Frequency can be in range from 100 kHz to about 50 MHz > > (adjustable in steps equal to 0.1 Hz). > > Your life will be a lot simpler if you just use the Analog Devices > parts. The AD9954 or AD9956 will do most of what you want. You will > need an external D/A for the amplitude control. But I already had bought Xilinx board and study it for a while .. At this point it would be too expensive to switch to Analog Devices and also my project can be implemented on Xilinx FPGA, I believe. Anyway, thanks for advice!Article: 143777
On 25 =D0=BE=D0=BA=D1=82, 01:46, doug <x...@xx.com> wrote: > Alex wrote: > > On 24 =D0=BE=D0=BA=D1=82, 00:56, doug <x...@xx.com> wrote: > > >>Alex wrote: > > >>>On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote: > > >>>>Nico Coesel wrote: > > >>>>>-jg <jim.granvi...@gmail.com> wrote: > > >>>>>>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote: > > >>>>>>>So, having decided every-cycle precision is not practical, you hav= e to > >>>>>>>decide over what time you need this 0.1Hz ? > >>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycle= s of > >>>>>>>1.00us, and one cycle of > > >>>>>>( oops, Hit the wrong button...) > >>>>>>Finishing that example: in a pure digital domain > > >>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate > >>>>>>99,999 cycles of 1,00us and one cycle 10ns less > >>>>>>Frequency is then Cycles.Time =C2=A0=3D3D > > >>>>>>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001 > > >>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of > >>>>>>greater than 100ms, with a 10ns timebase. > >>>>>>That certainly is FPGA doable. > > >>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for > >>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less th= an > >>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock > >>>>>cycles each frame. > > >>>>This works fine for locking to a fixed frequency over a narrow range > >>>>and many of us have used it. =C2=A0The deficiency of it is that it is= fine > >>>>for digital clocks but is bad for analog signals. =C2=A0For generatin= g > >>>>arbitrary frequencies, you are better off using a DDS. =C2=A0The DDS = is even > >>>>available as a coregen element for Xilinx (the digital part anyway). > > >>>Xilinx DDS Compiler seems suitable for my project. > > >>You have to decide if the jitter from this is ok for you. The ways > >>of reducing the jitter include increasing the clock rate or by > >>feeding the output through a d/a converter with a baseband > >>filter. The idea is to use the filter to do the interpolation of > >>the zero crossings. This is one of the real nice features of the > >>Analog Devices parts. You can clock at hundreds of MHz and for > >>low frequency outputs, the jitter is effectively zero. > > >>You never told us what kind of output you really want. A digital > >>clock? =C2=A0An audio test signal? =C2=A0What are the distortion and > >>purity specs? > > > Hi doug, > > > I actually have not decided yet on distortion and purity specs.. > > The output has to be a train of amplitude modulated RF pulses whose > > amplitude, waveform, phase, frequency could be set specifically for > > each pulse. Frequency can be in range from 100 kHz to about 50 MHz > > (adjustable in steps equal to 0.1 Hz). > > Your life will be a lot simpler if you just use the Analog Devices > parts. The AD9954 or AD9956 will do most of what you want. You will > need an external D/A for the amplitude control. Hi doug, As a biginner I wonder - what is main difference between design methods used in Analog Device line of products and FPGA-based solutions? As I understand, Analog Device products are all signal processors, i.e. their hardware cannot be changed meanwhile FPGA-based solutions allow re/programming of hardware and software as well. Is my understanding correct?Article: 143778
On Oct 24, 2:37=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote:
> On Oct 24, 3:44=A0am, GrIsH <grishkun...@gmail.com> wrote:
>
>
>
> > On Oct 23, 5:19=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote=
:
>
> > > Goran_Bilski <goran.bil...@xilinx.com> wrote:
>
> > > (snip)
>
> > > >MicroBlazeuse big-endian byte-ordering and big-endian bit ordering.
> > > > This is a legacy from PowerPC and CoreConnect bus.
> > > > It's not only PowerPC who uses big-endian ordering.
> > > > As much as the msb bitnumberchanges for big-endian so does the lsb
> > > > bitnumberfor little-endian.
>
> > > (snip)
>
> > > > I do however prefer big-endian byte order since when dumping bytes
> > > > from memory will show the word in the right order.
> > > > We tend to write numbers with the most significant numbers to the l=
eft
> > > > and that is how big-endian is storing bytes within a word.
>
> > > The VAX/VMS DUMP program prints the HEX data right to left, and
> > > the ASCII data left to right with the address in the middle.
> > > Big endian avoids strange solutions like that.
>
> > > -- glen
>
> > lot of thanks to all of you that you people have great discussion on
> > this topic..........i'm new to ubalze and this is my first project in
> > ublaze and i got the chance to know lots of things from these
> > discussions........I'm so sorry that i could not be a part of this
> > discussion for one week because i have a festival here which is one of
> > our great festival and now i'm in course.............
>
> > =A0i gave continuity to my work from yesterday,i simulated my design
> > with BFM(Bus Function Module) simulation and found the result bit
> > confusing .....
>
> > I already told that i'm new one..You people have great discussion its
> > fine!! But still my problem is with me, i think its very easy for you
> > people....
>
> > How is this happen??
> > I have signal "cnt" of integer type and was mapped to IP2Bus_Data as
> > IP2Bus_Data(0 to 31) <=3D std_logic_vector(to_signed(cnt,32));
>
> > after simulation , i found the data in the PLB bus was in 2's
> > complement form but i think it should be in signed form so how??
>
> > i mean.....
> > if i send +4(that is value of "cnt"), data in the PLB bus was
> > "00000000000000000000000000000100"(32 bit)
> > if -4 was send then it was "11111111111111111111111111111100" BUT i
> > think in signed form it should be
> > "10000000000000000000000000000100"......
>
> > -Grish- Hide quoted text -
>
> > - Show quoted text -
>
> Hi,
>
> The function to_signed converts it's to 2-complement format which is
> the default way of handlingnegativenumbers.
> The "sign,magnitude" format is not used that much since all arithmetic
> operations has to be handled specially while 2-complement is just
> normal operations.
>
> If you really want the "sign,magnitude" format, you have to manually
> set the sign bit and to a "abs" on the cnt value.
>
> G=F6ran
hey guys!!.....i found that sending/receiving a negative number is
not a problem. The real problem is the value of 'cnt' get
changed abruptly to next value(like 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11 then abruptly it becomes 4101/-3510,random number) after some
regular positive /negative count of encoder pulses........
Is this problem is due to my asynchronous design which is irrespective
of IP2Bus_clk??
my design:
-----------------
my_uut:process(channel_A) is
begin
if(channel_A 'event and channel_A=3D'1') then
direction<=3D '1' and channel_B;
if(direction=3D'0') then
cnt<=3Dcnt+1;
else
cnt<=3Dcnt-1;
end if;
end if;
if(cnt<0) then
sign_bit<=3D'1';
else
sign_bit<=3D'0';
end if;
end process;
channel_A and channel_B are quadrature encoder pulses(with 90 degree
phase difference) as:
--------- --------- ----------
| | | | | |
channel_A:------- -------- ---------
----------
--------- ---------
----------
| | | |
| |
channel_B:----------- --------- ---------
-------------
-grish
Article: 143779luudee pisze: > I assume the original poster was targeting commercial > ventures ? > > Some history ... > > This has been attempted at OpenCOres.org. When I was still > contributing to OpenCores (some 10 years ago), I too had > this ideological view of a community of like minded people > who would attempt to solve various problems. [...] Yuup, you right Rudi. Our job - FPGA - is to specific to work in large virtual teams. Knowledge base is usenet I mean "comp.arch.fpga" and others. There is www.odesk.com for freelancers, but no one want to trust engineers somewhere, when the product of our job must be embeded in specific hardware. IMHO, there is no sense to create new websites, new forums etc. But idea to create "open" database of people who have experience in our profession is great. It could be not nice for head hunters but, everyone can introduce how and wherever he/she likes. Regards, Jerzy GburArticle: 143780
On Oct 25, 10:38=A0am, GrIsH <grishkun...@gmail.com> wrote:
> On Oct 24, 2:37=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote:
>
>
>
> > On Oct 24, 3:44=A0am, GrIsH <grishkun...@gmail.com> wrote:
>
> > > On Oct 23, 5:19=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wro=
te:
>
> > > > Goran_Bilski <goran.bil...@xilinx.com> wrote:
>
> > > > (snip)
>
> > > > >MicroBlazeuse big-endian byte-ordering and big-endian bit ordering=
.
> > > > > This is a legacy from PowerPC and CoreConnect bus.
> > > > > It's not only PowerPC who uses big-endian ordering.
> > > > > As much as the msb bitnumberchanges for big-endian so does the ls=
b
> > > > > bitnumberfor little-endian.
>
> > > > (snip)
>
> > > > > I do however prefer big-endian byte order since when dumping byte=
s
> > > > > from memory will show the word in the right order.
> > > > > We tend to write numbers with the most significant numbers to the=
left
> > > > > and that is how big-endian is storing bytes within a word.
>
> > > > The VAX/VMS DUMP program prints the HEX data right to left, and
> > > > the ASCII data left to right with the address in the middle.
> > > > Big endian avoids strange solutions like that.
>
> > > > -- glen
>
> > > lot of thanks to all of you that you people have great discussion on
> > > this topic..........i'm new to ubalze and this is my first project in
> > > ublaze and i got the chance to know lots of things from these
> > > discussions........I'm so sorry that i could not be a part of this
> > > discussion for one week because i have a festival here which is one o=
f
> > > our great festival and now i'm in course.............
>
> > > =A0i gave continuity to my work from yesterday,i simulated my design
> > > with BFM(Bus Function Module) simulation and found the result bit
> > > confusing .....
>
> > > I already told that i'm new one..You people have great discussion its
> > > fine!! But still my problem is with me, i think its very easy for you
> > > people....
>
> > > How is this happen??
> > > I have signal "cnt" of integer type and was mapped to IP2Bus_Data as
> > > IP2Bus_Data(0 to 31) <=3D std_logic_vector(to_signed(cnt,32));
>
> > > after simulation , i found the data in the PLB bus was in 2's
> > > complement form but i think it should be in signed form so how??
>
> > > i mean.....
> > > if i send +4(that is value of "cnt"), data in the PLB bus was
> > > "00000000000000000000000000000100"(32 bit)
> > > if -4 was send then it was "11111111111111111111111111111100" BUT i
> > > think in signed form it should be
> > > "10000000000000000000000000000100"......
>
> > > -Grish- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi,
>
> > The function to_signed converts it's to 2-complement format which is
> > the default way of handlingnegativenumbers.
> > The "sign,magnitude" format is not used that much since all arithmetic
> > operations has to be handled specially while 2-complement is just
> > normal operations.
>
> > If you really want the "sign,magnitude" format, you have to manually
> > set the sign bit and to a "abs" on the cnt value.
>
> > G=F6ran
>
> hey guys!!.....i found that sending/receivinganegativenumberis
> not =A0a problem. The real problem is the value of 'cnt' get
> changed abruptly to next value(like 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
> 11 then abruptly it becomes 4101/-3510,randomnumber) after some
> regular positive /negativecount of encoder pulses........
>
> Is this problem is due to my asynchronous design which is irrespective
> of IP2Bus_clk??
>
> my design:
> -----------------
>
> =A0my_uut:process(channel_A) is
>
> =A0 =A0 begin
>
> =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and channel=
_B;
> =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1;
>
> =A0 =A0 =A0 =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1;
>
> =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
>
> =A0 =A0 =A0 =A0 if(cnt<0) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sign_bit<=3D'1';
> =A0 =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sign_bit<=3D'0';
> =A0 =A0 =A0 =A0 end if;
>
> =A0 =A0 end process;
>
> channel_A and channel_B are quadrature encoder pulses(with 90 degree
> phase difference) as:
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--------- =A0 =A0 =A0 =A0-=
-------- =A0 =A0 =A0 =A0 ----------
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0| =A0 =A0=
=A0 | =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 |
> channel_A:------- =A0 =A0 =A0 =A0 -------- =A0 =A0 =A0 =A0 ---------
> ----------
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--------- =A0 =A0 =
=A0 =A0 ---------
> ----------
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0|=
=A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 |
> | =A0 =A0 =A0 =A0 |
> channel_B:----------- =A0 =A0 =A0 =A0 --------- =A0 =A0 =A0 =A0 ---------
> -------------
>
> -grish
channel_A and channel_B are:
-------- ---------
| | | |
------- -------- -----------
--------- ---------
| | | |
----------- --------- ------------------
Article: 143781Hello group, I've started working on Virtex 4 (ML410). the PDF on Xlinx website point to ml410_bsb_design.zip, ml410_overview_setup.ppt and also ml410_bsb_vxworks_bsp_proj_creation.ppt but I couldn't find them. Does anybody have them or can give me a link to where there are ? Thanks, AmitArticle: 143782
On Oct 25, 11:18=A0am, GrIsH <grishkun...@gmail.com> wrote: > On Oct 25, 10:38=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > > > On Oct 24, 2:37=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote: > > > > On Oct 24, 3:44=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > > > On Oct 23, 5:19=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> w= rote: > > > > > > Goran_Bilski <goran.bil...@xilinx.com> wrote: > > > > > > (snip) > > > > > > >MicroBlazeuse big-endian byte-ordering and big-endian bit orderi= ng. > > > > > > This is a legacy from PowerPC and CoreConnect bus. > > > > > > It's not only PowerPC who uses big-endian ordering. > > > > > > As much as the msb bitnumberchanges for big-endian so does the = lsb > > > > > > bitnumberfor little-endian. > > > > > > (snip) > > > > > > > I do however prefer big-endian byte order since when dumping by= tes > > > > > > from memory will show the word in the right order. > > > > > > We tend to write numbers with the most significant numbers to t= he left > > > > > > and that is how big-endian is storing bytes within a word. > > > > > > The VAX/VMS DUMP program prints the HEX data right to left, and > > > > > the ASCII data left to right with the address in the middle. > > > > > Big endian avoids strange solutions like that. > > > > > > -- glen > > > > > lot of thanks to all of you that you people have great discussion o= n > > > > this topic..........i'm new to ubalze and this is my first project = in > > > > ublaze and i got the chance to know lots of things from these > > > > discussions........I'm so sorry that i could not be a part of this > > > > discussion for one week because i have a festival here which is one= of > > > > our great festival and now i'm in course............. > > > > > =A0i gave continuity to my work from yesterday,i simulated my desig= n > > > > with BFM(Bus Function Module) simulation and found the result bit > > > > confusing ..... > > > > > I already told that i'm new one..You people have great discussion i= ts > > > > fine!! But still my problem is with me, i think its very easy for y= ou > > > > people.... > > > > > How is this happen?? > > > > I have signal "cnt" of integer type and was mapped to IP2Bus_Data a= s > > > > IP2Bus_Data(0 to 31) <=3D std_logic_vector(to_signed(cnt,32)); > > > > > after simulation , i found the data in the PLB bus was in 2's > > > > complement form but i think it should be in signed form so how?? > > > > > i mean..... > > > > if i send +4(that is value of "cnt"), data in the PLB bus was > > > > "00000000000000000000000000000100"(32 bit) > > > > if -4 was send then it was "11111111111111111111111111111100" BUT i > > > > think in signed form it should be > > > > "10000000000000000000000000000100"...... > > > > > -Grish- Hide quoted text - > > > > > - Show quoted text - > > > > Hi, > > > > The function to_signed converts it's to 2-complement format which is > > > the default way of handlingnegativenumbers. > > > The "sign,magnitude" format is not used that much since all arithmeti= c > > > operations has to be handled specially while 2-complement is just > > > normal operations. > > > > If you really want the "sign,magnitude" format, you have to manually > > > set the sign bit and to a "abs" on the cnt value. > > > > G=F6ran > > > hey guys!!.....i found that sending/receivinganegativenumberis > > not =A0a problem. The real problem is the value of 'cnt' get > > changed abruptly to next value(like 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, > > 11 then abruptly it becomes 4101/-3510,randomnumber) after some > > regular positive /negativecount of encoder pulses........ > > > Is this problem is due to my asynchronous design which is irrespective > > of IP2Bus_clk?? > > > my design: > > ----------------- > > > =A0my_uut:process(channel_A) is > > > =A0 =A0 begin > > > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and chann= el_B; > > =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1; > > > =A0 =A0 =A0 =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1; > > > =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end if; > > > =A0 =A0 =A0 =A0 if(cnt<0) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sign_bit<=3D'1'; > > =A0 =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sign_bit<=3D'0'; > > =A0 =A0 =A0 =A0 end if; > > > =A0 =A0 end process; > > > channel_A and channel_B are quadrature encoder pulses(with 90 degree > > phase difference) as: > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--------- =A0 =A0 =A0 = =A0--------- =A0 =A0 =A0 =A0 ---------- > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0| =A0 = =A0 =A0 | =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 | > > channel_A:------- =A0 =A0 =A0 =A0 -------- =A0 =A0 =A0 =A0 --------- > > ---------- > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--------- =A0 = =A0 =A0 =A0 --------- > > ---------- > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 = =A0| =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 | > > | =A0 =A0 =A0 =A0 | > > channel_B:----------- =A0 =A0 =A0 =A0 --------- =A0 =A0 =A0 =A0 -------= -- > > ------------- > > > -grish > > channel_A and channel_B are: > =A0 =A0 =A0 =A0 -------- =A0 =A0 =A0 =A0 =A0 =A0--------- > =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0| > ------- =A0 =A0 =A0 =A0 =A0 -------- =A0 =A0 =A0 =A0 =A0 =A0----------- > =A0 =A0 =A0 =A0 =A0 =A0 --------- =A0 =A0 =A0 =A0 =A0 =A0 --------- > =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0| =A0 = =A0 =A0 =A0 =A0| > ----------- =A0 =A0 =A0 =A0 =A0 =A0--------- =A0 =A0 =A0 =A0 =A0 =A0---- ye.....my problem is get solved!! thanx all of you guys!!Article: 143783
Scorpiion wrote: > Hi, I have just started out with some VHDL in school and would like to have > something at home to play with. I'm not sure of CPLD vs FPGA for my use, > but CPLD feel more suited for smaller projects I guess. My question is how > Linux is supported as developmentplatform? You might want to consider a BaseBoard4 from Demand Peripherals. I designed the board _specifically_ to be used with Linux. This means that it does not use JTAG for download and so does not need the windrv stuff. The board uses a USB-to-serial FTDI part and so downloading code to the board is as simple as cat myfpgacode.bin > /dev/ttyUSB0 There is a tutorial on how to install the Xilinx tools on Linux, how to build a simple counter (i.e. "Hello, World!" for an FPGA), and how to download and test the code on a BaseBoard4. The build environment uses vi and make. Check it out: http://www.demandperipherals.com/docs/CmdLineFPGA.pdf The board costs $100 and has a Spartan 3E 100K on it. This is neither particularly cheap or over-powered but it sure is nice to use Linux, vi, and make for FPGA development. Bob SmithArticle: 143784
Okey, many answers, thanks! :) I will need to look this up a little bit more. But all these "developmentboards", is it like a programmer in those so I can program other chips than the one on the board? Or is it not like with MCU where you have a separated programmer? At school we have that but when I look at most homepages there are always these development boards... So, is development board used much more that just a bare chip and a programmer? Maybe because the chip's are so complex that they always need a custom PCB? How much does a CPLD/FPGA programmer cost? Can a microcontroller "program" an CPLD/FPGA? It should be able to do that I think but I have never does, I wonder how usual it is? And a last question, I have read that some chip has a special memory that get loaded into the chip a boot, is that more common then that the CPLD/FPGA stores it's instructions? (I think that CPLD usually or always store the instructions in them self?) Regards --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143785
On Oct 25, 2:23=A0pm, akohan <amit.ko...@gmail.com> wrote: > Hello group, > > I've started working on Virtex 4 (ML410). the PDF on Xlinx website > point to > > ml410_bsb_design.zip, ml410_overview_setup.ppt and also > ml410_bsb_vxworks_bsp_proj_creation.ppt but I couldn't find them. Does > anybody have them or can give me a link to where there are ? > > Thanks, > Amit http://www.xilinx.com/products/boards/ml410/ Cheers, Jim http://myfpgablog.blogspot.com/Article: 143786
Has anyone heard of software partial configuration ? Can someone please explain to me the differences between PR and SPR, and which one is the best in your opinion in terms on power utilization, performance, and cost. Thanks,Article: 143787
Hello Want to write a code in VHDL for aynschronous to synchronous communication. From PC i need to take asynchronous data and convert to synchronous data in code.. if any one knw abt this let me know its very urgent please let me know the detailsArticle: 143788
On Oct 22, 8:21=A0pm, yuebing <jiangyueb...@gmail.com> wrote:
> How does XilFATFS support the above function?
It doesn't. It is a very minimal filesystem implementation.
For end-of-file detection, you would have to compare the count values
returned by sysace_fwrite() / sysace_fread() against the number of
objects you requested to be written or read. But for something like
fseek(), there's no easy answer except to track the file position
yourself and perform dummy read operations, closing and reopening the
file if you ever need to go backwards.
You might try doing as much of your data manipulation as possible in
memory, and only read and write files all-at-once.
-Ben-
Article: 143789On Oct 26, 3:29=A0am, Smi <smi...@gmail.com> wrote: > Hello > > Want to write a code in VHDL for aynschronous to synchronous > communication. From PC i need to take asynchronous data and convert to > synchronous data in code.. if any one knw abt this let me know its > very urgent please let me know the details Are you talking about a UART? If you are, check on opencores.org HTH -Dave PollumArticle: 143790
Howdy All, Has anybody got the "Receiver Detect" feature to work in Virtex 5 VFX (with GTX transceivers) ? I have read "RocketIO GTX Transceiver User Guide" (UG198) from beginning to end, and am following the procedure described exactly as stated. I Am always getting "Receiver Not Present" status, even though external equipment (Protocol Analyser and Protocol Generator) properly report Receiver present or not present, depending on the setup. Any suggestion, and pointers appreciated. Cheers, rudiArticle: 143791
Alex wrote: > On 25 окт, 01:46, doug <x...@xx.com> wrote: > >>Alex wrote: >> >>>On 24 окт, 00:56, doug <x...@xx.com> wrote: >> >>>>Alex wrote: >> >>>>>On 23 ÏËÔ, 20:40, doug <x...@xx.com> wrote: >> >>>>>>Nico Coesel wrote: >> >>>>>>>-jg <jim.granvi...@gmail.com> wrote: >> >>>>>>>>On Oct 23, 11:51=A0am, -jg <jim.granvi...@gmail.com> wrote: >> >>>>>>>>>So, having decided every-cycle precision is not practical, you have to >>>>>>>>>decide over what time you need this 0.1Hz ? >>>>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycles of >>>>>>>>>1.00us, and one cycle of >> >>>>>>>>( oops, Hit the wrong button...) >>>>>>>>Finishing that example: in a pure digital domain >> >>>>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate >>>>>>>>99,999 cycles of 1,00us and one cycle 10ns less >>>>>>>>Frequency is then Cycles.Time =3D >> >>>>>>>>100000/(99999*1.0u + (1u-10n)) =3D 1000000.10000001 >> >>>>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of >>>>>>>>greater than 100ms, with a 10ns timebase. >>>>>>>>That certainly is FPGA doable. >> >>>>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for >>>>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less than >>>>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock >>>>>>>cycles each frame. >> >>>>>>This works fine for locking to a fixed frequency over a narrow range >>>>>>and many of us have used it. The deficiency of it is that it is fine >>>>>>for digital clocks but is bad for analog signals. For generating >>>>>>arbitrary frequencies, you are better off using a DDS. The DDS is even >>>>>>available as a coregen element for Xilinx (the digital part anyway). >> >>>>>Xilinx DDS Compiler seems suitable for my project. >> >>>>You have to decide if the jitter from this is ok for you. The ways >>>>of reducing the jitter include increasing the clock rate or by >>>>feeding the output through a d/a converter with a baseband >>>>filter. The idea is to use the filter to do the interpolation of >>>>the zero crossings. This is one of the real nice features of the >>>>Analog Devices parts. You can clock at hundreds of MHz and for >>>>low frequency outputs, the jitter is effectively zero. >> >>>>You never told us what kind of output you really want. A digital >>>>clock? An audio test signal? What are the distortion and >>>>purity specs? >> >>>Hi doug, >> >>>I actually have not decided yet on distortion and purity specs.. >>>The output has to be a train of amplitude modulated RF pulses whose >>>amplitude, waveform, phase, frequency could be set specifically for >>>each pulse. Frequency can be in range from 100 kHz to about 50 MHz >>>(adjustable in steps equal to 0.1 Hz). >> >>Your life will be a lot simpler if you just use the Analog Devices >>parts. The AD9954 or AD9956 will do most of what you want. You will >>need an external D/A for the amplitude control. > > > But I already had bought Xilinx board and study it for a while .. At > this point it would be too expensive to switch to Analog Devices and > also my project can be implemented on Xilinx FPGA, I believe. Anyway, > thanks for advice! You can make a DDS suitable as a clock for a digital system in an FPGA. If you want an RF source suitable for communication, that is not going to work. You may also have trouble getting the FPGA to run quickly enough to get your 50MHz output cleanly. You will lose speed adding in the phase shift. You cannot change the amplitude more than very coarsely etc. If this is a student project, you can have some fun with it.Article: 143792
Alex wrote: > On 25 окт, 01:46, doug <x...@xx.com> wrote: > >>Alex wrote: >> >>>On 24 окт, 00:56, doug <x...@xx.com> wrote: >> >>>>Alex wrote: >> >>>>>On 23 ÏËÔ, 20:40, doug <x...@xx.com> wrote: >> >>>>>>Nico Coesel wrote: >> >>>>>>>-jg <jim.granvi...@gmail.com> wrote: >> >>>>>>>>On Oct 23, 11:51=A0am, -jg <jim.granvi...@gmail.com> wrote: >> >>>>>>>>>So, having decided every-cycle precision is not practical, you have to >>>>>>>>>decide over what time you need this 0.1Hz ? >>>>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycles of >>>>>>>>>1.00us, and one cycle of >> >>>>>>>>( oops, Hit the wrong button...) >>>>>>>>Finishing that example: in a pure digital domain >> >>>>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate >>>>>>>>99,999 cycles of 1,00us and one cycle 10ns less >>>>>>>>Frequency is then Cycles.Time =3D >> >>>>>>>>100000/(99999*1.0u + (1u-10n)) =3D 1000000.10000001 >> >>>>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of >>>>>>>>greater than 100ms, with a 10ns timebase. >>>>>>>>That certainly is FPGA doable. >> >>>>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for >>>>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less than >>>>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock >>>>>>>cycles each frame. >> >>>>>>This works fine for locking to a fixed frequency over a narrow range >>>>>>and many of us have used it. The deficiency of it is that it is fine >>>>>>for digital clocks but is bad for analog signals. For generating >>>>>>arbitrary frequencies, you are better off using a DDS. The DDS is even >>>>>>available as a coregen element for Xilinx (the digital part anyway). >> >>>>>Xilinx DDS Compiler seems suitable for my project. >> >>>>You have to decide if the jitter from this is ok for you. The ways >>>>of reducing the jitter include increasing the clock rate or by >>>>feeding the output through a d/a converter with a baseband >>>>filter. The idea is to use the filter to do the interpolation of >>>>the zero crossings. This is one of the real nice features of the >>>>Analog Devices parts. You can clock at hundreds of MHz and for >>>>low frequency outputs, the jitter is effectively zero. >> >>>>You never told us what kind of output you really want. A digital >>>>clock? An audio test signal? What are the distortion and >>>>purity specs? >> >>>Hi doug, >> >>>I actually have not decided yet on distortion and purity specs.. >>>The output has to be a train of amplitude modulated RF pulses whose >>>amplitude, waveform, phase, frequency could be set specifically for >>>each pulse. Frequency can be in range from 100 kHz to about 50 MHz >>>(adjustable in steps equal to 0.1 Hz). >> >>Your life will be a lot simpler if you just use the Analog Devices >>parts. The AD9954 or AD9956 will do most of what you want. You will >>need an external D/A for the amplitude control. > > > Hi doug, > > As a biginner I wonder - what is main difference between design > methods used in Analog Device line of products and FPGA-based > solutions? As I understand, Analog Device products are all signal > processors, i.e. their hardware cannot be changed meanwhile FPGA-based > solutions allow re/programming of hardware and software as well. Is my > understanding correct? Yes, but a bit misleading. The FPGA consists of a large array of similiar pieces which can be arranged to do what you want. The AD parts are dedicated chips which have sections which can be made from and FPGA and sections which cannot. The D/A converter in the AD parts is an analog device which cannot be built in an FPGA. Also, the AD devices work at a higher clock rate than you will get in an inexpensive FPGA. You hopefully are just doing a school project where the experience will do you some goog rather than trying to make a commercial product.Article: 143793
Implementing a full DDFS in the FPGA, with sine lookup table AND D/A converter, Is only required when you want (need) a sine wave. If you want (need) a regular clock, then taking the carry out of the accumulator/register is just fine. Yes, the adjustment is one whole clock period, so the peak to peak jitter is the same as the clock period of the DDFS. As an example, there is often a "real time clock" project for various simple FPGA boards, that use the on-board crystal oscillator. Given the crystal oscillator is +/- 50 ppm (or worse), the clock will probably gain, or lose time in 24 hours, such that you will notice it is not keeping very good time. An exercise is to replace the "one second" clock to the real time clock (for seconds, minutes, hours, day, etc.) with a 36 bit DDFS running from 50 MHz. Now, to adjust the one second time click, you can increment, or decrement, the phase accumulator constant (frequency setting) until you are as close as how have the patience to play with it. I did this when I took the FPGA class here at Xilinx ten years ago. I used DDFS extensively to produce network clocks in the synchronous network hierarchy products I alluded to earlier. I used a 48 bit DDFS, as I wanted the synthesizer step size to be far less than the stratum 1 reference accuracy (+/- 1E-11 for cesium/GPS, and 3.5E-15 for lsb of 48 bit DDFS). The 48 bit DDFS was at the heart of the entire product line (inside a Xilinx FPGA). Since this was for the network, and jitter is really important, I would take the output of the DDFS, send it outside the FPGA, to a PLL using a VCXO, which had a ten to thirty second time constant (pole) in the feedback loop. The result was immeasurable jitter on the T1, or E1 clock references (the only jitter present was from the data itself, and the framing pattern). As is often the case, one doesn't need everything in the Analog Devices DDS chip (but it is incredibly convenient, and a very good choice if you are building a variable frequency oscillator for a radio receiver!). http://www.nitehawk.com/rasmit/vna_dds/dds-x_v1_6.pdf You could do the same thing with a FPGA, but you would need an external D/A converter (as well as all the analog filtering which the AD DDS also requires).Article: 143794
On Oct 23, 7:08=A0pm, "wixization" <mosfets....@gmail.com> wrote: > Hi everyone. > > can anybody tell why KCPSM3 assembler doesnt run on my windows sp2 versio= n > 2002. > I tried it on one of my friendz pc but it did'nt run their either. we bot= h > have different version of windows and picoblaze assembler for spartan 3 > KCPSM3 cannot be executed on my PC. Help plzz. i need it. > > thx in advance Couple of things: 1) What version of KCPSM3? 2) How are you trying to run it? 3) Drop the 'leet crap'. Please is spelled "please", not "plzz". ALArticle: 143795
On Oct 17, 3:41=A0pm, rickman <gnu...@gmail.com> wrote:
> On Oct 17, 3:11=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>
>
>
> > rickman <gnu...@gmail.com> wrote:
>
> > (snip, then I wrote)
>
> > >> Which seems simpler and more natural: ?
> > >> ? ? ? ? ? [8*n,8*n+7] ? ?or ? ?[31-8*n,24-8*n]
> > >> I do know that it took me longer to write the second one and
> > >> to verify that it did what I wanted it to do. ?
> > >> Or are you asking about the preference of big-endian for
> > >> processor design?
>
> > > I don't know what the above equations are for. =A0I have never used
> > > either forms for anything that I can recall.
>
> > That is the verilog from. =A0Most of the time I can read VHDL and
> > get the right idea, but I have never written it. =A0(I did some
> > VHDL to verilog conversions that worked, never the other way.)
>
> The verilog form for what? =A0I have never used a calculation like
> that. =A0What is n? =A0Why are you performing this calculation? =A0What i=
s
> the context.
All Glen is trying to do is index individual bits in the word. n is
the index.
If you've created a "custom IP core" for a Xilinx EDK project, then
undoubtedly you've run into the following construct:
for byte_index in 0 to (C_SLV_DWIDTH/8) - 1 loop
if (Bus2IP_BE(byte_index) =3D '1') then
my_register(byte_index*8 to byte_index*8+7) <=3D
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
Here, C_SLV_DWIDTH is defined as the width of the data bus (for
MicroBlaze this is 32 bits). byte_index iterates over the number of
byte-lane enables (Bus2IP_BE) so for a 32-bit data bus you have four
BEs. If the byte-lane is enabled then you assign all of the bits in
that byte. If you had a PPC system your data bus could be 64 or 128
bits wide so you'd have eight BEs or sixteen BEs.
The point here is that the same code handles all of these cases. This
is VERY useful.
> Like I said above, I have no idea why you are using a complicated
> calculation to specify the bit of a word. =A0It is extremely seldom that
> I need to select a bit range based on a byte address the way you have
> shown. =A0In fact, I can't remember ever doing that.
The example above shows why we use this "extremely complicated
calculation." And really -- it's not complicated at all.
The code you show later in this thread has the explicit bit
assignments, which is excellent for readability but is not at all
scalable.
> Ignoring that, I don't see this one calculation as being a driving
> reason to choose a numbering scheme for a bus. =A0It seems to me to be
> infinitely more useful to have the index correspond to the weight of
> each bit to facilitate the calculation of the values in this signal.
The numbering scheme goes back to the decisions made by IBM at the
time they were defining the architecture used by the PPC and the
MicroBlaze. Since it's an IBM bus, Xilinx uses the IBM nomenclature.
Note that BE(0) in my example above _always_ refers to the MOST
significant byte lane -- ALWAYS bits (0 to 7) which are the most
significant. If you think about it, this actually makes more sense
than the little-endian notion where the MS bits are numbered based on
the number of bits in the word. In a 32-bit world, the MS byte lane is
3 and the bits are (31 downto 24). In a 64-bit world, the MS byte lane
is 7 and the bits are (63 downto 56).
Really, this is not difficult at all.
-a
Article: 143796On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote: > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the > > entire project just corrupted - when "rerun all" it TOOK the topmodule > > source from "nowhere" - nomatter how you change your topmodule it > > still lock the topmodule source fom that mystery source > > > Oh my goodness > > The "Cleanup Project Files" under the "Project" menu can solve many of > these problems. > > kevin Thanks for suggestion - it does something difference when I tried to clean the project but it still lock the source from "nowhere" You know what? I've just started a brand new project and copy every single bit from the current design - it let me play for a couple rounds before doing exact the same thing That's totally frustrating - fortunatly every time successfully routing I backup rite away - btw/ the Xilinx snapshot does not help at all - it restore the junk project THis is a night mareArticle: 143797
On Oct 26, 12:43=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote: > > > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t= he > > > entire project just corrupted - when "rerun all" it TOOK the topmodul= e > > > source from "nowhere" - nomatter how you change your topmodule it > > > still lock the topmodule source fom that mystery source > > > > Oh my goodness > > > The "Cleanup Project Files" under the "Project" menu can solve many of > > these problems. > > > kevin > > Thanks for suggestion - it does something difference when I tried to > clean the project but it still lock the source from "nowhere" > > You know what? I've just started a brand new project and copy every > single bit from the current design - it let me =A0play for a couple > rounds before doing exact the same thing > > That's totally frustrating - fortunatly every time successfully > routing I backup rite away - btw/ the Xilinx snapshot does not help at > all - it restore the junk project > > THis is a night mare If you hover over the file in the source pane it will display the path to the source - verify that is correct. Also be careful when adding the source to the project as there is an option to "copy" the file to the project directory rather than using it in place. I have only had a problem once and the "cleanup project files" command corrected it. kevinArticle: 143798
On Oct 26, 2:43=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote: > > > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t= he > > > entire project just corrupted - when "rerun all" it TOOK the topmodul= e > > > source from "nowhere" - nomatter how you change your topmodule it > > > still lock the topmodule source fom that mystery source > > > > Oh my goodness > > > The "Cleanup Project Files" under the "Project" menu can solve many of > > these problems. > > > kevin > > Thanks for suggestion - it does something difference when I tried to > clean the project but it still lock the source from "nowhere" > > You know what? I've just started a brand new project and copy every > single bit from the current design - it let me =A0play for a couple > rounds before doing exact the same thing > > That's totally frustrating - fortunatly every time successfully > routing I backup rite away - btw/ the Xilinx snapshot does not help at > all - it restore the junk project > > THis is a night mare I may doing somthing stupid here, but I found a way temporary to deal with this night mare - In my project I always keep two top modules - One is the real design (big circuit) and the other is a dummy topmodule (just an input -ouput) Now everytime I attemp to route the real desing - I switch to set topmule as the dummy first - and run the XST first - if I see it route quick (less than a minute) then I know the XST doing ok - if it synthesize the dummy with tons of nets and macros - then it lock to the mystery topmodule source already. If it happens thta way then I would restore the archieve to save time chasing my own tail around Wow, what a night mareArticle: 143799
On Oct 26, 1:26=A0pm, Andy Peters <goo...@latke.net> wrote: > > The numbering scheme goes back to the decisions made by IBM at the > time they were defining the architecture used by the PPC and the > MicroBlaze. Since it's an IBM bus, Xilinx uses the IBM nomenclature. Any idea what those decisions were made on? The only advantage I have seen for little endian is the niceness of byte dumps. But then I guess I don't want to open that can of worms. Even with little endian byte addressing, I don't agree that little ending bit numbering goes with it to any significant advantage. > Note that BE(0) in my example above _always_ refers to the MOST > significant byte lane -- ALWAYS bits (0 to 7) which are the most > significant. If you think about it, this actually makes more sense > than the little-endian notion where the MS bits are numbered based on > the number of bits in the word. In a 32-bit world, the MS byte lane is > 3 and the bits are (31 downto 24). In a 64-bit world, the MS byte lane > is 7 and the bits are (63 downto 56). > > Really, this is not difficult at all. No, it's not especially difficult, but I have never needed that particular calculation. I find it much, much simpler to use the convention that is much more dominant where a bit index is calculated without any reference to the byte. Only a small portion of HDL code is used in microprocessor interfaces. In fact, the OP's example requires him to convert between the two. So what is the point of a small savings with that one calculation when there are so many other issues that are created in the interface? The OP's case is a perfect example, I couldn't tell from his code where he intended the 16 bit quantity to show up on the bus and I couldn't tell if he intended to sign extend the quantity or if it even mattered. Sure, you may be some small improvement in HDL code that is entirely internal to the processor, but that is just a small microcosm. That decision has impacts outside of that area. Rick
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