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On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote: > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > > > > > Antti, > > > I enjoy your responses they are to the bone, but valid. The right > > people are engineers who wish to pick this project up for their > > benefit, yes antti as well as mine. The engineer would be some one > > willing to pay a bit extra for one of four boards available with all > > the design file associated with the boards. These files are the meat > > of the work and would allow an engineer to make changes from the > > current form to one more suitable to their needs, if necessary. Open > > Source license also allows anyone willing to manufacture this product > > for sale and profit of their own, royalty free. Development and > > testing is a huge cost and has been paid for in this project. Yes, > > antti schematics are available for many of the development boards but > > firmware and how things are implemented are not. Digilent for example > > produced a project that only required a usb to miniB connection to the > > board to program utilizing Xilinx's impact program, how did they do > > that? They will not tell me, I understand, but it was worth asking. > > Yes, there are vendors who do not make all of their design files > available for FPGA development boards. =A0But for the most part, the > FPGA makers provide development boards and make all of their design > files available. =A0I think they do this to reduce the amount of support > required. =A0If you have all of the design files, you don't need to ask > so many questions, you can just look it up yourself. =A0So in that > sense, there are a number of open source FPGA development boards. > Just not with the freedom to make your own copies although I can't > imagine an FPGA vendor would object since you would be putting their > parts on it! > > > If the 4 layer printed circuit board was manufactured for $6 is that > > to expensive? > > No one can have a board manufactured for $6. =A0You might be able to get > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That is > one of the problems with open source hardware. =A0It is "hard" and often > difficult to make on your own. =A0But that does not need to be a > problem. =A0The most successful open source hardware (OSH) project I > have seen is the Beagle Board which can only be made in pretty > advanced factories. =A0It uses a Package on Package mounting technique > for the processor memory as the OMAP CPU used is intended for use in > PDAs and cell phone like applications. =A0So clearly, the fact that you > might have to sell some part or even all of the board would not doom > the project as Antti might think. =A0(Not trying to put words in your > mouth Antti, just making a point). > > In fact, I am thinking about an open source GPS receiver project which > would require not only the electronic hardware, but also a mechanical > design be done. =A0Now *that* can be a problem for open source I > think. > > > My point: is placing all of this projects work in an open source > > license to be easily duplicated at a reasonable cost one board under > > $50.00 for someone in need of well behaved electronic signals, maybe > > an engineer, a student, a hobbyist, and the like. Antti, you are so > > preceptive, Yes, I would like to be able to accept notes of > > appreciation for this body of work, because someone finds it helpful. > > Being able to discuss this body of work and let it go out to those who > > would find it useful makes me smile. Open Source Hardware licensing > > just prevents anyone from strangling the work and making it theirs, > > plagiarism. This body of work is not quite original but is not a rip > > off, or a copy of another work. Yes, their are similar projects out > > there and I have asked for help on this project from those similar > > project, but understandably I got go away, I did. > > I have spent my resource on this project and I need more to continue > > on or even try something different. > > Have you defined your goals for this project? =A0If you are going to > succeed, you need to know what you are trying to do, *clearly*. > Others can give feedback on the goals and you can modify them to > include as many others as possible. =A0Then you will get as much support > as possible. > > Rick Rick, beagle is: 1) backed up by TI 2) uses (used) newest components Cy's design: 1) uses OBSOLETED and NFND components see the difference? Cy: doing something different is an option And as before i am failing to see what you expect to find? I can only sayd that no "open source" developer will be ordering and assembling those boards for personal use and no company is interested to produce them either so if somebody makes the boards its only you, and then you have boards with 2 generation too old FPGA that nobody is interested in, and that you can not sell even for break even AnttiArticle: 143151
On Sep 23, 7:56=A0pm, rickman <gnu...@gmail.com> wrote: > I was looking up the shift operator in VHDL since I seldom use it and > saw that there is both a shift left logical and a shift left > arithmetic. =A0The logic shift left shifts in zeros and the arithmetic > shift left shifts in the value of the lsb. > > I remember from school how a shift right can be logical or arithmetic > in order to implement signed and unsigned arithmetic. =A0But when > shifting left, I have always used a single shift operator, the logical > shift. > > If an arithmetic left shift is used, it gives a valid result for some > values, assuming that the "valid" result is the same as multiplying by > 2**n. =A0But the arithmetic left shift does not fit that model for other > values. =A0On the other hand, the logical left shift *always* returns a > value that is the 2**n multiple of the input value, assuming there are > no range issues such as overflowing into the sign bit. > > So I don't understand the utility of the arithmetic left shift > operator and I especially don't see the reason for calling it > "arithmetic". =A0Can anyone shed some light on this? > > Rick how is this related to FPGA? try vhdl newsgroup? AnttiArticle: 143152
I just read the app note xapp224. This is exactly what i want to do, but unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. I am working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted by 90 degree. I am planning to cascade two DCM. The first DCM gives me CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 degree and fed as clk input then it will give me CLK45, CLK115, CLK225, CLK315. Is there any better way to do this? How precisely can I shift a clock by 45 degree? Will there any clk skew issue at 133 Mhz? Thanks >On Sep 16, 7:59=A0pm, kevin93 <ke...@whitedigs.com> wrote: >> On Sep 15, 10:20=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: >> >> >> >> > Thanks to all of you for useful feedback. >> >> > My clock freq is 133 MHz. Based on your inputs and my understandig from >> > reading "Spartan 3 FPGA Guide" this is what I plan to do. >> >> > clk_i (main clock) connect it to one DCM input clock. >> > 4 phased shifted output from the DCM will give me, clk90, clk180, clk >> > 270. >> >> > clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect= > it >> > to another DCM input clock. >> >> > 4 phased shifted output from the DCM will give me, clk45, clk135, clk22= >5, >> > clk315. >> >> > Am I in the right path? Each clock line drives only two FFs, is 133 MHz >> > okay? >> >> > How can I create "clk_i_inv_delayed" ? >> >> > Best regards, >> > Qamrul >> >> > >Qamrul >> >> > >If you don't need super fast clock outputs, that is less than say >> > >12-25 MHz, you can use an internal clock at X8, X16, and a clock >> > >enable structure to generate such outputs. If you take care such the >> > >outputs are "buffered" through an I/O register, running at the X8/16, >> > >then you won't get any significant skew on the phases due to routing. >> >> > >The clock enable can be a preloaded shift register, with wrap, that is >> > >loaded with X"0001" (X16) loaded at reset or other control condition. >> > >One thing that is ice about this way is that clocks can be "stopped" >> > >easily and restarted without any retraining or lock sequences. >> >> > >For higher frequencies using PLL or DLL techniques to achieve the >> > >required outputs is probably better. >> >> > >John Adair >> > >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. >> >> > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: >> > >> Hi All, >> >> > >> I need to provide 8 clock outs shifted by 45 degree, >> >> > >> clk_0 -> 0 degree phase shift >> > >> clk_1 -> 45 degree phase shift >> > >> clk_1 -> 90 degree phase shift >> > >> clk_1 -> 135 degree phase shift >> > >> clk_1 -> 180 degree phase shift >> > >> clk_1 -> 225 degree phase shift >> > >> clk_1 -> 270 degree phase shift >> > >> clk_1 -> 315 degree phase shift >> > >> clk_1 -> 360 degree phase shift >> >> > >> Is it at all possible? >> >> > >> Thanks in advance for your feed back. >> >> > >> Qamrul >> >> > --------------------------------------- =A0 =A0 =A0 =A0 >> > This message was sent using the comp.arch.fpga web interface onhttp://w= >ww.FPGARelated.com >> >> Do you need 8 phases? >> >> Have you read the relevant Xilinx app notes such as xapp224 that use >> this technique, even in the low cost FPGAs? >> >> kevin > >he hasnt > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143153
On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote: >how is this related to FPGA? >try vhdl newsgroup? Well... it is somewhat relevant. And comp.lang.vhdl is being spammed mercilessly right now by some bozo trying to sell fake sneakers. And Rick well knows that many of the usual comp.lang.vhdl suspects also hang out here. So it's not so crazy. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 143154
On Sep 23, 8:51=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote: > >how is this related to FPGA? > >try vhdl newsgroup? > > Well... it is somewhat relevant. > And comp.lang.vhdl is being spammed > mercilessly right now by some bozo trying > to sell fake sneakers. =A0And Rick well knows > that many of the usual comp.lang.vhdl suspects > also hang out here. =A0So it's not so crazy. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. ic comp . arch . embedded is also sneaker victim im not monitoring vhdl so wasnt aware its sneaker infection ok, that valid excuse ;) AnttiArticle: 143155
On Sep 23, 8:30=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > I just read the app note xapp224. This is exactly what i want to do, but > unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. I = am > working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted by > 90 degree. I am planning to cascade two DCM. The first DCM gives me > CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 > degree and fed as clk input then it will give me CLK45, CLK115, CLK225, > CLK315. > Is there any better way to do this? How precisely can I shift a clock by > 45 degree? Will there any clk skew issue at 133 Mhz? > > Thanks YOU CANT 8 phases of 133 mhz clock means 1064 MHz time "resolution" it will NOT work in S3 FPGA YOU Can not "over smart" things, not to that extent i am not saying what you actually want todo cant be done with S3, but you defenetly cant get it working with your 8 phase idea AnttiArticle: 143156
Antti.Lukats@googlemail.com <antti.lukats@googlemail.com> wrote: < On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote: <> I was looking up the shift operator in VHDL since I seldom use it and <> saw that there is both a shift left logical and a shift left <> arithmetic. ?The logic shift left shifts in zeros and the arithmetic <> shift left shifts in the value of the lsb. <> I remember from school how a shift right can be logical or arithmetic <> in order to implement signed and unsigned arithmetic. ?But when <> shifting left, I have always used a single shift operator, the logical <> shift. (snip) <> So I don't understand the utility of the arithmetic left shift <> operator and I especially don't see the reason for calling it <> "arithmetic". ?Can anyone shed some light on this? In software (languages such as C and Fortran) the difference is in the possible consequence of overflow. Computing hardware does support arithmetic left shift: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116 such that the sign bit does not participate in the shift. < how is this related to FPGA? try vhdl newsgroup? For questions related to synthesis, it doesn't seem so far off to post here. For questions only related to simulation, or language syntax questions, it does seem a little off topic. In this case, I suppose it could be used in synthesis, but it isn't so obvious. -- glenArticle: 143157
Antti, You have it all figured dont ya, Nobody, nothing, no company, no interest. Well, seems as if two others have joined in to express some interest. I agree the mating components, 4 connectors, used on the board for stacking the boards are expensive and therefore need to rethink that. There is an SPI flash in the lower right hand of that picture, which I have used to boot load, yes it was programmed with the Xilinx platform Cable USB II and the impact software. I do believe that the hardware is in place to allow a file to be copied into the flash through the USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and running. I am not all together convinced that this can not become a multiboot system, however it is not spoken about in either XAPP951 or XAPP974. Rick, I did not see the problem for your electrical and mechanical designs of the GPS receiver. When the design is done and all is working clients merely order the mechanical component order the electrical component put it together. If there is need for something different all design file are available for the next design, who ever it may be. Clear goals: Yes, agreed. I have met my initial goals: an operable usb powered and programmable fpga with a couple of addition for usability. Now what? Well as antti has so strongly points out no one wants this thing. Well, i have it, I am in need of it, and I do not want to purchase any of antti products, or anyone elses, for any of my contracted work, not that I have alot. I need some help in putting together something a bit more robust and engineering friendly, friendly to me and future work. I do not want to put something together that does everything just gets far enough along that I can work on the customers specifics. I can not be the only one in this situation, therefore I want to work with a group of like minded engineers to establish a good off the shelf component for future use. Now, I'm not selfish I would like to share and make all of it available, I like what happened to audrino it is a nice little 16 bit processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit processors or whatever the hardware can be reconfigured to be. I need it and want it. This board is only to say that I have the ability is anyone else interested, well, the internet is good enough to house a loose collection of engineers for a small project. Nico, What yet needs to be done, that's easy just look over Antti posts and wherever he says no, not, cant, doesnt, neight just solve those problems. Just because antti says no, not, cant, doesnt, neight does not make it so. Anyways- thanks for taking time to post and give me some ideas. Cy DrollingerArticle: 143158
On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote: > Antti, > > You have it all figured dont ya, Nobody, nothing, no company, no > interest. Well, seems as if two others have joined in to express some > interest. > > =A0I agree the mating components, 4 connectors, used on the board for > stacking the boards are expensive and therefore need to rethink > that. > > There is an SPI flash in the lower right hand of that picture, which I > have used to boot load, yes it was programmed with the Xilinx platform > Cable USB II and the impact software. I do believe that the hardware > is in place to allow a file to be copied into the flash through the > USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and > running. I am not all together convinced that this can not become a > multiboot system, however it is not spoken about in either XAPP951 or > XAPP974. > > Rick, > > I did not see the problem for your electrical and mechanical designs > of the GPS receiver. When the design is done and all is working > clients merely order the mechanical component order the electrical > component put it together. If there is need for something different > all design file are available for the next design, who ever it may be. > Clear goals: Yes, agreed. I have met my initial goals: an operable usb > powered and programmable fpga with a couple of addition for usability. > Now what? Well as antti has so strongly points out no one wants this > thing. Well, i have it, I am in need of it, and I do not want to > purchase any of antti products, or anyone elses, for any of my > contracted work, not that I have alot. I need some help in putting > together something a bit more robust and engineering friendly, > friendly to me and future work. I do not want to put something > together that does everything just gets far enough along that I can > work on the customers specifics. I can not be the only one in this > situation, therefore I want to work with a group of like minded > engineers to establish a good off the shelf component for future use. > Now, I'm not selfish I would like to share and make all of it > available, I like what happened to audrino it is a nice little 16 bit > processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit > processors or whatever the hardware can be reconfigured to be. I need > it and want it. This board is only to say that I have the ability is > anyone else interested, well, the internet is good enough to house a > loose collection of engineers for a small project. > > Nico, > What yet needs to be done, that's easy just look over Antti posts and > wherever he says no, not, cant, doesnt, neight just solve those > problems. Just because antti says no, not, cant, doesnt, neight does > not make it so. > > Anyways- thanks for taking time to post and give me some ideas. > > Cy Drollinger there is no failsafe multiboot in S3E just another reason never use something as old as S3E Antti PS I am not as negative just trying to help you, and yes i have pretty much figured outArticle: 143159
On Sep 23, 10:47=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote: > > > > > Antti, > > > You have it all figured dont ya, Nobody, nothing, no company, no > > interest. Well, seems as if two others have joined in to express some > > interest. > > > =A0I agree the mating components, 4 connectors, used on the board for > > stacking the boards are expensive and therefore need to rethink > > that. > > > There is an SPI flash in the lower right hand of that picture, which I > > have used to boot load, yes it was programmed with the Xilinx platform > > Cable USB II and the impact software. I do believe that the hardware > > is in place to allow a file to be copied into the flash through the > > USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and > > running. I am not all together convinced that this can not become a > > multiboot system, however it is not spoken about in either XAPP951 or > > XAPP974. > > > Rick, > > > I did not see the problem for your electrical and mechanical designs > > of the GPS receiver. When the design is done and all is working > > clients merely order the mechanical component order the electrical > > component put it together. If there is need for something different > > all design file are available for the next design, who ever it may be. > > Clear goals: Yes, agreed. I have met my initial goals: an operable usb > > powered and programmable fpga with a couple of addition for usability. > > Now what? Well as antti has so strongly points out no one wants this > > thing. Well, i have it, I am in need of it, and I do not want to > > purchase any of antti products, or anyone elses, for any of my > > contracted work, not that I have alot. I need some help in putting > > together something a bit more robust and engineering friendly, > > friendly to me and future work. I do not want to put something > > together that does everything just gets far enough along that I can > > work on the customers specifics. I can not be the only one in this > > situation, therefore I want to work with a group of like minded > > engineers to establish a good off the shelf component for future use. > > Now, I'm not selfish I would like to share and make all of it > > available, I like what happened to audrino it is a nice little 16 bit > > processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit > > processors or whatever the hardware can be reconfigured to be. I need > > it and want it. This board is only to say that I have the ability is > > anyone else interested, well, the internet is good enough to house a > > loose collection of engineers for a small project. > > > Nico, > > What yet needs to be done, that's easy just look over Antti posts and > > wherever he says no, not, cant, doesnt, neight just solve those > > problems. Just because antti says no, not, cant, doesnt, neight does > > not make it so. > > > Anyways- thanks for taking time to post and give me some ideas. > > > Cy Drollinger > > there is no failsafe multiboot in S3E > > just another reason never use something as old as S3E > > Antti > PS I am not as negative just trying to help you, > and yes i have pretty much figured out i must correct myself s3e: no failsafe multiboot in SPI flash without external circuitry AnttiArticle: 143160
>On Sep 23, 8:30=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: >> I just read the app note xapp224. This is exactly what i want to do, but >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. I = >am >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted by >> 90 degree. I am planning to cascade two DCM. The first DCM gives me >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 >> degree and fed as clk input then it will give me CLK45, CLK115, CLK225, >> CLK315. >> Is there any better way to do this? How precisely can I shift a clock by >> 45 degree? Will there any clk skew issue at 133 Mhz? >> >> Thanks > >YOU CANT > >8 phases of 133 mhz clock means 1064 MHz time "resolution" >it will NOT work in S3 FPGA > >YOU Can not "over smart" things, not to that extent >i am not saying what you actually want todo cant be done >with S3, but you defenetly cant get it working with your 8 phase idea > >Antti > > it is not clear to me why "resolution" comes here. 2 DCM should provide me with 8 clocks @45 degrees. So there will be 8 clock domains internal to the FPGA. I will drive 8 internal Flops with these clocks. May be I am missing something. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143161
On Sep 23, 10:49=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >On Sep 23, 8:30=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> I just read the app note xapp224. This is exactly what i want to do, > but > >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. > I =3D > >am > >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted > by > >> 90 degree. I am planning to cascade two DCM. The first DCM gives me > >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 > >> degree and fed as clk input then it will give me CLK45, CLK115, > CLK225, > >> CLK315. > >> Is there any better way to do this? How precisely can I shift a clock > by > >> 45 degree? Will there any clk skew issue at 133 Mhz? > > >> Thanks > > >YOU CANT > > >8 phases of 133 mhz clock means 1064 MHz time "resolution" > >it will NOT work in S3 FPGA > > >YOU Can not "over smart" things, not to that extent > >i am not saying what you actually want todo cant be done > >with S3, but you defenetly cant get it working with your 8 phase idea > > >Antti > > it is not clear to me why "resolution" comes here. 2 DCM should provide m= e > with 8 clocks @45 degrees. So there will be 8 clock domains internal to t= he > FPGA. I will drive 8 internal Flops with these clocks. May be I am missin= g > something. =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com yes you are AnttiArticle: 143162
On Sep 23, 10:49=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >On Sep 23, 8:30=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> I just read the app note xapp224. This is exactly what i want to do, > but > >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. > I =3D > >am > >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted > by > >> 90 degree. I am planning to cascade two DCM. The first DCM gives me > >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 > >> degree and fed as clk input then it will give me CLK45, CLK115, > CLK225, > >> CLK315. > >> Is there any better way to do this? How precisely can I shift a clock > by > >> 45 degree? Will there any clk skew issue at 133 Mhz? > > >> Thanks > > >YOU CANT > > >8 phases of 133 mhz clock means 1064 MHz time "resolution" > >it will NOT work in S3 FPGA > > >YOU Can not "over smart" things, not to that extent > >i am not saying what you actually want todo cant be done > >with S3, but you defenetly cant get it working with your 8 phase idea > > >Antti > > it is not clear to me why "resolution" comes here. 2 DCM should provide m= e > with 8 clocks @45 degrees. So there will be 8 clock domains internal to t= he > FPGA. I will drive 8 internal Flops with these clocks. May be I am missin= g > something. =A0 =A0 =A0 =A0 > you CAN TRY but you WILL FAIL but maybe while trying you understand why, so you learn something AnttiArticle: 143163
On Sep 23, 3:08=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Antti.Luk...@googlemail.com <antti.luk...@googlemail.com> wrote: > > < On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote: > <> I was looking up the shift operator in VHDL since I seldom use it and > <> saw that there is both a shift left logical and a shift left > <> arithmetic. ?The logic shift left shifts in zeros and the arithmetic > <> shift left shifts in the value of the lsb. > > <> I remember from school how a shift right can be logical or arithmetic > <> in order to implement signed and unsigned arithmetic. ?But when > <> shifting left, I have always used a single shift operator, the logical > <> shift. > (snip) > > <> So I don't understand the utility of the arithmetic left shift > <> operator and I especially don't see the reason for calling it > <> "arithmetic". ?Can anyone shed some light on this? > > In software (languages such as C and Fortran) the difference is > in the possible consequence of overflow. =A0 > > Computing hardware does support arithmetic left shift: > > http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116 > > such that the sign bit does not participate in the shift. =A0 Yes, but this is not an arithmetic left shift as defined by my original post. "For SLA or SLAG, zeros are supplied to the vacated bit positions on the right" That is what I was taught was the way to perform an arithmetic left shift, to fill the right positions with zero. But this is also the logical left shift operation. I don't understand why a left shift which fills the right most positions with the former lsb would be of value. I suppose it could just exist to fill the space in a chart, but calling it an arithmetic left shift is a misnomer as arithmetic would use the same shift as the logical left shift. To make Antti happy, ignore the use of the abbreviation VHDL in my original post. This is about an arithmetic algorithm as used in an FPGA I am designing. RickArticle: 143164
On Sep 23, 3:56=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 23, 10:49=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > > > > > >On Sep 23, 8:30=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > > >> I just read the app note xapp224. This is exactly what i want to do, > > but > > >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degre= e. > > I =3D > > >am > > >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shift= ed > > by > > >> 90 degree. I am planning to cascade two DCM. The first DCM gives me > > >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 4= 5 > > >> degree and fed as clk input then it will give me CLK45, CLK115, > > CLK225, > > >> CLK315. > > >> Is there any better way to do this? How precisely can I shift a cloc= k > > by > > >> 45 degree? Will there any clk skew issue at 133 Mhz? > > > >> Thanks > > > >YOU CANT > > > >8 phases of 133 mhz clock means 1064 MHz time "resolution" > > >it will NOT work in S3 FPGA > > > >YOU Can not "over smart" things, not to that extent > > >i am not saying what you actually want todo cant be done > > >with S3, but you defenetly cant get it working with your 8 phase idea > > > >Antti > > > it is not clear to me why "resolution" comes here. 2 DCM should provide= me > > with 8 clocks @45 degrees. So there will be 8 clock domains internal to= the > > FPGA. I will drive 8 internal Flops with these clocks. May be I am miss= ing > > something. =A0 =A0 =A0 =A0 > > you CAN TRY > but you WILL FAIL > > but maybe while trying you understand why, so you learn something > > Antti I think you are being rather pessimistic. You don't know what his requirements are for accuracy of the phase shift. If he is working with a fixed frequency, I think he may be able to approximate what he needs in the way he wants to do it. I have no idea how exact his 45 degree shift needs to be, nor do I know how well he will be able to generate the critical 45 degree phase shift to feed the second DCM. But I don't see that it is an automatic failure from the start. I don't recommend that elements in FPGAs be used as delay elements, but I won't say it can't be done. Just look at some of Peter Alfke's app notes where he does exactly that. It all comes down to how accurate the phase shift needs to be. RickArticle: 143165
On Sep 23, 10:06=A0am, gabor <ga...@alacron.com> wrote: > It turns out that even with simple binary encoding, the values > -1 to 2 (or any set of four contiguous integer values) can > always be decoded using only bits 1 and 0 as these are > different for each value. =A0In the case of -1 to 2 they are > 11 00 01 10, and so even though bit 2 also changes it is > not necessary to use bit 2 for decoding IF the optimising > agent is smart enough to detect that bit 2 can be described > as a function of bits 1 and 0 and is therefore redundant. You know that, and I know that, but I have yet to see a synthesis tool that knows that and takes advantage of it. Make an enumerated type with values minus_one, zero, one and two, and it might, but only because it has no clue that "one" in english is 1. AndyArticle: 143166
On Sep 23, 10:30=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > I just read the app note xapp224. This is exactly what i want to do, but > unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degree. I = am > working with a Spartan 3 FPGA board where the DCM has 4 clocks shifted by > 90 degree. I am planning to cascade two DCM. The first DCM gives me > CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 45 > degree and fed as clk input then it will give me CLK45, CLK115, CLK225, > CLK315. > Is there any better way to do this? How precisely can I shift a clock by > 45 degree? Will there any clk skew issue at 133 Mhz? > > Thanks ... I don't see why that wouldn't work but as others have stated you are reaching the limits of the S3 in terms of rise times. Why do you think you need 8 phases rather than 4? kevinArticle: 143167
Andy <jonesandy@comcast.net> wrote: (snip) < You know that, and I know that, but I have yet to see a synthesis tool < that knows that and takes advantage of it. It is probably right to say that the synthesis tool doesn't know that. But following synthesis on most systems is a redundant logic removal pass which will likely figure out many cases. More often, non-redundant logic is removed due to errors in the input. Signals may be constant for testing purposes, or otherwise accidentally, and be removed. With a little luck, the whole design is removed! < Make an enumerated type with values minus_one, zero, one and two, and < it might, but only because it has no clue that "one" in english is 1. If you assign it to a two bit bus it will know. (I think in verilog, not VHDL, but I don't think that matters for this question.) -- glenArticle: 143168
rickman wrote: > That is what I was taught was the way to perform an arithmetic left > shift, to fill the right positions with zero. But this is also the > logical left shift operation. I don't understand why a left shift > which fills the right most positions with the former lsb would be of > value. I suppose it could just exist to fill the space in a chart, > but calling it an arithmetic left shift is a misnomer as arithmetic > would use the same shift as the logical left shift. But only because you suppose that the MSB is on the left side and the LSB on the right side.Article: 143169
> On Sep 23, 7:56 pm, rickman <gnu...@gmail.com> wrote:
>> I was looking up the shift operator in VHDL since I seldom use it and
>> saw that there is both a shift left logical and a shift left
>> arithmetic. The logic shift left shifts in zeros and the arithmetic
>> shift left shifts in the value of the lsb.
sla shifts left and copies the right bit.
Use of sla and sll on std_logic_vector is depreciated since
numeric_standard.shift_left automatically does the
"right thing" with the edge bits for signed or unsigned types.
Antti.Lukats@googlemail.com wrote:
> how is this related to FPGA?
VHDL is a popular design entry language for FPGAs.
Up until today, short verilog and vhdl questions
have been tolerated in comp.arch.fpga.
-- Mike Treseler
Article: 143170On Sep 23, 8:45=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Sep 23, 4:38=A0am, "nic_o_...@msn.com" <nic_o_...@msn.com> wrote: > > > > > On Sep 22, 8:33=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > > Nicolas Matringe wrote: > > > > I copied the working code at the end of this message. If I define > > > > variable v_bcnt as unsigned(5 downto 0) then the design stops worki= ng. > > > > I haven't dug into the problem but SPI communication doesn't work > > > > anymore. > > > > consider using a natural range instead of unsigned. > > > Synthesis won't waste any bits if you declare the range. > > > I will give this a try. > > However I have another problem with the same code and variable v_cntr > > (type natural). If I change its range (and change the constants > > assigned to it accordingly) the design also stops working > > > Nicolas > > Simulation and debug will likely get you to the root cause > faster...'specially since the only description you give of the > unexpected behaviour is "the design also stops working". > > KJ I agree with doing simulations. I wasn't sure if "..stops working.." meant on real hardware or not. In your code where you have " if rst =3D '1' then -- asynchronous reset (active high)" what happens when rst goes back to 0 (inactive)? It would be best if you used a 2-stage synchronizer for rst, to make a SYNCHRONIZED version of rst so that going from 1 (active) to non-zero (inactive) is synchronized to your clock. Odd things can happen if all of the FFs are not released from reset on the same clock edge. This may or may not affect the problem you've described. But if you use it correctly, that's one less gremlin to track down. BTW, this isn't my invention, I first saw it in a Xilinx publication at least 5 years ago. -Dave PollumArticle: 143171
>On Sep 23, 3:56=A0pm, "Antti.Luk...@googlemail.com" ><antti.luk...@googlemail.com> wrote: >> On Sep 23, 10:49=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: >> >> >> >> > >On Sep 23, 8:30=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: >> > >> I just read the app note xapp224. This is exactly what i want to do, >> > but >> > >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 degre= >e. >> > I =3D >> > >am >> > >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shift= >ed >> > by >> > >> 90 degree. I am planning to cascade two DCM. The first DCM gives me >> > >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by 4= >5 >> > >> degree and fed as clk input then it will give me CLK45, CLK115, >> > CLK225, >> > >> CLK315. >> > >> Is there any better way to do this? How precisely can I shift a cloc= >k >> > by >> > >> 45 degree? Will there any clk skew issue at 133 Mhz? >> >> > >> Thanks >> >> > >YOU CANT >> >> > >8 phases of 133 mhz clock means 1064 MHz time "resolution" >> > >it will NOT work in S3 FPGA >> >> > >YOU Can not "over smart" things, not to that extent >> > >i am not saying what you actually want todo cant be done >> > >with S3, but you defenetly cant get it working with your 8 phase idea >> >> > >Antti >> >> > it is not clear to me why "resolution" comes here. 2 DCM should provide= > me >> > with 8 clocks @45 degrees. So there will be 8 clock domains internal to= > the >> > FPGA. I will drive 8 internal Flops with these clocks. May be I am miss= >ing >> > something. =A0 =A0 =A0 =A0 >> >> you CAN TRY >> but you WILL FAIL >> >> but maybe while trying you understand why, so you learn something >> >> Antti > >I think you are being rather pessimistic. You don't know what his >requirements are for accuracy of the phase shift. If he is working >with a fixed frequency, I think he may be able to approximate what he >needs in the way he wants to do it. I have no idea how exact his 45 >degree shift needs to be, nor do I know how well he will be able to >generate the critical 45 degree phase shift to feed the second DCM. >But I don't see that it is an automatic failure from the start. > >I don't recommend that elements in FPGAs be used as delay elements, >but I won't say it can't be done. Just look at some of Peter Alfke's >app notes where he does exactly that. It all comes down to how >accurate the phase shift needs to be. > >Rick I do see that the success of this approach lies in the relative skew of first DCM clocks and second DCM clocks. If I had pick hand pick buffer element to acheive 45 degree Phase shift for the clk input to DCM 2, can I get post layout timing report of the path? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143172
On Sep 24, 11:28=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > I do see that the success of this approach lies in the relative skew of > first DCM clocks and second DCM clocks. If I had pick hand pick buffer > element to acheive 45 degree Phase shift for the clk input to DCM 2, can = I > get post layout timing report of the path? =A0 =A0 =A0 =A0 Sure, you can get a value at one temperature, on a virtual silicon case :) If you want this to work in the real world, you need to decide what errors you can tolerate on that 45'. Solutions could include a longer delay block, that finds the 90' length, and then taps half of that - ie a self-cal case. You then need to decide when to cal.... Or, external RC/LC phase shifts can be used, if your freq is nailed down. Using both edges, can relax the fMAX to something that might just be doable or move to a FPGA that does have such delay elements in the fabric. -jgArticle: 143173
On Sep 23, 11:25=A0pm, rickman <gnu...@gmail.com> wrote: > On Sep 23, 3:56=A0pm, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 23, 10:49=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > > > > >On Sep 23, 8:30=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > > > >> I just read the app note xapp224. This is exactly what i want to d= o, > > > but > > > >> unlike the appnotes clk_90, I will need 8 clocks shifted by 45 deg= ree. > > > I =3D > > > >am > > > >> working with a Spartan 3 FPGA board where the DCM has 4 clocks shi= fted > > > by > > > >> 90 degree. I am planning to cascade two DCM. The first DCM gives m= e > > > >> CLK0,CLK90, CLK180,CLK270. For the 2nd DCM, if CLK0 is buffered by= 45 > > > >> degree and fed as clk input then it will give me CLK45, CLK115, > > > CLK225, > > > >> CLK315. > > > >> Is there any better way to do this? How precisely can I shift a cl= ock > > > by > > > >> 45 degree? Will there any clk skew issue at 133 Mhz? > > > > >> Thanks > > > > >YOU CANT > > > > >8 phases of 133 mhz clock means 1064 MHz time "resolution" > > > >it will NOT work in S3 FPGA > > > > >YOU Can not "over smart" things, not to that extent > > > >i am not saying what you actually want todo cant be done > > > >with S3, but you defenetly cant get it working with your 8 phase ide= a > > > > >Antti > > > > it is not clear to me why "resolution" comes here. 2 DCM should provi= de me > > > with 8 clocks @45 degrees. So there will be 8 clock domains internal = to the > > > FPGA. I will drive 8 internal Flops with these clocks. May be I am mi= ssing > > > something. =A0 =A0 =A0 =A0 > > > you CAN TRY > > but you WILL FAIL > > > but maybe while trying you understand why, so you learn something > > > Antti > > I think you are being rather pessimistic. =A0You don't know what his > requirements are for accuracy of the phase shift. =A0If he is working > with a fixed frequency, I think he may be able to approximate what he > needs in the way he wants to do it. =A0I have no idea how exact his 45 > degree shift needs to be, nor do I know how well he will be able to > generate the critical 45 degree phase shift to feed the second DCM. > But I don't see that it is an automatic failure from the start. > > I don't recommend that elements in FPGAs be used as delay elements, > but I won't say it can't be done. =A0Just look at some of Peter Alfke's > app notes where he does exactly that. =A0It all comes down to how > accurate the phase shift needs to be. > > Rick Rick, not pessimistic, realistic! I did not say what he wants (initial task) is not doable in S3, but an attempt to do it in S3 using 8 phase clock will fail. the reason is "routing delay" no matter HOW GOOD HE IS with Xilinx "DIRT" (directed routing) constraints, there is no way he manages to get the routing delay for ALL data (8 routes minimum) AND clock (8 routes for of ALL the 8 phases) adjusted to the required precision. i bet the OP hasnt even ever used DIRT there is no chance without, and VERY VERY small with the use of DIRT, I said none. Antti PS I do not think even Ray would go this path with 8 clock and DIRT in S3, I defenetly would not.Article: 143174
On Sep 24, 12:32=A0am, Dave Pollum <vze24...@verizon.net> wrote: > On Sep 23, 8:45=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > On Sep 23, 4:38=A0am, "nic_o_...@msn.com" <nic_o_...@msn.com> wrote: > > > > On Sep 22, 8:33=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > > > Nicolas Matringe wrote: > > > > > I copied the working code at the end of this message. If I define > > > > > variable v_bcnt as unsigned(5 downto 0) then the design stops wor= king. > > > > > I haven't dug into the problem but SPI communication doesn't work > > > > > anymore. > > > > > consider using a natural range instead of unsigned. > > > > Synthesis won't waste any bits if you declare the range. > > > > I will give this a try. > > > However I have another problem with the same code and variable v_cntr > > > (type natural). If I change its range (and change the constants > > > assigned to it accordingly) the design also stops working > > > > Nicolas > > > Simulation and debug will likely get you to the root cause > > faster...'specially since the only description you give of the > > unexpected behaviour is "the design also stops working". > > > KJ > > I agree with doing simulations. =A0I wasn't sure if "..stops working.." > meant on real hardware or not. > In your code where you have " if rst =3D '1' then =A0-- asynchronous rese= t > (active high)" what happens when rst goes back to 0 (inactive)? =A0It > would be best if you used a 2-stage synchronizer for rst, to make a > SYNCHRONIZED version of rst so that going from 1 (active) to non-zero > (inactive) is synchronized to your clock. =A0Odd things can happen if > all of the FFs are not released from reset on the same clock edge. > This may or may not affect the problem you've described. =A0But if you > use it correctly, that's one less gremlin to track down. =A0BTW, this > isn't my invention, I first saw it in a Xilinx publication at least 5 > years ago. > -Dave Pollum I always use an asynchronous reset description in my processes but the actual reset signal is synchronized in another block. I only posted the offending entity, the design is larer than this single file. I am no beginner and I did simulate my design before synthesizing it. Simulation runs absolutely fine. I have made further investigation, the SPI master generates the correct number of clock cycles but only the 12 first bits are transmitted, MOSI then goes high. Nicolas
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