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On Wed, 22 Jul 2009 18:19:26 -0700 (PDT), KJ <kkjennings@sbcglobal.net> wrote: >On Jul 22, 5:45 pm, Mike Harrison <m...@whitewing.co.uk> wrote: ><snip> > >> >Then, OK the #ifdef lets you make this edit quicker. But that means >> >either that you also have to edit the type definition to remove the >> >'Blah' state or leave it in and let the 'when others' pick it up and >> >hope that this state bit synthesizes away so it doesn't cost you. The >> >other way to code this would be... >> >> A few extra unused states probably wouldn't be a big deal compared to the logic generated to deal >> with them. >> > >I disagree that extra states are not a big deal, but not because of >logic resource concerns but due to debug methodology. Typical >hardware design flows rely (or should rely) on simulation for logic >validation. You setup a testbench (more VHDL that stimulates all the >inputs and check the outputs) and run a test case (or cases) that >exercises the logic that is under test. <dons flameproof underpants> I'm not doing any simulation. I tend to approach things in a bottom-up way, starting with the simplest functionality and gradually building things up step by step, testing on real hardware as I go, and learning the tools, language and architecture as I go. I'm much more comfortable with a soldering iron and scope probe in hand than a PC screen trying to define simulation inputs from umpteen possible sources. The speeds and complexities involved are so far below the device's capabilities that I also haven't yet set any timing constraints, although these will happen once I get this urgent prototype build out of the way. I'm sure many people here will throw up their hands in horror but it's just the way I like to work and I'm too old to change now! >> >> or servicing peripheral devices which are not present in some variants >> >> Obviously 'others' will catch things that are conditionally excluded and take it to the 'idle' >> >> state. >> >> >If the peripherals are not there in some variants, then simply not >> >connecting any of the output signals from the entity that produces the >> >unneeded signals to any of the top level entity outputs is >> >sufficient. The synthesis tool will not produce any logic to >> >implement anything that doesn't affect an output pin. These inputs may be pins connected to a devicewhich isn't always populated on the PCB. >> there may be input-only peripherals, and you may want to make sure no logic is generated as that >> variant may have alternative functionality that needs the space. > >Not sure what you mean by an 'input-only' peripheral, e.g. a comms interface - let's say an async receiver, which can receive commands to influence system behaviour. >Once you've done so (change some build setting), how do you keep track >of how a given file was built? You can't exactly peruse the binary >output file to check to see how that setting was set. Now you've >created a configuration management issue, the only way to know how a >particular xyz.bin file was built is to rebuild it. Not a big problem. I'm the only one who will ever build it. If course having build tools that can create different target filenames based on build options would be good but I've not even found any software IDEs that will do this in a useful way, although some have a means to create different builds with different object directories.Article: 142051
On Jul 23, 1:09=A0pm, dowlers <eoindowl...@gmail.com> wrote: > > Do you want to hide the fact that it's an FPGA? We epoxy pin-fin > > heatsinks on top. > > >ftp://jjlarkin.lmi.net/DSC01786.JPG > > > John > > Not really hide but advertise company name. It is a non volotile FPGA - > XP2. > I have found a company - Action Circuits. > > Eoin Lattice make custom marking too, if you ask, but min qty applies AnttiArticle: 142052
On Jul 23, 3:55=A0am, sheri <saras_rajg...@yahoo.co.in> wrote: > On Jul 23, 12:02=A0pm, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 23, 9:31=A0am, saras <saras_rajg...@yahoo.co.in> wrote: > > > > hi all, I am using SPARTAN - 3AN FPGA . While progaramming the FPGA , > > > it erases , programs and verifiys successfully but at the end, I get > > > PROGRAMMING FAILED status..The reason it says is DONE pin did'nt go > > > high.. > > > But if I erase the on -board DSP and then program FPGA, I get > > > PROGRAMMING SUCCESSFULL. I am not understaning this. DONE signal is > > > supposed to be genearated by FPGA..Why DSP has to be erased? All the > > > required signals for programming like INIT_B , PROG is generated by > > > another on -board =A0microcontroller. Please provide some suggestions= . > > > erasable DSP? > > > what are you talking about ;)? > >>>>>>> >> It is flash based DSP chip, which can be erased using the DSP = Jtag debugger. > > what are you programming? the onchip SPI flash? > > or loading config via slave serial using onboard MCU? > >>> >>I'm flashing the onchip SPI flash for now, but will be done by MCU = in future.For now it is in dvevelopment stage and I'm using Xilix Jtag cabl= e to program the onchip SPI flash. > > what is the DSP doing?? > > >>> I donno much about its functinality but I'm using its clock... > > a real mystery (to anyone except you) > > > Antti > > I typically don't mix different vendor products in the same JTAG chain. It's possible that the DSP JTAG debug interface somehow affects FPGA programming. It's also possible that some connections between the DSP chip and the FPGA are causing the problem. If the latter is true you may try setting Impact to "Use HIGHZ Instead of BYPASS" in the configuration preferences. HTH, GaborArticle: 142053
On Jul 21, 10:13=A0am, "Fredxx" <fre...@spam.com> wrote: > Andy wrote: > > On Jul 21, 4:18 am, "Fredxx" <fre...@spam.com> wrote: > >> Actually running Chipscope at a higher multiple of the clock is very > >> good at seeing timing errors. Ideal if you have a spare DCM! > > > Except inserting chipscope alters the timing, so it may help you find > > timing errors that were not there to begin with, or mask timing errors > > that are there without it. > > > Andy > > Maybe, but I would hope that the timing criteria would have been tied dow= n > so waveforms didn't change on every compilation. I'm not sure of your distinction between "waveforms" and "intermediate" timing, but I think specifying timing relationships to the tools is one significant hole in verifying the correctness of an FPGA design. We have lots of software to help us figure out if our code is logically correct or to show us where a problem might be, but there is little in the way of software to verify the adequacy or correctness of timing constraints which are the only tool to specify timing. It is expected that every engineer be infallible when specifying their timing constraints. > I was thinking more of interface issues, rather than "intermediate > failiures" where I assume there is some internal timing failure within th= e > device. =A0It should be possible to overcome or identify these sorts of > failures by entering timing information in the UCF file, or by following > good practice if crossing clock domains. Yes, it "should" be possible and of course, it is "possible". But how do you even figure out if a given path is constrained or not and if it is constrained by the constraint you think it is covered by? RickArticle: 142054
On Jul 22, 6:29=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > On Jul 21, 7:13=A0pm, "Fredxx" <fre...@spam.com> wrote: > > > > > Andy wrote: > > > On Jul 21, 4:18 am, "Fredxx" <fre...@spam.com> wrote: > > >> Actually running Chipscope at a higher multiple of the clock is very > > >> good at seeing timing errors. Ideal if you have a spare DCM! > > > > Except inserting chipscope alters the timing, so it may help you find > > > timing errors that were not there to begin with, or mask timing error= s > > > that are there without it. > > > > Andy > > > Maybe, but I would hope that the timing criteria would have been tied d= own > > so waveforms didn't change on every compilation. > > > I was thinking more of interface issues, rather than "intermediate > > failiures" where I assume there is some internal timing failure within = the > > device. =A0It should be possible to overcome or identify these sorts of > > failures by entering timing information in the UCF file, or by followin= g > > good practice if crossing clock domains. > > Thanks alot all for helping me out with your valuable ideas and > experiences. Actually, I dont see a timing problem there. Had it been > a timing problem, it should have given me the same problem on the > first FPGA board which is identical. As I said earlier, I have > identical Spartan3AN boards. WHOA!!! The boards may have been made identically, but the silicon has three main sources of timing variation, temperature, voltage and process. I will assume that the two boards would be running at the same temperature. But unless you are running them from external power supplies, you can't assume the power supply voltages are identical. Then there is process... I can assure you that you can find a wide variation between any two chips that were not on the same wafer and in fact, close together on the same wafer. I had a project once where we had a bad design tool that was underestimating the timing delay in some net, likely a wide fan out signal in the part. We could produce a design that would run fine when we kept the part cool, but would crap out if we let it get hot (or heated it). This would change from compile to compile and of course it varied between different boards and chips. Our MO ended up being to run overnight, in parallel many compiles with different seeds to produce different routes. We would then test them the next morning on a board with a temperature controlled heater on the chip. The board had been chosen as the worst we had in the lab in terms of sensitivity to temperature. So when we found a design that would run on that board at a temperature some 20 degrees above rated temps, we shipped it! This was going in some pricey test gear, but it was an upgrade to equipment in the field, so we didn't have the choice of changing the part... at least not without a lot of costs. > The same code works on one board but > fails on the other in a strange manner which I have explained in my > opening post. It seems something has really gone wrong with the FPGA > fabric as Antii said. I was more interested to find out is there > really something wrong with the FPGA and if so, how to authenticate > it! That something is wrong with the FPGA other than possibly damaged I/O pins is very, very, VERY remote. On the other hand, this sounds *exactly* like a timing problem. The fact that it happens on one board and not the other is actually a clue pointing to that conclusion. Try a test. Construct a ring oscillator using some number of LUTs in a ring each configured as an inverter. Route one output to an output pin and measure the frequency with a scope or freq counter. See which part is faster and how much they differ. I bet the failing part is noticeably slower. RickArticle: 142055
>> Mike Treseler wrote:
>>> I find that leaving in live, but unused
>>> or obsolescent code like this
>>> is sometimes more informative
>>> to my future self, than is tidying up.
> On Jul 22, 8:43 pm, Mark McDougall <ma...@vl.com.au> wrote:
>> So I'm not the only one!!! Good to know! ;)
KJ wrote:
> No you're not alone, at least three of us now...but then you also said
> earlier that you leave in some "obsolete/experimental/irrelevant code
> without it passing elaboration"...that's a bit different. You're not
> alone there either, but if I keep something like that around it's
> commented out. I'd much rather it be live code that really does
> elaborate and sim.
I agree. If some of my "switched off" code does not elaborate,
that means I have changed or eliminated the target of some identifier
that previously make the code usable.
I would either fix up the option or take it all out.
The advantage of leaving the dependency in,
is, that I'll get a warning if I unintentional
rule out future use of the option. Even if the option is
never again used, it is an effective way to document
ambiguity by letting the code talk about itself.
-- Mike Treseler
Article: 142056On Jul 23, 8:02=A0pm, rickman <gnu...@gmail.com> wrote: > On Jul 22, 6:29=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > > > > > > > On Jul 21, 7:13=A0pm, "Fredxx" <fre...@spam.com> wrote: > > > > Andy wrote: > > > > On Jul 21, 4:18 am, "Fredxx" <fre...@spam.com> wrote: > > > >> Actually running Chipscope at a higher multiple of the clock is ve= ry > > > >> good at seeing timing errors. Ideal if you have a spare DCM! > > > > > Except inserting chipscope alters the timing, so it may help you fi= nd > > > > timing errors that were not there to begin with, or mask timing err= ors > > > > that are there without it. > > > > > Andy > > > > Maybe, but I would hope that the timing criteria would have been tied= down > > > so waveforms didn't change on every compilation. > > > > I was thinking more of interface issues, rather than "intermediate > > > failiures" where I assume there is some internal timing failure withi= n the > > > device. =A0It should be possible to overcome or identify these sorts = of > > > failures by entering timing information in the UCF file, or by follow= ing > > > good practice if crossing clock domains. > > > Thanks alot all for helping me out with your valuable ideas and > > experiences. Actually, I dont see a timing problem there. Had it been > > a timing problem, it should have given me the same problem on the > > first FPGA board which is identical. As I said earlier, I have > > identical Spartan3AN boards. > > WHOA!!! =A0The boards may have been made identically, but the silicon > has three main sources of timing variation, temperature, voltage and > process. =A0I will assume that the two boards would be running at the > same temperature. =A0But unless you are running them from external power > supplies, you can't assume the power supply voltages are identical. > Then there is process... I can assure you that you can find a wide > variation between any two chips that were not on the same wafer and in > fact, close together on the same wafer. > > I had a project once where we had a bad design tool that was > underestimating the timing delay in some net, likely a wide fan out > signal in the part. =A0We could produce a design that would run fine > when we kept the part cool, but would crap out if we let it get hot > (or heated it). =A0This would change from compile to compile and of > course it varied between different boards and chips. =A0Our MO ended up > being to run overnight, in parallel many compiles with different seeds > to produce different routes. =A0We would then test them the next morning > on a board with a temperature controlled heater on the chip. =A0The > board had been chosen as the worst we had in the lab in terms of > sensitivity to temperature. =A0So when we found a design that would run > on that board at a temperature some 20 degrees above rated temps, we > shipped it! =A0This was going in some pricey test gear, but it was an > upgrade to equipment in the field, so we didn't have the choice of > changing the part... at least not without a lot of costs. > > > The same code works on one board but > > fails on the other in a strange manner which I have explained in my > > opening post. It seems something has really gone wrong with the FPGA > > fabric as Antii said. I was more interested to find out is there > > really something wrong with the FPGA and if so, how to authenticate > > it! > > That something is wrong with the FPGA other than possibly damaged I/O > pins is very, very, VERY remote. =A0On the other hand, this sounds > *exactly* like a timing problem. =A0The fact that it happens on one > board and not the other is actually a clue pointing to that > conclusion. > > Try a test. =A0Construct a ring oscillator using some number of LUTs in > a ring each configured as an inverter. =A0Route one output to an output > pin and measure the frequency with a scope or freq counter. =A0See which > part is faster and how much they differ. =A0I bet the failing part is > noticeably slower. > > Rick- Hide quoted text - > > - Show quoted text - hm, I assumed the OP already tested and excluded most causes if the signals DID come to into the FPGA (he did see with CS) but did not get latched? hm i would assume that one path fail but not all 16, ok that also possible but then the latch would have latched 0's or random, but he got no update (but i guess he verified the clock and strobe/enables?) hm, guess we are all guessing ;) sure the faulty FPGA is very very remote possibility, but it can not be fully exluded, i did spend lots of troubleshooting when i did see the faulty fpga, but at the end i rewrote special code that worked in it just some type of primitives did not work, i was testing with something simple like counter, after special arrangement i got the counter to work also in faulty fpga, but i had to hand-code it fully AnttiArticle: 142057
On Jul 9, 12:47=A0pm, Dirk Bell <bellda2...@cox.net> wrote:
> On Jul 8, 6:44=A0pm, vizziee <vizz...@gmail.com> wrote:
>
>
>
> > > Check your equations. =A0I get
>
> > > ( ( (22-1)/2 )/20 + ( (22-1)/2 )/10 + ( (1010-1)/2 )/5 ) =3D 102.4750
> > > which is consistant with what you are actually getting, not what you
> > > are calculating.
>
> > > Also note that the filters you are identifying as half-band filters
> > > are not actually half-band filters. =A0Half-band filters have the
> > > property that almost half of the coefficients are zero, saving
> > > calculations, which may be useful to you. But, among other properties=
,
> > > the lengths of halfband filters are constrained to {3, 7, 11, 15, 19,
> > > 23, 27, ..., previous+4, ...}, so a filter of length 22 isn't a half-
> > > band filter.
>
> > > Dirk Bell
>
> > Thanks Dirk. I checked the Halfband filters that I generated in
> > MATLAB. It says it has Direct Form Polyphase Filter structure. The
> > coefficients were generated by specifying 'halfband' option to
> > fdesign.decimator function. The number of generated coefficients for
> > this half-band decimator is actually 21 and I padded a zero to make it
> > 22 for a 2-path polyphase implementation.
>
> > I did a reading for Half-band filters and what you say about the
> > HalfBand FIR filter coefficients is absolutely true: the number of
> > coefficients should be 3+4n for a non-negative integer n. However I
> > couldn't reconcile the MATLAB halfband filter generated above with
> > this definition. Are halfband decimators different than the Nyquist
> > half-band filters? Also the way you calculated the delay of half-band
> > filters appears very much true. However assuming this is the polyphase
> > implementation of half-band decimators, shouldn't delay be calculated
> > like a standard polyphase filter delay formula: ((No_of_taps-1)/2)/
> > Decimation_Factor?
>
> > Thanks again for your insightful replies earlier. I could drastically
> > reduce the no of taps in my current design while also bettering the
> > response. Though the questions as above still linger in my mind.
>
> > Regards,
>
> > vizziee.
>
> Vizziee,
>
> Would you post the coefficients (or preferably all MATLAB inputs and
> resulting output) from your halfband design.
>
> BTW a halfband filter could have a length 21 if it is really a length
> 19 filter with a zero added to each end, but that would be a waste of
> computation if you used the zero coefficients.
>
> Dirk Bell
> DSP Consultant
Thanks Dirk. After a little bit of reading and experimenting, it
appears to me that the MATLAB coefficients so generated for a Halfband
filter were because of the fact that they were implemented as
polyphase structure. The coefficients and the command use dto generate
them are as follows:
dhb =3D fdesign.decimator(2, 'halfband', 'N,AST', 20, 80, 200e6);
hb =3D design(dhb);
hb.Numerator =3D
0 0.0015 0 -0.0083 0 0.0283 0
-0.0801 0 0.3087 0.5000 0.3087 0
-0.0801 0 0.0283 0 -0.0083 0
0.0015 0
Regards,
vizziee.
Article: 142058I just got myself a fpga development board (Altera DE1[1]) to play with. The free development tools (Quartus II web edition) runs only under windows. The subscription edition of Quartus II is priced well beyond my reach (oh, Altera, why no free edition for Linux?). I prefer to run FreeBSD[2] on my workstations, or Linux[2] if I can't run FreeBSD. Are there alternative development tools for Altera (DE1) that runs under FreeBSD? I anyone here running their fpga development tools on FreeBSD? I tried googling, but didm't find anything interesting. References: 1) http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=83 2) http://www.freebsd.org/ 3) http://xubuntu.org/ -- Torfinn Ingolfsen, NorwayArticle: 142059
On Jul 22, 2:09=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > On Tue, 21 Jul 2009 06:08:46 -0700 (PDT), Andy <jonesa...@comcast.net> wr= ote: > >Unfortunately, the generate statement only allows conditionally > >including concurrent statements. > > so does that mean that, for example, you couldn't use it to conditionally= exclude particular case > branches in a case structure? > > > > >You must use subprograms or if- > >statements based on generics for conditionally executing sequential > >code. And while you can't conditionally declare objects, you can make > >unconditional declarations dependent upon generic parameters > >(constants can be initialized by a function call that takes a > >generic). Generate does allow a local declarative region for the > >concurrent statement(s) that are included, but those declarations are > >not visible outside of it. > > >In most cases you can use a constant anywhere you could use a generic. > >You can use a generic anywhere you could use a deferred constant > >(beware locally static restrictions). > > >With generic driven packages in the new standard, the (dis)advantages > >of generics vs package of constants may get more blurred. > > >Andy > > The replies so far suggest to me that it could get far more complicated t= han it would be if a #ifdef > type feature were available, which would be universally applicable to any= type of construct. > I've yet to look in detail but it seems like the code/project structure h= as to be significantly > designed around the need to handle variants. > > ISPLever can specify pin mapping within the VHDL, so this would also prov= ide a way to handle pinout > differences between boards. > I can't immediately see any way to make ISPLever select different prefere= nces files based on a > simple option - any suggestions/examples on this would be appreciated. Looks like something like ifdef's in the preference file might be helpful. ispLever has this, a user can have many options inside one preference file. This is called 'preference scripts' in ispLever help. Please have have a look at : Design Flow User Guide>Design Implementation>Applying Design Constraints> Using Preference Scripts in ispLever html help. You can have a single preference file for different boards/FPGA targets and/or for DEBUG or release, for example. You will still have to do a simple edit for the .lpf, however it can be done in a clearly defined 'header' region with main (verbose) variables. AlexArticle: 142060
On Jul 22, 6:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > jleslie48 <j...@jonathanleslie.com> writes: > > Sorry to start from scratch yet again, but I don't know where to > > begin. > > > In the past I've had log file info dump out onto a UART as > > necessary. The UART is slow, and requires an additional device to > > capture the datastream. > > How fast do you need? FTDIs UART-USB (TTL-232R-3V3) cable will go @ > 3Mbps IIRC. It's an extra cable, hardly a device though, unless you > count the PC as well? > > http://apple.clickandbuild.com/cnb/shop/ftdichip?productID=53&search=... > > > I want to be able to write to a removable memory stick, or compact > > flash card, but I don't have any idea how to do it. When the FPGA is > > powered up it should start a new "file" on the compact flash card, and > > start writing to it. On commanded bit or powerdown, the file should > > be closed, and stored such that I can pull the card, plug it into a PC > > and read the file with notepad or such. > > Is this sort of thing any use? > > http://www.vinculum.com/ > > Easy modules:http://apple.clickandbuild.com/cnb/shop/ftdichip?op=catalogue-product... > > I've never used them, but it looks like a simple way to add use-storage > to a system. > > Failing that, glue a USB host controller on the side and run linux on a > microblaze. > > [BTW, even though I sound like an FTDI salesman I have no affiliation > with FTDI, other than having used various of their products!] > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html Ok, I'm looking at these solutions, they look promising, but has anyone actually got one of these to work? I've got a Diligent test board and it has a compact flash reader on it, so I'm assuming someone actually used this reader for something, but I can't find any test code or any clue how to use it. I keep hearing something about microblaze, and then I can write C code, but I have yet to stumble onto an example.Article: 142061
Torfinn Ingolfsen wrote:
> I just got myself a fpga development board (Altera DE1[1]) to play with.
> The free development tools (Quartus II web edition) runs only under
> windows.
> The subscription edition of Quartus II is priced well beyond my reach
> (oh, Altera, why no free edition for Linux?).
Using vhdl or verilog description, you could enter and verify
the design using free unix editors and simulators.
To synthesize and load your design onto the board however,
you will need some version of quartus.
-- Mike Treseler
Article: 142062On Thu, 23 Jul 2009 20:41:50 +0200, Torfinn Ingolfsen <tingo@start.no> wrote: >I just got myself a fpga development board (Altera DE1[1]) to play with. >The free development tools (Quartus II web edition) runs only under windows. >The subscription edition of Quartus II is priced well beyond my reach >(oh, Altera, why no free edition for Linux?). > >I prefer to run FreeBSD[2] on my workstations, or Linux[2] if I can't >run FreeBSD. > >Are there alternative development tools for Altera (DE1) that runs under >FreeBSD? >I anyone here running their fpga development tools on FreeBSD? > >I tried googling, but didm't find anything interesting. > >References: >1) >http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=83 >2) http://www.freebsd.org/ >3) http://xubuntu.org/ How about running quartus for windows in Virtual box ? You still need a windows license but better than dual-booting. - Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 142063
On Thu, 23 Jul 2009 20:41:50 +0200, Torfinn Ingolfsen wrote: > I just got myself a fpga development board (Altera DE1[1]) to play with. > The free development tools (Quartus II web edition) runs only under > windows. The subscription edition of Quartus II is priced well beyond my > reach (oh, Altera, why no free edition for Linux?). > > I prefer to run FreeBSD[2] on my workstations, or Linux[2] if I can't > run FreeBSD. > > Are there alternative development tools for Altera (DE1) that runs under > FreeBSD? > I anyone here running their fpga development tools on FreeBSD? > > I tried googling, but didm't find anything interesting. > > References: > 1) > http://www.terasic.com.tw/cgi-bin/page/archive.pl? Language=English&CategoryNo=39&No=83 > 2) http://www.freebsd.org/ > 3) http://xubuntu.org/ They want to limit your productivity with the free tools, that's why it's Windows only. Your best bet would be to run an XP VM. I don't know what VM tools are available for BSD but with Linux you have lots of choices. For a Windows VM your best bet would be to use VMWare Server 2, which is the free edition of VMware. VMware Server 2 requires a .27 kernel or lower so you can't use it with Fedora 11, but it's fine with Fedora 10 or CentOS5.3. If you do a SAMBA export of your project directories, and do a network mount in the XP VM, you can do everything in Linux except for running Quartus which you will have to run from the VM.Article: 142064
Torfinn Ingolfsen <tingo@start.no> wrote: < I just got myself a fpga development board (Altera DE1[1]) to play with. < The free development tools (Quartus II web edition) runs only under windows. < The subscription edition of Quartus II is priced well beyond my reach < (oh, Altera, why no free edition for Linux?). Will it run on wine? I thought I remembered some running such on wine, but I haven't heard that recently. Since Xilinx has Linux versions, I would expect Altera to be working on it. -- glenArticle: 142065
On Thu, 23 Jul 2009 19:27:54 +0000, glen herrmannsfeldt wrote: > Torfinn Ingolfsen <tingo@start.no> wrote: < I just got myself a fpga > development board (Altera DE1[1]) to play with. < The free development > tools (Quartus II web edition) runs only under windows. < The > subscription edition of Quartus II is priced well beyond my reach < (oh, > Altera, why no free edition for Linux?). > > Will it run on wine? I thought I remembered some running such on wine, > but I haven't heard that recently. Since Xilinx has Linux versions, I > would expect Altera to be working on it. > > -- glen Altera does support Linux in their subscription edition, it's the free version that's limited to Windows.Article: 142066
General Schvantzkoph <schvantzkoph@yahoo.com> wrote: > Altera does support Linux in their subscription edition, it's the free > version that's limited to Windows. Yes, but Xilinx has a free version for Linux. I believe it won't do the largest devices, but it will do enough for many people, and especially for the affordable development boards. I believe that before the Linux versions, Xilinx or Altera software would run on wine, but I don't remember which one. -- glenArticle: 142067
"saras" ...
> hi all, I am using SPARTAN - 3AN FPGA . While progaramming the FPGA ,
> it erases , programs and verifiys successfully but at the end, I get
> PROGRAMMING FAILED status..The reason it says is DONE pin did'nt go
> high..
> But if I erase the on -board DSP and then program FPGA, I get
> PROGRAMMING SUCCESSFULL. I am not understaning this. DONE signal is
> supposed to be genearated by FPGA..Why DSP has to be erased? All the
> required signals for programming like INIT_B , PROG is generated by
> another on -board microcontroller. Please provide some suggestions.
Don't you need a pull-up resistor for that? Did you program it in the FPGA
stream, or in the DSP (or maybe it's default in the DSP when erased)?
>From the manuals:
"The FPGA actively drives the DONE pin Low during configuration. When the
configuration process successfully completes, the FPGA either actively
drives the DONE pin High ("DriveDone") or allows the DONE pin to float High
using either an internal or external pull-up resistor, controlled by the
DonePin bitstream generator option. In a multi-FPGA daisy-chain or broadside
configuration, the open-drain option permits the DONE lines of multiple
FPGAs to be tied together, so that the common node transitions High only
after all of the FPGAs have successfully completed configuration. Externally
holding the open-drain DONE pin Low stalls the "Startup" sequence. The DONE
pin is powered by the VCCAUX"
Arie
Article: 142068On Thu, 23 Jul 2009 19:46:30 +0000, glen herrmannsfeldt wrote: > General Schvantzkoph <schvantzkoph@yahoo.com> wrote: > >> Altera does support Linux in their subscription edition, it's the free >> version that's limited to Windows. > > Yes, but Xilinx has a free version for Linux. I believe it won't do the > largest devices, but it will do enough for many people, and especially > for the affordable development boards. > > I believe that before the Linux versions, Xilinx or Altera software > would run on wine, but I don't remember which one. > > -- glen Way back in the ISE4.x days the Xilinx tools ran under wine, native Linux support was added in the ISE 5.x tools. The Xilinx tools started life as UNIX command line programs which made running them under wine trivial. I don't know if the same can be said for Altera.Article: 142069
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > Torfinn Ingolfsen <tingo@start.no> wrote: > < I just got myself a fpga development board (Altera DE1[1]) to play with. > < The free development tools (Quartus II web edition) runs only > < under windows. > < The subscription edition of Quartus II is priced well beyond my reach > < (oh, Altera, why no free edition for Linux?). > Will it run on wine? I thought I remembered some running such > on wine, but I haven't heard that recently. Since Xilinx has > Linux versions, I would expect Altera to be working on it. The program as such have good chances to run, but the protection mechanism and sometimes the install are major obstacles. I wish the Altera/Lattice would take to Codeweavers to get the rough edges rounded... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142070
glen herrmannsfeldt wrote: > I believe that before the Linux versions, Xilinx or Altera > software would run on wine, but I don't remember which one. I think it is Xilinx, because last week I've tried to install the latest version of Quartus on Debian Linux with wine and it doesn't work. With standard wine setup (running wine in XP mode), it just freezes after installing and if you stop this, it freezes when trying to start the program. The only way was to switch to Windows 98 mode. Then at least Quartus starts, but with lots of error messages from Cygwin that Windows 98 is not supported. The IDE starts and you can edit files, even diagrams works, but when you click the syntesize button, it displays some error message and the program exits. The ironic thing is, that on Windows it does lots of things with Cygwin to simulate a Unix environment, so looks like it is only some proparitary Windows GUI component of the IDE which prevents the use on Linux. Maybe calling the tools by command line would work. If some Altera staff reads this: What do you think about using Qt? It's LPGL even on Windows now that Nokia bought it. With this GUI library it should be possible to release Quartus for Windows, Linux and even for Macintosh, without much individual code for the different platforms. Other EDA companies have switched already, like CadSoft for EAGLE. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142071
On Jul 23, 1:03=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 23, 1:09=A0pm, dowlers <eoindowl...@gmail.com> wrote: > > > > Do you want to hide the fact that it's an FPGA? We epoxy pin-fin > > > heatsinks on top. > > > >ftp://jjlarkin.lmi.net/DSC01786.JPG > > > > John > > > Not really hide but advertise company name. It is a non volotile FPGA - > > XP2. > > I have found a company - Action Circuits. > > > Eoin > > Lattice make custom marking too, if you ask, but min qty applies > > Antti Thanks Antti I am aware, it is a good option from Lattice but the MOQ ~1800 -is too high for the moment... EoinArticle: 142072
dowlers wrote: > I am aware, it is a good option from Lattice but the MOQ ~1800 -is too > high for the moment... maybe it is more cost-effective to just stick/glue a label ? or even the waranty label ? :-) > Eoin yg -- http://ygdes.com / http://yasep.orgArticle: 142073
On Thu, 23 Jul 2009 20:08:21 +0000, Uwe Bonnes wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >> Torfinn Ingolfsen <tingo@start.no> wrote: < I just got myself a fpga >> development board (Altera DE1[1]) to play with. < The free development >> tools (Quartus II web edition) runs only < under windows. >> < The subscription edition of Quartus II is priced well beyond my reach >> < (oh, Altera, why no free edition for Linux?). > >> Will it run on wine? I thought I remembered some running such on wine, >> but I haven't heard that recently. Since Xilinx has Linux versions, I >> would expect Altera to be working on it. > > The program as such have good chances to run, but the protection > mechanism and sometimes the install are major obstacles. > > I wish the Altera/Lattice would take to Codeweavers to get the rough > edges rounded... The issue isn't technical, the subscription edition has been running on Linux for years. Altera has always regarded their tools as a profit center, they've been using Flexlm for years, and as such they want to offer the bare minimum in the free package. They also probably have some idea that it costs them more to support Linux, I doubt that true, the Linux version of Quartus is as least as solid as the Windows version, but chances are that's what they think.Article: 142074
General Schvantzkoph <schvantzkoph@yahoo.com> writes: > offer the bare minimum in the free package. They also probably have some > idea that it costs them more to support Linux, I doubt that true, the I always thought that Altera had to pay a per seat license fee to the Windu toolkit developers. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
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