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Guys and Girls Your chance to have input to what we bring to market as Spartan-6 products. We have several release candidates nearly ready now but we can still add or modify features and I am interested in features you would all like to have in these boards either based on things we hve done before in our product range or even new features you would like to see. So go ahead and let us know what you want. John Adair Enterpoint Ltd. - Home of Merrick1. The HPC solution.Article: 142401
On Aug 9, 3:44=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > Guys and Girls > > Your chance to have input to what we bring to market as Spartan-6 > products. > > We have several release candidates nearly ready now but we can still > add or modify features and I am interested in features you would all > like to have in these boards either based on things we hve done before > in our product range or even new features you would like to see. > > So go ahead and let us know what you want. > > John Adair > Enterpoint Ltd. - Home of Merrick1. The HPC solution. if you could ship BEFORE Xilinx SP-601 availability, there would be interest. if not.. sure there is still place for more boards, but at the moment its the time that counts, when would you ship? guaranteed time of delivery? can you answer that today? [No] I have ordered from those who have announced first, only to find out that orders are accepted but fulfilled way later (after competitors have better products) AnttiArticle: 142402
John Adair <g1@enterpoint.co.uk> wrote:
>Guys and Girls
>
>Your chance to have input to what we bring to market as Spartan-6
>products.
>
>We have several release candidates nearly ready now but we can still
>add or modify features and I am interested in features you would all
>like to have in these boards either based on things we hve done before
>in our product range or even new features you would like to see.
>
>So go ahead and let us know what you want.
I'd go for as few options as possible and loads of room for additional
circuitry and small pads to attach (enameled) wires to the FPGA.
Whenever I start using a new microcontroller I make a prototype board
with the least possible features. The less features, the greater the
possibilities. If people want to do high-speed stuff they'll have to
make their own boards anyway.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142403
Peter Alfke <alfke@sbcglobal.net> wrote:
>On Aug 8, 2:26=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>
>>
>> Well, if Peter is no longer employed by Xilinx he is free to post
>> whatever he wants in this newsgroup :-)
>>
>Nico, I was never ever held back, censored or reprimanded by Xilinx
>management.
Previous posts from Austin indicated Xilinx has (strict) rules for
Xilinx employees regarding posting messages on the internet. Which is
understandable for a company like Xilinx.
>After the end of this month I will no longer be an employee, but still
>a shareholder of Xilinx.
>And I owe this company a lot of gratitude, financial, intellectual,
>and emotional.
>It was "the best years of my life".
>So don't expect me to divulge any "dirty secrets", whatever you might
>imagine them to be.
I wasn't refering to exposing dirty secrets (goes against my
professional ethics too). I just guessed you have more time on your
hands and no management to approve messages. In other words: less
hassle. My posting was intended as 'Take it easy and enlighten us if
you feel like it'.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142404Antti At the moment all I can say is we don't have production amounts of silicon available. The dates for production silicon arrival are still flexible and confidential so we can't give any guarantees on dates for boards as yet. xilinx probably will feed their own asembly first but I'm sure we won't be far behind in our shipping. To a dregree our product announcement will be linked to a reason expectation of when we have silicon. There also questions of whether customers want silicon without the fully fixed memory controller in there. John Adair Enterpoint Ltd. On 9 Aug, 15:45, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Aug 9, 3:44=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > > > Guys and Girls > > > Your chance to have input to what we bring to market as Spartan-6 > > products. > > > We have several release candidates nearly ready now but we can still > > add or modify features and I am interested in features you would all > > like to have in these boards either based on things we hve done before > > in our product range or even new features you would like to see. > > > So go ahead and let us know what you want. > > > John Adair > > Enterpoint Ltd. - Home of Merrick1. The HPC solution. > > if you could ship BEFORE Xilinx SP-601 availability, > there would be interest. if not.. sure there is still > place for more boards, but at the moment its the > time that counts, when would you ship? > guaranteed time of delivery? > > can you answer that today? > [No] > > I have ordered from those who have announced first, > only to find out that orders are accepted but fulfilled > way later (after competitors have better products) > > AnttiArticle: 142405
Nico It's umlikely we would encourage direct soldering to development boards principally because we might end up with warranty issues. However it is very much in our tradition that we make a higher number of I/Os "free of function" than our compeditors and that is very unlikely to change. We are adding a little more to boards now than the early days but that is driven by customer demand and not what product lines we cover like disti board designs. When we can we do compensate for the extra bits by design or bigger I/O packages so lot's of I/O are left free. If had not seen our boards up close our standard customer headers for expansion is based on 0.1 inch (2,54mm) pitch headers. These headers are also spaced on multiples of 0.1 inch.That layout allows stripboard or simple add modules to be attached to the development board. The headers work well at low speed and not so bad high speed as well. If you also want a maximum I/O for customer use do have a look at our Darnaw1 http://www.enterpoint.co.uk/moelbryn/darnaw1.html or Craignell1/2 http://www.enterpoint.co.uk/component_replacements/craignell2.= html, http://www.enterpoint.co.uk/component_replacements/craignell.html. Polmaddie1 also gives some of these features as do some other boards. We do have long term plans for all of these products to extend into Spartan-6 replacements as and when demand dictates and our engineering team has time. It is our general policy to be "compatible" as we can with older products so that any customer designed add-ons can be used in later designs wherever that is possible. Our headers have evolved in the last few designs and those seen on Mulldonnoch2 http://www.enterpoint.co.uk/oem_industrial/mulldonnoch2.html are going to be the norm whenever we do that although some boards may not have features like the user set regulator and all the ancillary fixed voltages. The complete length strips of 0V/GND and 3.3V seem on Mulldonnoch2 are now the minimum to be expected on boards supporting headers. In general that would be Broaddown, Raggedstone, Drigmorn and Merrick ranges. John Adair Enterpoint Ltd. On 9 Aug, 16:07, n...@puntnl.niks (Nico Coesel) wrote: > John Adair <g...@enterpoint.co.uk> wrote: > >Guys and Girls > > >Your chance to have input to what we bring to market as Spartan-6 > >products. > > >We have several release candidates nearly ready now but we can still > >add or modify features and I am interested in features you would all > >like to have in these boards either based on things we hve done before > >in our product range or even new features you would like to see. > > >So go ahead and let us know what you want. > > I'd go for as few options as possible and loads of room for additional > circuitry and small pads to attach (enameled) wires to the FPGA. > > Whenever I start using a new microcontroller I make a prototype board > with the least possible features. The less features, the greater the > possibilities. If people want to do high-speed stuff they'll have to > make their own boards anyway. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > --------------------------------------------------------------Article: 142406
On Sun, 9 Aug 2009 05:44:15 -0700 (PDT), John Adair <g1@enterpoint.co.uk> wrote: >Guys and Girls > >Your chance to have input to what we bring to market as Spartan-6 >products. > >We have several release candidates nearly ready now but we can still >add or modify features and I am interested in features you would all >like to have in these boards either based on things we hve done before >in our product range or even new features you would like to see. > >So go ahead and let us know what you want. I'm looking for a standard high speed extension bus. I used the Avnet exp to good results but these days FMC seems to be the new standard. A LPC FMC connector header would be nice. - Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 142407
John Adair <g1@enterpoint.co.uk> wrote: < Your chance to have input to what we bring to market as < Spartan-6 products. < We have several release candidates nearly ready now but we can still < add or modify features and I am interested in features you would all < like to have in these boards either based on things we hve done before < in our product range or even new features you would like to see. I was thinking not so long ago that it would be nice to have a board ready to build a clock radio, including the appropriate external parts for an SDR (software defined radio, I believe). The idea was a board for beginning and intermediate EE/CS projects that could also be mounted in a nice box for a completed project. One could use or not use the LED display and/or radio parts, as usual for such boards. -- glenArticle: 142408
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > In most cases, the mass market software sells in large enough > quantities to overcome a small side usage. If not, then a new > business model is needed. Note that no grocery items are protected > by AES, and yet they seem to be able to seel them and make a profit. Coming in a little late at this thread, but anyway... One way to tackle this issue is general economics. Don't try to drive your product into the ground by piling it high with layers of costly DRM (which may well backfire on you, and may distract from your actual market intentions). So build a better product than the competition, or a cheaper one, or build up enough of a market share by being first that imitations don't matter (like I suspect Apple doesn't care about $10 Chinese knockoff MP3 players because they're hardly in the same marketplace). The next way is to think about security economics. If it costs someone $1million to clone your product, is it worth it? What about $100K, $10K, $1K? So make it economically unaffordable to do so. Now Russian or Chinese labour is cheap, so this has become more difficult of late. But, for example, Datel put in $17million (IIRC) into reverse engineering Sony's MagicGate chip (the DRM controller Sony's MemoryStick flash format) and didn't succeed. The chip was a mass of random gates, with no structure. With semi-automated netlist generation tools they got a netlist, but it didn't work. That investment, if successful, would probably have been worthwhile given the worldwide sales of MemorySticks. But if your field is smaller, your attacker has to spend less money before it becomes economically infeasible. So perhaps simply potting your board in epoxy is enough (but a bit of a pain from a service point of view). If you're worried about your board being repurposed for something else, make their life difficult. Use wierd connectors, and route all the traces on an internal PCB layer so they can't easily be tapped and patched (a mistake the Xbox people made). If the attacker has to spend $100 on parts and some hours customising your board almost everyone probably won't bother. And if your board costs much more than $100 less than another major application area, just increase the faff-cost to the customiser until they're level. If someone is really keen, they'll be desoldering FPGAs or depackaging your chip, applying lasers or Focused Ion Beams to it, looking at its EM emissions or many other evil things. The way to protect against that is either to make that economically infeasible (so reduce the gain from doing this) or else apply a higher level control. I may have an attack where I'm able to deduce a PIN in 50 guesses. But if the bank only allows me three, I'll only be successful about 6% of the time (and to do this frequently enough to get a decent return I run the risk that I'm intercepted and locked up). Or a combination may apply. So, despite all the security in smartcards, let's assume I can copy your bank card. I can go to ATMs and withdraw lots of money. This is only worthwhile if the cost for me to clone the card was less than you have in your account. But the bank will notice this unusual pattern after a while and block the card. So even if I clone Bill Gates' card I can't go on raiding his account forever. If the bank blocks the card before I've received back the investment I put in in cracking the card, the attack isn't worth it. Theo -- Security research, University of Cambridge Computer Laboratory http://www.cl.cam.ac.uk/~atm26/Article: 142409
On Thu, 06 Aug 2009 14:21:34 +0000, Allan Herriman wrote: > On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote: > >> On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote: >> >>> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph >>> <schvantzkoph@yahoo.com> wrote: >>> >>>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and >>>>Altera FPGA tools? >>> >>> I'd also be very interested in Core7 vs Phenom II performance too >>> (45nm AMD ie Phenom II 955 etc.) >> >> >> We just got a new i7 machine for FPGA builds. It tested at just over >> twice as fast as our high-end AMD box that was 2-3 years old. >> >> I will publish the results in this ng within a week or two, assuming I >> can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx, >> flexlm was a really good move.) > > > It's been a week and we still can't get the Xilinx licensing working on > the new machine, so I can't post any ISE11.2 results. I assume we will > be able to get the licensing running soon, because I have told the local > Xilinx reps that I won't be designing their parts into new products if > we can't run the software. My last big design used an Altera FPGA, so > they know I'm not joking. > > Here are the two machines: > > Old machine: > AMD Phenom 9750 CPU 2.40GHz > MSI K9A2-CD-F Motherboard (AMD 790X Chipset) 8GB Corsair > TWIN2X2048-8500C5DF Xtreme CL5 DDR2 RAM (1066MHz) Windows XP > Professional x64 Edition Version 2003 Service Pack 2 > > New machine: > Intel Core i7 Extreme Edition 975 CPU 3.33GHz Asus Rampage-II-Extreme > Motherboard (Intel X58 Chipset) 12GB OCZ Platinum Low-Voltage Triple > Channel CL7 DDR3 RAM (1600MHz), Windows Server 2003 R2 Standard x64 > Edition Service Pack 2. > > > Using ISE8.2 SP3 (yes, 8.2) on an old test design that almost filled a > medium sized fpga, we recorded a run time of 6 hours and 12 minutes for > the older AMD machine, and 3 hours and 3 minutes for the new i7 machine. > That's 2.03 times as fast. > > The runs contained XST, ngdbuild, map, par, etc. In both cases, the 32 > bit version of software was used. Peak memory usage (during map) was > just under 3GBytes. Map was run with the -speed option. > > Regards, > Allan I should point out that hyperthreading was turned ON on the i7 machine. The results might be a little quicker with hyperthreading turned off. I'm not worried about the loss of parallelism here; the thing has four cores, each capable of hyperthreading, and most of the cores will be idle most of the time. The FPGA build machines here are dedicated to doing just that and are headless. We use different machines for desktop work and simulations, etc. Regards, AllanArticle: 142410
We have been looking at the FMC standard but it does have a pile of problems for us and our potential customers. This specification was written by a group of people all from companies, in the same market sectors, and with a very limited vison as a result. Problems as I see it: (1) The specification costs a lot to buy and will limit widespread adoption and potential customer base. (2) The format is very small even on the bigger version. (3) A lot of on-module regulation will be needed further limiting what else can be done on the module. (4) On small and medium size devices, e.g. most Spartans, it uses up most I/O that we would normally use for our own headers and we can't maintain our support for existing customers. (5) Connectors are very expensive and single source. I will say Samtec is a very good supplier of connectors but even so if they go out of business where are the connectors coming from. (6) The currently available FMC modules are many times the price of a potential Spartan-6 board especially a starter kit Spartan-6. (7) There may be IP or licensing issues as a result of the way the spec is controlled and owned. That all said the attraction of common standard is a nice idea. I'm just not sure of the practical and cost aspects of it as FMC currently appears. There are so many connector standards that could have been either reused or just used as is without a totally new standard. One of my personal favorites is the PC104 connectors that we allready use both in normal mode but also in custom fashions for some of our products. We also do that just by FPGA configuration and that selection doesn't affect the hardware aspects of our boards. I think we will adopt FMC on our high end Spartan-6 boards and maybe have an adaptor available for our low end. We are looking at the practicality of that. Our Virtex-6 boards may have this as standard but we debating that. We will also John Adair Enterpoint Ltd. On 9 Aug, 21:11, Muzaffer Kal <k...@dspia.com> wrote: > On Sun, 9 Aug 2009 05:44:15 -0700 (PDT), John Adair > > <g...@enterpoint.co.uk> wrote: > >Guys and Girls > > >Your chance to have input to what we bring to market as Spartan-6 > >products. > > >We have several release candidates nearly ready now but we can still > >add or modify features and I am interested in features you would all > >like to have in these boards either based on things we hve done before > >in our product range or even new features you would like to see. > > >So go ahead and let us know what you want. > > I'm looking for a standard high speed extension bus. I used the Avnet > exp to good results but these days FMC seems to be the new standard. A > LPC FMC connector header would be nice. > - > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.comArticle: 142411
As it happens one of our first release candidates may be quite good for this. It will need an add-on module for the front end RF and maybe our simple R/2R DAC module to drive a speaker but probably very close to what you want. John Adair Enterpoint Ltd. On 10 Aug, 00:42, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > < Your chance to have input to what we bring to market as > < Spartan-6 products. > > < We have several release candidates nearly ready now but we can still > < add or modify features and I am interested in features you would all > < like to have in these boards either based on things we hve done before > < in our product range or even new features you would like to see. > > I was thinking not so long ago that it would be nice to > have a board ready to build a clock radio, including the > appropriate external parts for an SDR (software defined > radio, I believe). =A0The idea was a board for beginning and > intermediate EE/CS projects that could also be mounted in > a nice box for a completed project. =A0One could use or not use > the LED display and/or radio parts, as usual for such boards. > > -- glenArticle: 142412
On Aug 10, 1:42=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > < Your chance to have input to what we bring to market as > < Spartan-6 products. > > < We have several release candidates nearly ready now but we can still > < add or modify features and I am interested in features you would all > < like to have in these boards either based on things we hve done before > < in our product range or even new features you would like to see. > > I was thinking not so long ago that it would be nice to > have a board ready to build a clock radio, including the > appropriate external parts for an SDR (software defined > radio, I believe). =A0The idea was a board for beginning and > intermediate EE/CS projects that could also be mounted in > a nice box for a completed project. =A0One could use or not use > the LED display and/or radio parts, as usual for such boards. > > -- glen Hi john, I was thinking about the same: a nice board that will be able to do SDR application so mean include at least one fast ADC and DAC (>100MSPS, 200 would be better in order to play in FM bandwidth without any analogic stage) I am currently playing with a Terasic board : DE2-70 and using the video ADV7123 as a DAC: I have been able to generate FM broadcast with it,but I am now missing an ADC in order to do a loopback and analyze what i generate. Like this a board including those component would be able to do SDR applications, video applications, or things like a scope, spectrum analyzer... I have been thinking and a video ADC like AD9483 might be a good choice as it offer 3 fast channel , the resolution is low but i believe is enought for lab testing. But if you add ADC/DAC on your board you should have as much output channel than input , they should be same resolution and same clock speed... Can you tell us about the targeted price for you board is it like around a few hundred euros/pound, or more a thousand?Article: 142413
John, A header option you might not have considered is Altera's HSMC interface. This is becoming a 'standard' on all their new dev boards with an expanding range of add onn cards available off the shelf. http://www.altera.com/products/devkits/kit-daughter_boards.jsp It does take quite a few device pins though, this might rule it out. (I have to admit to producing one of the add on boards listed). Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883 32/12 Hardengreen Business Park Fax: +44 131 663 8771 Dalkeith, Midlothian EH22 3NX www.nialstewartdevelopments.co.ukArticle: 142414
> So I don't already understand where the pin LVDS195p/nCEO come from > and even more why the fitter put it on an assigned pin What configuration type have you selected, it might be that one of the required pins is one you've selected as user io? Also check Assigmnents->Device -> Device and Pin Options, there are options to allow some config pins to be used as user IO when configuration's finished. (I've only got an old version of Quartus on this PC so can't check). NialArticle: 142415
Hi it seems that i may have lost all my skills of using google :( as I havent found any ready to use HDL for for DS DAC with higher order than 1 only research papers, or then commercial cores, but absolutly no HDL sources. this cant be true? or is there some magic reason why all online DS DAC code is first order only? so far i have failed to figure out what the reason could be. AnttiArticle: 142416
On Aug 6, 1:37=A0pm, JimLewis <J...@SynthWorks.com> wrote: > Kevin, > It is here:https://bugzilla.mentor.com/show_bug.cgi?id=3D240 > > Note it is IR 2132, however it is bugzilla issue 240. > > Best, > Jim Bug #275 has been submitted as an enhancement to the language to allow for opens on vector subelements. Kevin JenningsArticle: 142417
"Sudhir Singh" <Sudhir.Singh@email.com> wrote > > Are you saying > that regardless of what ever speed the line is operating at > (10/100/1000 Mbps), the PHY will always have the interface to the MAC > operating at 1000Mbps, i.e in GMII? It won't be operating at 1000 Mbps regardless, but the clock direction will not change either. The clock frequency however should change to 25 MHz in 100Mb mode, and to 2.5MHz in 10Mb mode. > > The Micrel PHY I am looking at has a boot strap option of starting in > GMII/MII mode, I couldn't see anything to force a GMII only mode. I am > wondering whether PHY switches to MII when it finds a 10/100 Mbps > device at the other end, and switches to GMII if it finds a 1000Mbps > device. It really shouldn't. It should stay in the mode found at the boot time. Think of the MII mode as just a legacy thing required to interface to an obsolete MAC. /MikhailArticle: 142418
The biggest problem with fitting fast ADC/DAC on the board is the cost. It means that other people that might buy the board don't and hence you end up with a board with small sales and hence large costs. To some extend FMC or another module system is an answer allowing a more generic product for price. The other problem is the choice of ADC/ DAC is very variable andhard fitting a particular ADC/DAC combo can reduce the sales. For the meantime the modular approach is best although we do often do customised variants of standard boards for specif customers in numbers as low as 25 off. The range of products that we are about to release range for $200 to $200K so I'm sure there something of a match in there. I think a lower module will probably do it but the ADC/DAC combo maybe more significant. John Adair Enterpoint Ltd. On 10 Aug, 08:55, kclo4 <alexis.ga...@gmail.com> wrote: > On Aug 10, 1:42=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > > > > John Adair <g...@enterpoint.co.uk> wrote: > > > < Your chance to have input to what we bring to market as > > < Spartan-6 products. > > > < We have several release candidates nearly ready now but we can still > > < add or modify features and I am interested in features you would all > > < like to have in these boards either based on things we hve done befor= e > > < in our product range or even new features you would like to see. > > > I was thinking not so long ago that it would be nice to > > have a board ready to build a clock radio, including the > > appropriate external parts for an SDR (software defined > > radio, I believe). =A0The idea was a board for beginning and > > intermediate EE/CS projects that could also be mounted in > > a nice box for a completed project. =A0One could use or not use > > the LED display and/or radio parts, as usual for such boards. > > > -- glen > > Hi john, > > =A0I was thinking about the same: a nice board that will be able to do > SDR application so mean include at least one fast ADC and DAC > (>100MSPS, 200 would be better in order to play in FM bandwidth > without any analogic stage) > I am currently playing with a Terasic board : DE2-70 and using the > video ADV7123 as a DAC: I have been able to generate FM broadcast with > it,but I am now missing an ADC in order to do a loopback and analyze > what i generate. Like this a board including those component would be > able to do SDR applications, video applications, or things like a > scope, spectrum analyzer... > I have been thinking and a video ADC like AD9483 might be a good > choice as it offer 3 fast channel , the resolution is low but i > believe is enought for lab testing. > But if you add ADC/DAC on your board you should have as much output > channel than input , they should be same resolution and same clock > speed... > > Can you tell us about the targeted price for you board is it like > around a few hundred euros/pound, or more a thousand?Article: 142419
On 10 Aug, 10:05, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > John, > > A header option you might not have considered is Altera's HSMC > interface. > > This is becoming a 'standard' on all their new dev boards with an > expanding range of add onn cards available off the shelf. > Using an Altera stabdard for a Xilinx board might ruffle a few feathers back in San Jose but again havinf a common standard would be good. The Altera way of add-on is more sensible than FMC allowing stanardish connectors to be used and a less rigid physical form too. The connectors still are not cheap and I don't see a good way to have several modules covering a requirement. If you see they dip headers we use now we can in some cases have 5 different, or even the same, modules fitted and that is selectable totally on a user need. The comment on pins is the same unfortunately although the Altera header may make onto our Altera product range at some point. John Adair Enterpoint Ltd. > http://www.altera.com/products/devkits/kit-daughter_boards.jsp > > It does take quite a few device pins though, this might rule it > out. > > (I have to admit to producing one of the add on boards listed). > > Nial > > ---------------------------------------------------------- > Nial Stewart Developments Ltd =A0 =A0 =A0 =A0Tel: +44 131 516 8883 > 32/12 Hardengreen Business Park =A0 =A0 =A0Fax: +44 131 663 8771 > Dalkeith, Midlothian > EH22 3NXwww.nialstewartdevelopments.co.ukArticle: 142420
John Adair <g1@enterpoint.co.uk> wrote: < The biggest problem with fitting fast ADC/DAC on the board is the < cost. It means that other people that might buy the board don't and < hence you end up with a board with small sales and hence large costs. The idea was for a board that could be used for undergraduate CS/EE courses. For a freshman course, they could just do the clock part. A nice six digit LED display would do for that. (Why are six digit digital clocks so rare now?) For that, it would help to keep the price down, but you might be able to sell large numbers of them. I would prefer one that didn't need separate modules, but I do like the LED display on a separate board so that it can face out when the board is lying flat. As for ADC/DAC, for SDR as I understand it you would need a fast but not so wide (in bits) ADC, and a much slower DAC. You could put just the pads on, such that one could solder the parts in later. Or maybe a breadboard area, so that the students had to do a little work to get it running. < To some extend FMC or another module system is an answer allowing a < more generic product for price. The other problem is the choice of ADC/ < DAC is very variable andhard fitting a particular ADC/DAC combo can < reduce the sales. For the meantime the modular approach is best < although we do often do customised variants of standard boards for < specif customers in numbers as low as 25 off. If you design a board that one medium sized school uses for an introductory undergrad CS/EE course, that could already be a significant number of boards. Even more, if many schools would use it. -- glenArticle: 142421
Announcing the 1st ever FPGACamp event at Silicon Valley on Aug'26th. Attendance is FREE. More details & registration at http://www.fpgacentral.com/fpgacamp TOPIC: "High Speed Serial Interface: Protocols, IPs & Devices" The idea behind FPGA Camp is to bring semiconductor engineers together and discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories. We are hoping that this would act as a platform to bring all the FPGA users together more often. Agenda: 5:30 PM- 6:00 PM: Registration and demo 6:00 PM- 7:00 PM: Tech Talk- "High Speed Serial Interface: Protocols, IPs & Devices" 7:00 PM- 7:30 PM: Vendor talk- a brief talks from the vendors offering High Speed Serial Interface devices or IPs. (5 to 10 Mins each). 7:30 PM- 8:00 PM: Networking and exhibits Recent expansion in the video usage and growth in the Internet use have created a demand to move more data faster than ever. To meet this demand, system & chip designers are moving towards high speed serial interfaces such as PCIe, XAUI, Interlaken, XFI, 10GbE etc. With FPGA devices currently supporting speeds upto ~12.5Gb per IO pair, which makes FPGAs a unique choice for the next design. This talk will focus on familiarizing people with various protocols (both currently used & emerging), IPs & Devices which can be used to solve the next system problem. The talk will be followed by quick presentations from some of the vendors offering these solutions (no marketing talk, only technical). Registration: FREE! Feel free to bring a friend. For Registration/ RSVP visit http://www.fpgacentral.com/fpgacamp or http://events.linkedin.com/FPGA-Camp-High-Speed-Serial-Interfaces/pub/104860 Thanks, VikramArticle: 142422
On Sun, 26 Jul 2009 16:23:16 +0000, General Schvantzkoph wrote: > Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and > Altera FPGA tools? I have an iCore7 system up and running. It's a 920 overclocked to 3.6GHz using a Thermalright Ultra 120 Extreme. 3.6GHz seems to be the limit for stable operation. I also have a Core2 P8400 overclocked to 4GHz, it's been running at that speed for a year without problems. The iCore7 seems to be better for Xilinx tools, worse for NCSim. Here are the times (in seconds) for a Xilinx build (11.1 tools, Virtex6) and an NCVerilog regression. Both systems are running on 64 bit Fedora 11 with 8G of RAM. iCore7 Core2 iCore7/Core2 Normalized GHz 3.6 4 Xilinx 2040 2259 110.74% 123.04% NCverilog 1660 1358 81.81% 90.90% NC is incredibly cache sensitive, my guess is that the iCore7's three level cache doesn't work very well for NC.Article: 142423
"John Adair" <g1@enterpoint.co.uk> wrote in message news:d4baa37f-f871-4143-9711-23ce3d444009@g1g2000vbr.googlegroups.com... > Your chance to have input to what we bring to market as Spartan-6 > products. I do a lot of video algorithm development. DVI (dual-link) I/O would be great. HDMI and DisplayPort would be a nice addition. PeteArticle: 142424
Yes if you can hit a combination that suits a particular school you could make it worth doing. That's only every really happened though with a couple of boards in the market as far as I know. If you look at the sales of Spartan-3 boards apart from those boards the sales are relatively low and not in the critical mass area to make that all work. However if you have particular suggestions I am open to looking at them and pricing the cost of adding them to a product. John Adair Enterpoint Ltd. On 10 Aug, 19:13, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > < The biggest problem with fitting fast ADC/DAC on the board is the > < cost. It means that other people that might buy the board don't and > < hence you end up with a board with small sales and hence large costs. > > The idea was for a board that could be used for undergraduate > CS/EE courses. =A0For a freshman course, they could just do the > clock part. =A0A nice six digit LED display would do for that. > (Why are six digit digital clocks so rare now?) =A0For that, > it would help to keep the price down, but you might be able > to sell large numbers of them. =A0I would prefer one that didn't > need separate modules, but I do like the LED display on > a separate board so that it can face out when the board is > lying flat. =A0 > > As for ADC/DAC, for SDR as I understand it you would need a > fast but not so wide (in bits) ADC, and a much slower DAC. > > You could put just the pads on, such that one could solder > the parts in later. =A0Or maybe a breadboard area, so that > the students had to do a little work to get it running. > > < To some extend FMC or another module system is an answer allowing a > < more generic product for price. The other problem is the choice of ADC/ > < DAC is very variable andhard fitting a particular ADC/DAC combo can > < reduce the sales. For the meantime the modular approach is best > < although we do often do customised variants of standard boards for > < specif customers in numbers as low as 25 off. > > If you design a board that one medium sized school uses for > an introductory undergrad CS/EE course, that could already > be a significant number of boards. =A0Even more, if many schools > would use it. > > -- glen
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