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Torfinn Ingolfsen <tingo@start.no> writes: > But why (oh why) is the free IDE only for Windows? In the Altera case I assume it's because they have to pay a per seat licenses for their Linux window library (MainWin). > Interesting. Is this by any chance freely available / open source? No, at least not at the moment. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 142801
"Dennis Yurichev" <dennis.yurichev@gmail.com> wrote in message news:6080efe0-0c92-4152-aa85-002586e6a0dd@z34g2000vbl.googlegroups.com... > Hi. > > Does anybody had any real success on running OpenSPARC core on Altera > Stratix II? You might get more responses if you change OpenSparc to Leon, I looked at the OpenSparc code and build scripts years ago and found that this core is clearly marked for the ASIC/Cadence/Synopsys world rather than the FPGA world (it might have changed since then?). Leon is a great core and you'll be hard pressed to find anything better, Hans www.ht-lab.comArticle: 142802
On Tue, 01 Sep 2009 18:07:35 -0500, Jon Elson <jmelson@wustl.edu> wrote: >Frank Buss wrote: >> Antti.Lukats@googlemail.com wrote: >> >>> Option 1: >>> Get a PC with preinstalled WinXP/Vista and forget the attempts to use >>> FPGA tools under linux >>> This option saves lots of frustration and is worth the money spent >> >> I use Windows, too, but maybe a VMWare, or with another virtualization >> software, you don't need at least an extra PC (I'm using this on my desktop >> PC to run Debian Linux in VMWare, which works fine). Or install Linux and >> Windows on one PC with a bootmanager like Grub (this is my Laptop setup), >> but Murphy's Law says, that you just need some program for Linux fast (e.g. >> phone call from a customer and you have to check something) when Windows is >> booted and vice versa :-) >> >Windows 2K Pro running under VMWare works perfectly to program Xilinx >CPLDs with the Parallel Cable III. I'm sure it would work fine for >downloading FPGAs, also. (I just prefer EPROMS for that, as there are >less cables, par ports, etc. required that way. If you are using >ChipScope, then you need it hooked up anyway. The "libusb" driver from rmdir.de works well for me under Linux (OpenSuse 11) natively (no Windows required) with Parallel Cable IV. Works fine with both Impact and Chipscope. I also tried the Xilinx recommended "libusb" which apparently will work with their USB programming cables, but doesn't support the parallel cables. (the Xilinx supplied Windriver for the same purpose doesn't build with recent kernels!) - BrianArticle: 142803
Hi, I am new to the FPGA world. I am using chipcon CC2400 board and has the Xilinx's XC2S200E FPGA. Is it possible to program it program the FPGA in C? I donot have any experience in VHDL and verilog. If it possible to program in C, what interface can i use? CC2400 has a 10 pin JTAG. any help will be highly appreciable.Article: 142804
Hi, I get these errors when trying to grasp output datas using chipscope from ERROR:Pack:1564 - The dual data rate register ODDR_INST failed to join the OLOGIC component as required. The output signal for register symbol ODDR_INST requires general routing. If I directly implement the disign without the function of chipscope, then I dont get these errors. Once adding the chipscope,then I got the errors. Could anyone explain me this error, or maybe suggest another design? thanksArticle: 142805
Hi David Brown, > The trouble with a large polynomial like this is that the higher power > parts are very sensitive to the resolution. =A0For polynomials expressed > in this form, you'll want a great deal more binary point bits for the > later a_n coefficients, or to use floating point (which makes things > much more complicated). =A0With care and enough bits, and different > placement of the binary points depending on the values of a_n, you might > make it work well enough. In fact, the problem is precisely the higher coefficients. Coefficients range from 0.000xxx to xxxxxx.xxx, the problem is to optimize the multiplier. I was thinking about going down to 7 or 5 coefficients. > A lookup table with linear interpolation much easier to make accurately > than a large polynomial like this. =A0You could also compromise and use a > lookup table and quadratic or cubic interpolation to get more accuracy > from a smaller table. I never facing a problem like this until now. so I do not know where to begin to implement this technique. > Another idea, if your maths is up to it, is to use Chebyshev polynomials > instead of powers of x. =A0You would need more multipliers (18 for a nint= h > power polynomial, if I've done my sums right) and more adders, but all > your partial calculations and coefficients are on the same scale making > it much easier. > > http://en.wikipedia.org/wiki/Chebyshev_polynomials No. I can not. I have to save as much resources as possible. Thanks. Kappa.Article: 142806
"HT-Lab" <hans64@ht-lab.com> wrote in message news:U9rnm.29170$bU2.5046@newsfe29.ams2... > > "Dennis Yurichev" <dennis.yurichev@gmail.com> wrote in message > news:6080efe0-0c92-4152-aa85-002586e6a0dd@z34g2000vbl.googlegroups.com... >> Hi. >> >> Does anybody had any real success on running OpenSPARC core on Altera >> Stratix II? > > You might get more responses if you change OpenSparc to Leon, I looked at the > OpenSparc code and build scripts years ago and found that this core is clearly > marked for the ASIC/Cadence/Synopsys world rather than the FPGA world (it > might have changed since then?). It seems I am wrong :-( http://www.opensparc.net/fpga/index.html Hans www.ht-lab.com > > Leon is a great core and you'll be hard pressed to find anything better, > > Hans > www.ht-lab.com > >Article: 142807
Hi Jonathan, > With an 18-bit input, you have only 128K different input values. > It would be easy to write a small program to calculate all the > result values, and then compare them with the values obtained by > interpolation (or any other method). =A0You can then decide whether > the errors are small enough to be insignificant. Was what I was thinking. But to implement a memory 128K x 18 bits requires too many resources. > Consider this, though. =A0Suppose you make a 1024-entry table. =A0Use > the top 10 bits of your 18-bit data to address into the table. > Use the lower 8 bits for linear interpolation. =A0 This technique is not very clear to me ... can get more details? > I'm intrigued to know why you are applying a 9th order > polynomial transfer function to your signal. I'm realizing Digital Predistortion. With 9 polynomial coefficients i'm doing the fitting function for the amplifier. It would be sufficient even 5 or 7 I was experiencing with 9. Thanks. Kappa.Article: 142808
Kappa wrote: > Hi David Brown, > >> The trouble with a large polynomial like this is that the higher power >> parts are very sensitive to the resolution. For polynomials expressed >> in this form, you'll want a great deal more binary point bits for the >> later a_n coefficients, or to use floating point (which makes things >> much more complicated). With care and enough bits, and different >> placement of the binary points depending on the values of a_n, you might >> make it work well enough. > > In fact, the problem is precisely the higher coefficients. > Coefficients range from 0.000xxx to xxxxxx.xxx, the problem is to > optimize the multiplier. I was thinking about going down to 7 or 5 > coefficients. > Are you able to post the function and its coefficients, or perhaps the original function that the polynomial approximates? Where did the polynomial come from in the first place? If it is an approximation made to fit existing data, then it would be better to use the raw data as the basis for your lookup table. >> A lookup table with linear interpolation much easier to make accurately >> than a large polynomial like this. You could also compromise and use a >> lookup table and quadratic or cubic interpolation to get more accuracy >> from a smaller table. > > I never facing a problem like this until now. so I do not know where > to begin to implement this technique. > Wikipedia is a reasonable starting point: http://en.wikipedia.org/wiki/Cubic_spline http://en.wikipedia.org/wiki/Cubic_Hermite_spline >> Another idea, if your maths is up to it, is to use Chebyshev polynomials >> instead of powers of x. You would need more multipliers (18 for a ninth >> power polynomial, if I've done my sums right) and more adders, but all >> your partial calculations and coefficients are on the same scale making >> it much easier. >> >> http://en.wikipedia.org/wiki/Chebyshev_polynomials > > No. I can not. I have to save as much resources as possible. > You might need more multipliers for Chebyshev, but they will (should!) be narrower than you would need for your Horner's method polynomial with a given accuracy. Maybe you'll end up with less resources overall.Article: 142809
FPGA's are not processors, so FPGA's are not "programmed" by a language per se. They are designed, and the design is specified using a schematic or a language, usually verilog or vhdl. "Programming" an fpga usually refers to downloading the design configuration data into the FPGA (i.e. via the JTAG port you mentioned. The FPGA and/or board vendor will provide utilities to "program" the FPGA with your design configuration data. The design configuration data is created by tools that read your design description (schematic or language-based), synthesize a netlist of various resources, and then optimally place and route those resources within the FPGA chip's architecture. With a lot of money for some high-dollar tools, it is possible to synthesize an FPGA design from a description written in the C language. Then you place and route that synthesized netlist using the FPGA vendor's tools (some available for free). But for starters, I would strongly recommend using an HDL like verilog or vhdl, and of those two, I recommend vhdl. Both are supported by the FPGA vendors' free design tools. AndyArticle: 142810
Hi Brain, > There are any number of ways to implement it; as Jonathan said your pipelined > implementation is easy and cheap (though you will inevitably lose resolution > through the successive multiplications; see below) I already have been realized and tested. It's works very well, better than what I expected, but it very expensive resource. > His suggestion of interpolation is good, though I tend to add a quadratic term > to guarantee accuracy (this requires three multiplications rather than one; but > is accurate enough for single precision floating point; i.e. 24-bit or better > accuracy, on square root, reciprocal, etc) It would be perfect, the problem is that I do not know the technique. > Or if you prefer a direct implementation, consider the range of coefficient > values for your higher order terms; they are typically small. Consider the > rounding error imposed by truncating the product of x and the largest > coefficient; you can reduce the resolution of the smaller multiplications until > they introduce a similar (preferably still smaller) error with economic benefits > (reduced resources) I'd rather save resources instead of direct implementation. It must be mentioned that the coefficients will be changed at runtime, will not be fixed. I must be able to move without risk of overflow or underflow. > Or if latency is important, note that the slowest path, > a9 * x^9 = (a9 * x) * ((x*x) * (x*x)) * (ditto) > which takes 4 cycles to compute; plus a fifth to add it to the (parallel > computed) sum of the faster paths. (Implementation issues may require additional > cycles to move data between multipliers) This is not a problem. Now direct form working until 125 MHz. > Only you can determine if the loss of resolution due to e.g. truncating > multiplier outputs,or economising on word widths is acceptable; i.e. within your > error budget. Here I agree, for now I am more interested in a model that saves resources. > But for prototyping the algorithm and testing e.g. the accuracy of an > interpolated LUT, I suggest starting with a simple spreadsheet! You can truncate > values to 16 (or 19) bits and quickly investigate tradeoffs to get a pretty good > idea of what you are doing before moving to VHDL. I am always rushed and I can not wait to see the result after I realize that a whale never enters the backside of a mouse ... :-) ... Thanks. Kappa.Article: 142811
On Sep 2, 10:10=A0am, "liyiyiyam" <liyiyi_...@126.com> wrote: > Hi, > > I get these errors when trying to grasp output datas using chipscope from > > ERROR:Pack:1564 - The dual data rate register ODDR_INST failed to join > the > OLOGIC component as required. =A0The output signal for register symbol > ODDR_INST requires general routing. > > If I directly implement the disign without the function of chipscope, the= n > I dont get these errors. Once adding the chipscope,then I got the errors. > > Could anyone explain me this error, or maybe suggest another design? > > thanks You can't directly monitor pin nets in ChipScope. If you want to see the value at the pin, the best you can do is monitor the input signal after the IBUF from that pin. The output net of the ODDR flip-flop can only drive the OBUF to the pin. If your design already has feedback from the pin (i.e. it is an inout or bidir pin in the design), you should have an input net you can tie to ChipScope. Otherwise you may need to change the pin to an inout, then instantiate or infer the input buffer. If the input buffer only goes to ChipScope, you'll need a KEEP attribute on the net to prevent it being ripped out before you can attach it using the ChipScope inserter. HTH, GaborArticle: 142812
On Wed, 2 Sep 2009 07:30:48 -0700 (PDT), Kappa wrote:
>> Consider this, though. Suppose you make a 1024-entry table. Use
>> the top 10 bits of your 18-bit data to address into the table.
>> Use the lower 8 bits for linear interpolation.
>
>This technique is not very clear to me ... can get more details?
OK, so here's an example. Suppose I have 5-bit input data,
and I want to calculate X^2. But I don't have enough space
for a 32-entry lookup table. So I split my 5-bit data
into 3+2 bits, and I use the upper 3 bits to index this
table, in which each entry contains two values - the
function of the index, and its first difference. The
first difference value is scaled by 4; we'll look at
that later.
index function first difference scaled by /4
0 0^2 = 0 ( 4^2 - 0^2)/4 = 4
1 4^2 = 16 ( 8^2 - 4^2)/4 = 12
2 8^2 = 64 (12^2 - 8^2)/4 = 20
3 12^2 = 144 (16^2 - 12^2)/4 = 28
etc, etc, etc
OK, now let's suppose I want to use this to compute
11^2. So I take the value 11 in 5-bit binary: 01011.
The top 3 bits are 010. The lower 2 bits are 11.
Use the top 3 bits to look up in the table:
function = 64, first difference = 20
Next, I take the lower 2 bits (11 binary) and multiply them
by the first difference (20), giving 60. Now add together
the function value from the table, and the value I just
calculated: 64+60=124. The correct answer is 121. Not
a very large error.
So, what about the scaling? We have split the number
into two parts - you can think of them as 3-bit integer
and 2-bit fraction, if you like. The integer part
is used to look up in the table. The 2-bit fraction,
multiplied by the first differences (gradient of the
function), completes the correct value. Because the
fraction has 2 bits, the (first differences * fraction)
needs to be divided by 4 before the addition.
I hope this makes sense. It's fairly easy to write this
in a more rigorous mathematical style, but I though the
informal description might be more accessible.
>I'm realizing Digital Predistortion. With 9 polynomial coefficients
>i'm doing the fitting function for the amplifier.
So the transfer function will be fairly smooth, and therefore
an interpolation technique will probably be OK.
What's more, as Andy said, it probably makes more sense to
describe the function as a lookup table rather than as
a polynomial.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 142813Hi, I am designing a circuit to calculate GF(233) multiplication. Where can I find a correct digital example or a GF calculator to check if my GF(233) multiplication is correct? Thank you. WengArticle: 142814
I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5 is loading the recovered clock signal with an apparent impedance of 50 ohms (measured by the voltage drop across a series resistor). This is dropping the voltage swing of the signal in half. We have tried a different input pin with no change. We then added a buffer with no change. The ucf for that input is: NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25; This is not happening to any of the other inputs from the SERDES. Any ideas as to what is going on?Article: 142815
On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2morrow@yahoo.com> wrote: >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5 >is loading the recovered clock signal with an apparent impedance of 50 >ohms (measured by the voltage drop across a series resistor). This is >dropping the voltage swing of the signal in half. We have tried a >different input pin with no change. We then added a buffer with no >change. The ucf for that input is: > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25; > >This is not happening to any of the other inputs from the SERDES. > >Any ideas as to what is going on? > Did you check the board schematics? This signal seems to be connected to the CPLD also which might be causing the issue you see. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 142816
On Sep 2, 8:20 am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 2, 4:21 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > On 9=D4=C21=C8=D5, =CF=C2=CE=E71=CA=B125=B7=D6, "Antti.Luk...@googlemai= l.com" > > > <antti.luk...@googlemail.com> wrote: > > > On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@goog= lemail.com" > > > > > <antti.luk...@googlemail.com> wrote: > > > > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wro= te: > > > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@= googlemail.com" > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com>= wrote: > > > > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk= ...@googlemail.com" > > > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > > > > who have the available wrapper? > > > > > > > > > > wau do you think its only the wrapper you need? > > > > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > > > > then think how likely is to get a free IP > > > > > > > > > > Antti > > > > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > > > > i only need this wrapper. > > > > > > > > 1) contact PLDA > > > > > > > 2) contact asics.ws > > > > > > > 3) write yourself > > > > > > > > Antti > > > > > > > PS look at your rating: > > > > > > > you have been rated 20 times, and the rating score is 1 out 5= , > > > > > > > means that.. [insert here....] > > > > > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > > > > > but if you have the IP, you would also have the wrapper.. > > > > > > > I have designed usb3.0 host controller sucessfully. but i need = verify > > > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 devi= ce.- Hide quoted text - > > > > > > > - Show quoted text - > > > > > > try using 1GbE setting for MGT wrapper, if you test with your own= test > > > > > IP it should work already > > > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > > > it doesn't work with PCIE GEN2 template. > > > > > Can it work with 1GbE template? why? > > > > writing a IP core is 10% of the work > > > sim testbench, verification ,FPGA testing, > > > test software, compliance testing, documentation > > > > make up the 90% > > > > are you asking i do that 90% for you? > > > for 50% share of your potential profits, I might..:) > > > or if you plan to open-source it, i also would help you > > > but if you want to cash-in i will not do your work > > > > hm.. but u are welcome to contact me in private, still > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > it is very easy for me write the wrapper. > > > i only want to know if the 1GbE template works for usb3.0 pipe PHY. > > if it very easy why dont you do it? > > Antti because it is too easy to do it, so he prefer to help some lower level engineer to train himself by doing something for free for him...Article: 142817
On Sep 2, 11:10=A0am, Muzaffer Kal <k...@dspia.com> wrote: > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com> > wrote: > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5 > >is loading the recovered clock signal with an apparent impedance of 50 > >ohms (measured by the voltage drop across a series resistor). This is > >dropping the voltage swing of the signal in half. We have tried a > >different input pin with no change. We then added a buffer with no > >change. The ucf for that input is: > > >NET "RX_CLK" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > >This is not happening to any of the other inputs from the SERDES. > > >Any ideas as to what is going on? > > Did you check the board schematics? This signal seems to be connected > to the CPLD also which might be causing the issue you see. > > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Yes, we are aware of that. We previously used AJ32 and had the same problem. We used it because it was the only global clock input available (ISE kept complaining about using that input for a clock source). If need be, we can isolate the CPLD and LED from that line (we removed the LED and got no change). We just tried rerouting that signal to the USER_CLK after removing the oscillator (X1). This greatly improved the signal quality, but requires a flying wire off of our mezzanine board to make the connection.Article: 142818
On Sep 2, 9:35 pm, kclo4 <alexis.ga...@gmail.com> wrote: > On Sep 2, 8:20 am, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 2, 4:21 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > On 9=D4=C21=C8=D5, =CF=C2=CE=E71=CA=B125=B7=D6, "Antti.Luk...@googlem= ail.com" > > > > <antti.luk...@googlemail.com> wrote: > > > > On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@go= oglemail.com" > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> w= rote: > > > > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk..= .@googlemail.com" > > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.co= m> wrote: > > > > > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.L= uk...@googlemail.com" > > > > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > > > > > who have the available wrapper? > > > > > > > > > > > wau do you think its only the wrapper you need? > > > > > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > > > > > then think how likely is to get a free IP > > > > > > > > > > > Antti > > > > > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > > > > > i only need this wrapper. > > > > > > > > > 1) contact PLDA > > > > > > > > 2) contact asics.ws > > > > > > > > 3) write yourself > > > > > > > > > Antti > > > > > > > > PS look at your rating: > > > > > > > > you have been rated 20 times, and the rating score is 1 out= 5, > > > > > > > > means that.. [insert here....] > > > > > > > > > there is no need for wrapper if you dont have the USB 3.0 I= P > > > > > > > > but if you have the IP, you would also have the wrapper.. > > > > > > > > I have designed usb3.0 host controller sucessfully. but i nee= d verify > > > > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 de= vice.- Hide quoted text - > > > > > > > > - Show quoted text - > > > > > > > try using 1GbE setting for MGT wrapper, if you test with your o= wn test > > > > > > IP it should work already > > > > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > > > > it doesn't work with PCIE GEN2 template. > > > > > > Can it work with 1GbE template? why? > > > > > writing a IP core is 10% of the work > > > > sim testbench, verification ,FPGA testing, > > > > test software, compliance testing, documentation > > > > > make up the 90% > > > > > are you asking i do that 90% for you? > > > > for 50% share of your potential profits, I might..:) > > > > or if you plan to open-source it, i also would help you > > > > but if you want to cash-in i will not do your work > > > > > hm.. but u are welcome to contact me in private, still > > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > > it is very easy for me write the wrapper. > > > > i only want to know if the 1GbE template works for usb3.0 pipe PHY. > > > if it very easy why dont you do it? > > > Antti > > because it is too easy to do it, so he prefer to help some lower level > engineer to train himself by doing something for free for him... not all things that look easy are ..well at least until you have done them and even then when done (easily) the way to them may not be as easy (and this is true in the case of the wrapper in question too..:) AnttiArticle: 142819
Well, Every input has to go from somewhere to get to where it needs to be, and the pcb traces, and the FPGA package are 50 ohm transmission lines. Once the signal gets to the IO pin, the receiver is ~ 8pF of capacitance, with respect to ground. I have no idea what the drive capability of the driver is. Have you simulated the signal integrity using the driver chip IBIS models, the trace lengths, and the termination chip IBIS models? I suspect that if you do that, you will see immediately that the ML507 doesn't violate the rules of physics, and may provide you with some insight why the signal amplitude is reduced. AustinArticle: 142820
In article <134260ba-aafa-4926-862f-38398b41027b@f20g2000prn.googlegroups.com>, Weng Tianxiang <wtxwtx@gmail.com> wrote: >Hi, >I am designing a circuit to calculate GF(233) multiplication. > >Where can I find a correct digital example or a GF calculator to check >if my GF(233) multiplication is correct? Are you actually working modulo the integer 233, or in the field with 2^33 elements, or in the field with 2^233 elements? It's probably the last of those three cases, in which case: what is the polynomial defining your field? Let's say it's x^233+x^97+x+1 Get hold of a Linux machine and install the 'pari-gp' package, define e=Mod(1,2) f=e*(x^233+x^97+x+1) X=Mod(x,ff) then you can multiply polynomials in X and check that you get the answer you expect. TomArticle: 142821
On 2 Sep, 15:34, Andy <jonesa...@comcast.net> wrote: ... > But for starters, I would strongly recommend using an HDL like verilog > or vhdl, and of those two, I recommend vhdl. Both are supported by the > FPGA vendors' free design tools. Verilog is closer to C and may thus be a little easier for the OP to learn. It's probably been covered many times but as a beginner myself it would be interesting to know why you recommend VHDL. Care to elucidate? JamesArticle: 142822
Antti <antti.lukats@googlemail.com> wrote: > Hi > Uwe, (and others) what should i do (how high to jump, etc) to get USB > Blaster officially supported by XC3sprog? > urjtat already supports it, and xc3sprog supports partially drivers > from urjag, so i think my plea isnt so complicated to fulfill? > and yes i can donate some usb gadgets to the xc3sprog developers, (or > to any one who adds the support) > hm, basically the offer is valid to any developers adding usb blaster > support to some open or closed software..:) > OpenOCD lacks usb blaster support as well, and i think some more jtag > software also... (sorry for the delay, I was on vacation) There are at several possibilities: - write the low level support driver yourself. No too hard if you look how the xc3sprog xpc-driver was ripped of the urjtag xpc-driver - lend me a USB Blaster and hope that I find time to write the driver - hope that I find time and that I write the the driver without the hardware. Feedback on some probably non-working intermediate step will be welcome. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142823
Thorsten Kiefer <toki78@gmx.net> wrote: > Hi, > I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the > Digilent USB/JTAG cable. > I find ISE 11.1 too slow under Windows, so I want to use it with Linux. > My question is : is it possible to program the FPGA under Linux ? > Xilprg is too old. Export from digilent is discontinued and not available > for Linux. > Are there any alternatives ? Did you try xc3sprog from sourceforge (the SVN version)? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142824
James Harris wrote:
> Verilog is closer to C and may thus be a little easier for the OP to
> learn.
Maybe, but it's harder to write C-like code
because variables are not completely safe.
-- Mike Treseler
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