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On Aug 22, 10:00=A0am, morp <mbox2...@gmail.com> wrote: > Hi, > > Has anyone here thought of an idea to make an fpga io to be serdes > capable, that said, capable of connecting to standards like, PCIe,SATA > et. al. for chip to chip connection (i.e not on cable). > > What could be the components inside the fpga? Any ideas? > > -Morp You can't make the FPGA I/O run faster than the published bit-rates, usually well below 1 Gbps. Chip to chip vs. over cable won't change this. Your best bet is to use an external PHY part that connects via a parallel bus to the cheap FPGA. Also you'll probably find you won't be able to run PCIe, or SATA chips slow enough to work around this from the other end. Sorry for the bad news, GaborArticle: 142626
On Aug 22, 10:00=A0am, morp <mbox2...@gmail.com> wrote: > Hi, > > Has anyone here thought of an idea to make an fpga io to be serdes > capable, that said, capable of connecting to standards like, PCIe,SATA > et. al. for chip to chip connection (i.e not on cable). > > What could be the components inside the fpga? Any ideas? > > -Morp If you want a low cost FPGA wiht SERDES, look at the Lattice devices. They brought out the first low priced line with SERDES and now the others are copying it. RickArticle: 142627
I want to use a spi config mode for the Virtex 5 and then use a serial daisy chain to config a Virtex 4. Looking at the V5 user guide I am pretty sure I can do this but could someone just confirm it? Thanks JonArticle: 142628
Hi, I've been wondering how to translate lvds drive to tmds, my application is chip to chip only, i.e tmds does not go through any cable etc. From altera fpga, the lvds (translated into tmds) goes to a tmds input chip. What could be a solution for this? thanks.Article: 142629
Hi Umair, with the RF frontend coming with the SFF SDR you can just tune to carrier frequencies between 200 MHz and 1000 MHz while the Broadcast stations are around 100 MHz. Nevertheless if you have questions with the SFF just post it Kind regards Stefan >Hi,..I want to make an FM broadcast receiver using Lyrtech SFF SDR Kit,..it >has RF module, data conversion module and signal processing module having >vertex 4 FPGA and a DSP chip, ...I am using Matlab/Simulink and System >Generator to make my models,..Can anybody help me with it that what exactly >i should be doing for making my receiver ,.... > >Secondly i have an FRS model with this kit ,..i have made some ammendments >to make it work as an FM broadcast receiver but it has some sections which >i have failed to understand.. I can provide the details with snapshots if >anybody is willing to help.. :( > >Umair > > >Article: 142630
On Aug 23, 4:12=A0am, "Niieg" <stefan.na...@kit.edu> wrote: > Hi Umair, > with the RF frontend coming with the SFF SDR you can just tune to carrier > frequencies between 200 MHz and 1000 MHz while the Broadcast stations are > around 100 MHz. > Nevertheless if you have questions with the SFF just post it > > Kind regards > =A0Stefan > > > > > > >Hi,..I want to make an FM broadcast receiver using Lyrtech SFF SDR > Kit,..it > >has RF module, data conversion module and signal processing module > having > >vertex 4 FPGA and a DSP chip, ...I am using Matlab/Simulink and System > >Generator to make my models,..Can anybody help me with it that what > exactly > >i should be doing for making my receiver ,.... > > >Secondly i have an FRS model with this kit ,..i have made some > ammendments > >to make it work as an FM broadcast receiver but it has some sections > which > >i have failed to understand.. I can provide the details with snapshots > if > >anybody is willing to help.. :( > > >Umair- Hide quoted text - > > - Show quoted text - ASFAIK the RF front is capable to work below 200mhz (i know it reads 200 in the manual) AnttiArticle: 142631
On Aug 23, 1:05=A0am, morp <mbox2...@gmail.com> wrote: > Hi, > > I've been wondering how to translate lvds drive to tmds, my > application is chip to chip only, i.e tmds does not go through any > cable etc. > From altera fpga, the lvds (translated into tmds) goes to a tmds input > chip. What could be a solution for this? > > thanks. there should be no reason to use TMDS on single board (without cable) if you need TMDS, its better and easier to use DVI transmit/receive IC Altera does not officially support TMDS at all and, TMDS uses DC-couped CML not LVDS signalling, so you can not use LVDS I/O for sure AnttiArticle: 142632
Hi Uwe, (and others) what should i do (how high to jump, etc) to get USB Blaster officially supported by XC3sprog? urjtat already supports it, and xc3sprog supports partially drivers from urjag, so i think my plea isnt so complicated to fulfill? and yes i can donate some usb gadgets to the xc3sprog developers, (or to any one who adds the support) hm, basically the offer is valid to any developers adding usb blaster support to some open or closed software..:) OpenOCD lacks usb blaster support as well, and i think some more jtag software also... AnttiArticle: 142633
I've developed a simple graphics controller: http://www.frank-buss.de/yagraphcon/index.html Currently it needs twice as much block RAM as the resolution requires, because the architecture is very simple, with two read ports and one write port. I've developed it to see how difficult it is to develop a graphics controller (it was easy, I needed about 3 days for it) and to test a new FPGA module. Maybe implementing a GPU core would be better, because then you can implement the graphics acceleration you need, instead of being restricted to the available functions and then it is possible to implement more complex functions, like triangle shading. And a fast external SRAM or SDRAM interface is missing, because internal block RAM of inexpensive FPGAs is too small for higher resolutions. BTW: are there any other interesting concepts than framebuffers? Many gaphics controller have text modes, but this is only a special case. Do you think it is possible to define a general functional graphics output device? E.g. you upload the function sqrt(x*x+y*y)<10=white and the FPGA evaluates this function for each x/y pair on the fly with pixel clock and shows a circle. But the calculation needs to be really fast, if you define multiple combined functions. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142634
On Aug 23, 6:53=A0pm, Frank Buss <f...@frank-buss.de> wrote: > I've developed a simple graphics controller: > > http://www.frank-buss.de/yagraphcon/index.html > > Currently it needs twice as much block RAM as the resolution requires, > because the architecture is very simple, with two read ports and one writ= e > port. I've developed it to see how difficult it is to develop a graphics > controller (it was easy, I needed about 3 days for it) and to test a new > FPGA module. Maybe implementing a GPU core would be better, because then > you can implement the graphics acceleration you need, instead of being > restricted to the available functions and then it is possible to implemen= t > more complex functions, like triangle shading. And a fast external SRAM o= r > SDRAM interface is missing, because internal block RAM of inexpensive FPG= As > is too small for higher resolutions. > > BTW: are there any other interesting concepts than framebuffers? Many > gaphics controller have text modes, but this is only a special case. Do y= ou > think it is possible to define a general functional graphics output devic= e? > E.g. you upload the function sqrt(x*x+y*y)<10=3Dwhite and the FPGA evalua= tes > this function for each x/y pair on the fly with pixel clock and shows a > circle. But the calculation needs to be really fast, if you define multip= le > combined functions. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de did you check the genode-FX? they have full gui and graphics library support also, all free to use AnttiArticle: 142635
Antti.Lukats@googlemail.com wrote: > did you check the genode-FX? > > they have full gui and graphics library support also, all free to use Thanks, the high-level part is interesting. But I have browsed the VHDL files and it seems that they don't implement any graphics acceleration, except fast screen clear, and it is a standard framebuffer concept, but still very complete with the software graphics library. Drawbacks are, that it is available as GPL or commercial, only and very Xilinx specific. My system is BSD, which might be better for small commercial projects and should work on FPGAs from other vendors, too. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142636
Greetings, I'm currently trying to "get into" VHDL. Bought a few books for a start. Now, I feel it is time to get one of those starter kits to try out the examples from the books. Hence my question: can anyone recommend a "good" starter kit? My criteria so far (please suggest others): - should suffice for implementing up to a 32-bit CPU core (e.g. MIPS-alike) - Linux-based development (also Windows, but I guess that goes without saying) - "hip" (i.e. not obsolete) - easy/quick to obtain (I'm in Germany) - low cost - good educational value (I'm planning on using it for teaching later) Many thanks for your suggestions! Best regards RobArticle: 142637
Robert Kaiser (FH) wrote: > I'm currently trying to "get into" VHDL. Bought a few books for a start. > Now, I feel it is time to get one of those starter kits to try out the > examples from the books. Hence my question: can anyone recommend a "good" > starter kit? My criteria so far (please suggest others): > > - should suffice for implementing up to a 32-bit CPU core (e.g. MIPS-alike) > - Linux-based development (also Windows, but I guess that goes without > saying) > - "hip" (i.e. not obsolete) > - easy/quick to obtain (I'm in Germany) > - low cost > - good educational value (I'm planning on using it for teaching later) For Germany this shop has some nice boards: http://shop.trenz-electronic.de/catalog/ Use one from Xilinx, if you want to use Linux, because I didn't manage to run the Altera IDE (Quartus) on Linux with Wine. There is a commercial version of Quartus which runs on Linux, but it is expensive. If you use Windows, it doesn't matter which vendor you use. Quartus is a bit easier to use, but the Xilinx has improved ISE, too, compared to versions some years ago. If you want some low-cost system, take a look at this page: http://shop.trenz-electronic.de/catalog/default.php?cPath=1_48 But maybe it is not "hip" :-) For a hip board, take a look at this board: http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html You can buy it online in the Altera shop, no problem from Germany. There are some daughter boards available. The right ones depends on what you want to do with it. I've bought this one, for general purpose development, because it is very difficult to use the HSTC connector without an adapter: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=322 -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142638
On Aug 22, 4:58=A0pm, green <atgree...@gmail.com> wrote: > On Aug 16, 5:51=A0am, "Antti.Luk...@googlemail.com" > > <antti.luk...@googlemail.com> wrote: > > YES, there is no need to point to the "usual suspects" > > unless there is a real feeling, i have missed something obvious. > > I've been working on a new `Free Software' soft core, but backwards. > The gcc/binutils/gdb/simulator ports are already in the upstream FSF > repositories. =A0I also have a qemu port and uClinux has just started to > boot on the simulator. Interesting - how fast is the simulator ? > It's a 32-bit load/store architecture. =A0Most instructions are 16-bits, > but it also has 48-bit instructions for dealing with 32-bit immediate > values. =A0I think this is fair trade-off that should result in compact > code. =A0The ISA was designed specifically to be an excellent target for > GCC, although it still need tweaking (I've blogged all the details). Be interesting to see how this pathway fits on FPGA. In FPGA cores, you'll find things like 18 bit opcodes, as that is the width of block ram. More recent FPGA cores also target the dual-port memory blocks that most new FPGA's now include, but few I've seen also context switch that memory. - ie given that the memory-block is often larger than any core register set needs, switching within that for fast interrupts, or even hard time-slicing better uses HW that is 'almost free' -jgArticle: 142639
On Aug 23, 11:39=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Robert Kaiser (FH) wrote: > > I'm currently trying to "get into" VHDL. Bought a few books for a start= . > > Now, I feel it is time to get one of those starter kits to try out the > > examples from the books. Hence my question: can anyone recommend a "goo= d" > > starter kit? My criteria so far (please suggest others): > > > =A0- should suffice for implementing up to a 32-bit CPU core (e.g. MIPS= -alike) > > =A0- Linux-based development (also Windows, but I guess that goes witho= ut > > saying) > > =A0- "hip" (i.e. not obsolete) > > =A0- easy/quick to obtain (I'm in Germany) > > =A0- low cost > > =A0- good educational value (I'm planning on using it for teaching late= r) > > For Germany this shop has some nice boards: > > http://shop.trenz-electronic.de/catalog/ > > Use one from Xilinx, if you want to use Linux, because I didn't manage to > run the Altera IDE (Quartus) on Linux with Wine. There is a commercial > version of Quartus which runs on Linux, but it is expensive. If you use > Windows, it doesn't matter which vendor you use. Quartus is a bit easier = to > use, but the Xilinx has improved ISE, too, compared to versions some year= s > ago. > > If you want some low-cost system, take a look at this page: > > http://shop.trenz-electronic.de/catalog/default.php?cPath=3D1_48 > > But maybe it is not "hip" :-) For a hip board, take a look at this board: > > http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html > > You can buy it online in the Altera shop, no problem from Germany. > > There are some daughter boards available. The right ones depends on what > you want to do with it. I've bought this one, for general purpose > development, because it is very difficult to use the HSTC connector witho= ut > an adapter: > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&No..= . > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de just a forward statement, Trenz will have very soon S3ADSP low cost module in the shop I have seen the product photos, low cost connectors too :) Trenz may offer educational discounts too, please contact them about this AnttiArticle: 142640
On Aug 24, 3:32=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Aug 22, 4:58=A0pm, green <atgree...@gmail.com> wrote: > > > On Aug 16, 5:51=A0am, "Antti.Luk...@googlemail.com" > > > <antti.luk...@googlemail.com> wrote: > > > YES, there is no need to point to the "usual suspects" > > > unless there is a real feeling, i have missed something obvious. > > > I've been working on a new `Free Software' soft core, but backwards. > > The gcc/binutils/gdb/simulator ports are already in the upstream FSF > > repositories. =A0I also have a qemu port and uClinux has just started t= o > > boot on the simulator. > > Interesting - how fast is the simulator ? > > > It's a 32-bit load/store architecture. =A0Most instructions are 16-bits= , > > but it also has 48-bit instructions for dealing with 32-bit immediate > > values. =A0I think this is fair trade-off that should result in compact > > code. =A0The ISA was designed specifically to be an excellent target fo= r > > GCC, although it still need tweaking (I've blogged all the details). > > Be interesting to see how this pathway fits on =A0FPGA. > > In FPGA cores, you'll find things like 18 bit opcodes, as that is the > width > of block ram. > > More recent FPGA cores also target the dual-port memory blocks that > most > new FPGA's now include, but few I've seen also context switch that > memory. > - ie given that the memory-block is often larger than any core > register set needs, > switching within that for fast interrupts, or even hard time-slicing > better uses HW > that is 'almost free' > > -jg hi Jim, humm.. what IP core have you spotted doing context switch? I suppose there are some, NIOS-I used windowed register file (what could already be considered as context switch), my own ABM Risc uses ram-register context switch for subroutines and interrupts/thread, sure there must be others.. can you recall some? as of 18 bit, yes and no, for block RAM only, yes the 18 bits is very nice for 16 bit datapath, but for a SoC with external memory bus, a 18 bit core is nono and, even for block RAM's for true cross vendor, one should consider 16 bits only, as example Silicon Blue rams are 16 bit wide, not 18 AnttiArticle: 142641
On Aug 23, 8:59=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Antti.Luk...@googlemail.com wrote: > > did you check the genode-FX? > > > they have full gui and graphics library support also, all free to use > > Thanks, the high-level part is interesting. But I have browsed the VHDL > files and it seems that they don't implement any graphics acceleration, > except fast screen clear, and it is a standard framebuffer concept, but > still very complete with the software graphics library. Drawbacks are, th= at > it is available as GPL or commercial, only and very Xilinx specific. My > system is BSD, which might be better for small commercial projects and > should work on FPGAs from other vendors, too. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de yes, GPL is real bad thing, one latest example is OpenOCD project they can not distribute compiled binaries if those support FTDI drivers due to GPL restrictions. recompiling OpenOCD from sources for windows is sure possible but having precompiled version would make live much more easier well, GPL prevents that... AnttiArticle: 142642
Hello, Our project is to build a spectrometer, in which the FPGA is configured to perform autocorrelation. See: http://brsharath.googlepages.com/autocorr.jpeg to get an idea. (The difference in our project is the two signals from antenna 1 and 2 acome from the same antenna). The basic building block is a Delay- Multiply-Accumalate (DMAC) element. DMACs are aranged in a serial manner to perform n-channel autocorrelation. All the DMACs share a common clock. In terms of hardware requirement, the input digital data should be available to all the DMACs including the =93farthest DMAC=94. I am using Spartan 3A FPGA (XC3S400A) which can be clocked at a maximum of 320 MHz, and there is a provision of providing external clock. My question is : 1. Can the FPGA be easily clocked at 320 MHz using an external oscillator ? or Will I have to deal with serious =93data synchronization=94 issues since the signal is routed to the farthest DMAC ? If so, are there any methods to overcome the problem ? Thanks, SharathArticle: 142643
On Aug 24, 9:40=A0am, Sharath Raju <brshar...@gmail.com> wrote: > Hello, > > Our project is to build a spectrometer, in which the FPGA is > configured to perform autocorrelation. > See:http://brsharath.googlepages.com/autocorr.jpegto get an idea. > (The difference in our project is the two signals from antenna 1 and 2 > acome from the same antenna). The basic building block is a Delay- > Multiply-Accumalate (DMAC) element. DMACs are aranged in a serial > manner to perform n-channel autocorrelation. All the DMACs share a > common clock. > > In terms of hardware requirement, the input digital data should be > available to all the DMACs including the =93farthest DMAC=94. I am using > Spartan 3A FPGA (XC3S400A) which can be clocked at a maximum of 320 > MHz, and there is a provision of providing external clock. > > My question is : > 1. Can the FPGA be easily clocked at 320 MHz using an external > oscillator ? or > Will I have to deal with serious =93data synchronization=94 issues since > the signal is routed to the farthest DMAC ? If so, are there any > methods to overcome the problem ? > > Thanks, > Sharath very short: the design as in the picture will NOT work in S3a at 320 mhz clock. give up..! that is look for other solution other solution 1 you clock at 160mhz using DDR in the IOB, and build the datapath 2 times in parallel and double the data rate at the output IOBs again this would reduce the internal clock to 160mhz, what may be ok already AnttiArticle: 142644
-jg wrote: > On Aug 22, 4:58 pm, green <atgree...@gmail.com> wrote: >> It's a 32-bit load/store architecture. Most instructions are 16-bits, >> but it also has 48-bit instructions for dealing with 32-bit immediate >> values. I think this is fair trade-off that should result in compact >> code. The ISA was designed specifically to be an excellent target for >> GCC, although it still need tweaking (I've blogged all the details). > > Be interesting to see how this pathway fits on FPGA. > > In FPGA cores, you'll find things like 18 bit opcodes, as that is the > width > of block ram. > Taking advantage of the extra bit width in FPGA rams has advantages and disadvantages. 18 bits for your opcodes gives you significantly more opcode space, but it effectively limits you to onboard ram for your code, makes your development tools more complex (especially if you are aiming to re-use existing tools like gcc/binutils), and would be a pain if you want to be able to do insystem software updates. It might still be a win if you are looking for a tiny core (perhaps 9-bit rather than 18-bit). For comparison in the microcontroller world, the only cores I know of that use something other than a multiple of 8 for their basic opcode width are the PIC12 and PIC14 cores. These are 8-bit micros, limited to internal memory for code and using specialised toolchains. I don't know if the use of 12-bit and 14-bit wide ROM/flash saves them much money compared to 16-bit wide, but from the users' viewpoint it is not an advantage.Article: 142645
On Aug 24, 11:49=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Aug 24, 9:40=A0am, Sharath Raju <brshar...@gmail.com> wrote: > > > > > Hello, > > > Our project is to build a spectrometer, in which the FPGA is > > configured to perform autocorrelation. > > See:http://brsharath.googlepages.com/autocorr.jpegtoget an idea. > > (The difference in our project is the two signals from antenna 1 and 2 > > acome from the same antenna). The basic building block is a Delay- > > Multiply-Accumalate (DMAC) element. DMACs are aranged in a serial > > manner to perform n-channel autocorrelation. All the DMACs share a > > common clock. > > > In terms of hardware requirement, the input digital data should be > > available to all the DMACs including the =93farthest DMAC=94. I am usin= g > > Spartan 3A FPGA (XC3S400A) which can be clocked at a maximum of 320 > > MHz, and there is a provision of providing external clock. > > > My question is : > > 1. Can the FPGA be easily clocked at 320 MHz using an external > > oscillator ? or > > Will I have to deal with serious =93data synchronization=94 issues sinc= e > > the signal is routed to the farthest DMAC ? If so, are there any > > methods to overcome the problem ? > > > Thanks, > > Sharath > > very short: the design as in the picture will NOT work in S3a at 320 > mhz clock. > give up..! that is look for other solution >> Why ? Is it due to data synchronization or is it some other issue ? Plea= se explain. > > other solution 1 > you clock at 160mhz using DDR in the IOB, and build the datapath 2 > times in parallel > and double the data rate at the output IOBs again > > this would reduce the internal clock to 160mhz, what may be ok already > >> Why do you think that clocking at 160MHz is safe ? I shall check whether= the above solution is suitable for our application. Thanks! > AnttiArticle: 142646
On Aug 24, 10:37=A0am, Sharath Raju <brshar...@gmail.com> wrote: > On Aug 24, 11:49=A0am, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Aug 24, 9:40=A0am, Sharath Raju <brshar...@gmail.com> wrote: > > > > Hello, > > > > Our project is to build a spectrometer, in which the FPGA is > > > configured to perform autocorrelation. > > > See:http://brsharath.googlepages.com/autocorr.jpegtogetan idea. > > > (The difference in our project is the two signals from antenna 1 and = 2 > > > acome from the same antenna). The basic building block is a Delay- > > > Multiply-Accumalate (DMAC) element. DMACs are aranged in a serial > > > manner to perform n-channel autocorrelation. All the DMACs share a > > > common clock. > > > > In terms of hardware requirement, the input digital data should be > > > available to all the DMACs including the =93farthest DMAC=94. I am us= ing > > > Spartan 3A FPGA (XC3S400A) which can be clocked at a maximum of 320 > > > MHz, and there is a provision of providing external clock. > > > > My question is : > > > 1. Can the FPGA be easily clocked at 320 MHz using an external > > > oscillator ? or > > > Will I have to deal with serious =93data synchronization=94 issues si= nce > > > the signal is routed to the farthest DMAC ? If so, are there any > > > methods to overcome the problem ? > > > > Thanks, > > > Sharath > > > very short: the design as in the picture will NOT work in S3a at 320 > > mhz clock. > > give up..! that is look for other solution > >> Why ? Is it due to data synchronization or is it some other issue ? Pl= ease explain. > > > other solution 1 > > you clock at 160mhz using DDR in the IOB, and build the datapath 2 > > times in parallel > > and double the data rate at the output IOBs again > > > this would reduce the internal clock to 160mhz, what may be ok already > > >> Why do you think that clocking at 160MHz is safe ? I shall check wheth= er the above solution is suitable for our application. Thanks! > > Antti- Hide quoted text - > > - Show quoted text - 320MHz will not work 160MHz MAY work but you need to check this, even the 160mhz may be hard to achieve AnttiArticle: 142647
Dear all, Thank you so much for the fantastic responses - it really means a lot to a "noob" like myself :) > Frankly I'd just put down a DIP8 or DIP14 socket and buy a handful of oscillator > modules of different frequencies. Great - this sounds like the it will be the easiest to do in a DIY context ! Looks like this is what I'll try to do... > ... But then I'd start with a newer FPGA ... > ... DO NOT make any new board with Spartan-II - use s3a, nothing older .. > ... More importantly, do not start fresh with an obsolete design, go for > Spartan 3. ... Yup, I will let go of the Spartan-II :) I had already found Xilinx Spartan-3A Starter Kit Board Schematic http://www.xilinx.com/support/documentation/boards_and_kits/s3astarter_schematic.pdf But, the reason I wanted to go with a Spartan-II board: http://www.fpga.synth.net/evalboards/files/fes2_user.pdf was that, first, the fes2_user.pdf has a schematic which was a bit easier for me to read, so I counted on having an easier time selecting out elements I would not need; and another thing was, that I speculated that an older chip would be less sensitive to the imperfections of a DIY board, and therefore easier to get running. However, now I believe I will go after a Spartan 3 :) > We use the Cypress CY2292F and CY22392F chips. > ... Either chip requires programming, but they both > have three select inputs so you can have up to 8 frequencies > selectable by DIP switch. Definitely worth looking into - for some reason, when I typed "selectable output oscillator" (and variants) in the search engine, I never got a hit for these, so thanks for he tip :) Besides, I wrote to Epson regarding this MG-7010SA, and besides getting a confirmation that they are not produced anymore, I also got this: "The only programmable oscillators which we have are one time programmable i.e. at the factory, but the frequency can not be changed at the customer." So, unfortunately for us noobs, the definition of "programmable oscillator" can vary widely :) > It would be interesting to use a VCO and a trimpot. One could tease > the clock frequency to FPGA failure. There are lots of cheap-ish VCOs > with octave tuning range. > Or make your own, with a trimpot, capacitor, and a TinyLogic schmitt. > That might cover a decade. Very interesting - I also thought of making a RC VCO, but I thought I'd never be able to to tune the oscillator frequency to some stable value with a trimmer (even a 15-turn one), so I'd know what to enter as a clock frequency during programming (I'm assuming that is a step that must be done, if one wants to derive signals correctly timed in seconds ?!) But had no idea about the existence of VCO's with octave tuning range - thanks ! > Even more importantly: When you design and make your own multi-layer > pc board, you will struggle with, and hopefully learn many things, > like signal integrity, soldering of surface-mount components etc. You > need to master that before you even start designing the logic inside > the FPGA. I also have the feeling that I'd have to face these hardware issues before I even start with the logic - and I am even sort of looking forward to it :) However, my DIY ambition goes only toward making a (if possible) double layer, minimal circuit: > My advice: Buy a ready-made, populated and tested board for $50 to > 150, and save yourself a lot of grief and time. The thing is, when I started with microcontrollers, I really didn't feel confident about understanding them, until I built both a programmer cable, and a board. This time, I wanted to do the same - although I understand that the level of frustration with a DIY build to be expected is certainly greater here than if talking about microcontrollers ... But, I decided against building a programmer cable, mostly because I cannot get a hold of a parallel port that easily anymore (which is the only one I'd dare building myself; and unfortunately it seems current USB/parallel converters do not aim to fully emulate timings and such of the parallel port, so they cannot be used to interface to a parallel port programmer). Still, I feel that I should at least try to build a minimal board myself, and see if I can get it programmed and running a "hello world" (blinking led) on it - in order to get a better understanding of what is going on. In relation to a minimal circuit, I have seen this thread: Minimum circuit to get Spartan-3 running http://www.fpgarelated.com/usenet/fpga/show/24358-1.php and such attempts are discouraged there - but after all, in my case I'd like to start with a DIY minimal board, before I start considering a ready made development board.. Anyways - thanks again everyone for the fine answers, I definitely found them encouraging !! :) Cheers !! sdArticle: 142648
On Aug 24, 11:47=A0am, "sdaau" <s...@imi.aau.dk> wrote: > Dear all, > > Thank you so much for the fantastic responses - it really means a lot to = a > "noob" like myself :) > > > > > Frankly I'd just put down a DIP8 or DIP14 socket and buy a handful of > oscillator > > modules of different frequencies. > > Great - this sounds like the it will be the easiest to do in a DIY contex= t > ! Looks like this is what I'll try to do... > > > > > ... But then I'd start with a newer FPGA ... > > ... DO NOT make any new board with Spartan-II - use s3a, nothing older > ... > > ... More importantly, do not start fresh with an obsolete design, go > for > > Spartan 3. ... > > Yup, I will let go of the Spartan-II :) > > I had already found Xilinx Spartan-3A Starter Kit Board Schematichttp://w= ww.xilinx.com/support/documentation/boards_and_kits/s3astarte... > > But, the reason I wanted to go with a Spartan-II board:http://www.fpga.sy= nth.net/evalboards/files/fes2_user.pdf > > was that, first, the fes2_user.pdf has a schematic which was a bit easier > for me to read, so I counted on having an easier time selecting out > elements I would not need; and another thing was, that I speculated that = an > older chip would be less sensitive to the imperfections of a DIY board, a= nd > therefore easier to get running. However, now I believe I will go after a > Spartan 3 :) > > > We use the Cypress CY2292F and CY22392F chips. =A0 > > ... =A0Either chip requires programming, but they both > > have three select inputs so you can have up to 8 frequencies > > selectable by DIP switch. > > Definitely worth looking into - for some reason, when I typed =A0"selecta= ble > output oscillator" (and variants) in the search engine, I never got a hit > for these, so thanks for he tip :) =A0 > > Besides, I wrote to Epson regarding this MG-7010SA, and besides getting a > confirmation that they are not produced anymore, I also got this: > "The only > programmable oscillators which we have are one time programmable i.e. at > the factory, but the frequency can not be changed at the customer." > > So, unfortunately for us noobs, the definition of "programmable > oscillator" can vary widely :) > > > It would be interesting to use a VCO and a trimpot. One could tease > > the clock frequency to FPGA failure. There are lots of cheap-ish VCOs > > with octave tuning range. > > Or make your own, with a trimpot, capacitor, and a TinyLogic schmitt. > > That might cover a decade. > > Very interesting - I also thought of making a RC VCO, but I thought I'd > never be able to to tune the oscillator frequency to some stable value wi= th > a trimmer (even a 15-turn one), so I'd know what to enter as a clock > frequency during programming (I'm assuming that is a step that must be > done, if one wants to derive signals correctly timed in seconds ?!) But h= ad > no idea about the existence of VCO's with octave tuning range - thanks ! > > > Even more importantly: When you design and make your own multi-layer > > pc board, you will struggle with, and hopefully learn many things, > > like signal integrity, soldering of surface-mount components etc. You > > need to master that before you even start designing the logic inside > > the FPGA. > > I also have the feeling that I'd have to face these hardware issues befor= e > I even start with the logic - and I am even sort of looking forward to it > :) However, my DIY ambition goes only toward making a (if possible) doubl= e > layer, minimal circuit: > > > My advice: Buy a ready-made, populated and tested board for $50 to > > 150, and save yourself a lot of grief and time. > > The thing is, when I started with microcontrollers, I really didn't feel > confident about understanding them, until I built both a programmer cable= , > and a board. > > This time, I wanted to do the same - although I understand that the level > of frustration with a DIY build to be expected is certainly greater here > than if talking about microcontrollers ... But, I decided against buildin= g > a programmer cable, mostly because I cannot get a hold of a parallel port > that easily anymore (which is the only one I'd dare building myself; and > unfortunately it seems current USB/parallel converters do not aim to full= y > emulate timings and such of the parallel port, so they cannot be used to > interface to a parallel port programmer). > > Still, I feel that I should at least try to build a minimal board myself, > and see if I can get it programmed and running a "hello world" (blinking > led) on it - in order to get a better understanding of what is going on. = In > relation to a minimal circuit, I have seen this thread: > > Minimum circuit to get Spartan-3 runninghttp://www.fpgarelated.com/usenet= /fpga/show/24358-1.php > > and such attempts are discouraged there - but after all, in my case I'd > like to start with a DIY minimal board, before I start considering a read= y > made development board.. =A0 > > Anyways - thanks again everyone for the fine answers, I definitely found > them encouraging !! :) > > Cheers !! > sd sure can be fun! some years ago i got XC2V2000 FG898 from ebay at 49$ (CHEAP!!) placed it back down to a protoboard, added one diode-drop for 2.5V, a few caps, direkt wires to LPT port, connected to 3.3V supply and it worked well hm, or was it 1.8V down from 2.5, anyway the dirtcheap diode trick is not to be recommended AnttiArticle: 142649
Frank Buss <fb@frank-buss.de> wrote:
>Antti.Lukats@googlemail.com wrote:
>
>> did you check the genode-FX?
>>
>> they have full gui and graphics library support also, all free to use
>
>Thanks, the high-level part is interesting. But I have browsed the VHDL
>files and it seems that they don't implement any graphics acceleration,
>except fast screen clear, and it is a standard framebuffer concept, but
>still very complete with the software graphics library. Drawbacks are, that
>it is available as GPL or commercial, only and very Xilinx specific. My
>system is BSD, which might be better for small commercial projects and
>should work on FPGAs from other vendors, too.
Did you even look into a Yamaha VG9938? This chip has acceleration for
copying and line draw. AFAIK it is available as HDL source. There is
also a VG9958 which is better & faster. These chips where used in MSX
home computers.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
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