Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 142725

Article: 142725
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 12:22:27 -0600
Links: << >>  << T >>  << A >>

> That's the whole rationale for opencores.org.
> 
> Of course, if you've tried to use one of their cores, you quickly get
> annoyed by the lack of useful documentation.
> 

Thanks Andy.  Of course, a large amount of open source/Free Software 
doesn't have good documentation, but especially for research, it's nice 
to know that you can always use the same code again and again for your 
projects.

Article: 142726
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Andy Peters <google@latke.net>
Date: Fri, 28 Aug 2009 11:24:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 27, 1:57=A0pm, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello--
>
> I am trying to compare and contrast the differences between the
> freely-downloadable tools for FPGA development from the two largest
> vendors: Xilinx and Altera.
>
> What has always been puzzling for me is that there is often no easy way
> of determining if there is any IP available from the vendor for no
> additional charge.
>
> Since I am a researcher building circuits for research use there is
> little impetus for purchasing IP unless I really need it.
>
> For example, are there any SDRAM memory controllers available for gratis
> along with the freely downloadable development tools? =A0What about other
> types of controllers (i.e. NAND flash controller, etc).

Yes, there are memory controllers for NOR flash, SDR SDRAM, DDR and
DDR2 SDRAM, sync and async SRAM too.

However, it's worth noting that you get what you pay for. Some of the
memory controllers are horribly inefficient.

> In other words, I am looking for IP that I don't have to eventually
> purchase. =A0I can simply use the IP over the course of my development
> cycle and in the final circuit.

All of free Xilinx cores can be used without restrictions or licensing/
royalties, assuming of course that you use them on Xilinx devices. I
haven't used either Altera or Lattice in years but I would imagine
that their licensing is similar.

Xilinx offers other cores that are not free (as in beer).

The Xilinx home page has a nice big link titled "Intellectual
Property." You should start there.

-a

Article: 142727
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 12:41:24 -0600
Links: << >>  << T >>  << A >>

> 
> Yes, there are memory controllers for NOR flash, SDR SDRAM, DDR and
> DDR2 SDRAM, sync and async SRAM too.
>
> However, it's worth noting that you get what you pay for. Some of the
> memory controllers are horribly inefficient.
> 

Sadly this may be true.  But then again, perhaps some of them may be 
useful for my application.  How inefficient are these cores?  Speeds 
approaching 100MHz would be more than suitable for my project.

Are these cores easy to use?  I've never used Xilinx tools.  Would they 
simply involve running a wizard, and out pops some Verilog/VHDL code?

Have you heard about the Memory Interface Generator (MIG) from Xilinx? 
Does the MIG generate all of the code that is required for using SDRAM 
and other similar memories?


>> In other words, I am looking for IP that I don't have to eventually
>> purchase.  I can simply use the IP over the course of my development
>> cycle and in the final circuit.
> 
> All of free Xilinx cores can be used without restrictions or licensing/
> royalties, assuming of course that you use them on Xilinx devices. I
> haven't used either Altera or Lattice in years but I would imagine
> that their licensing is similar.
> 

I've been looking at the cores/megafunctions available in the Altera 
Quartus II software, and it appears some of the cores can be simulated, 
but not used in actual hardware.  There doesn't seem to be any good way 
to knowing exactly which of the cores will indeed work without 
additional licensing.


> Xilinx offers other cores that are not free (as in beer).
> 
> The Xilinx home page has a nice big link titled "Intellectual
> Property." You should start there.
> 

I've noticed that link, thanks, Andy!  I am assuming that all of the 
cores listed at

http://www.xilinx.com/ipcenter/coregen/11_2_datasheets.htm

are freely available for users of the Web Edition software?


Article: 142728
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 13:21:02 -0600
Links: << >>  << T >>  << A >>

> 
> I've noticed that link, thanks, Andy!  I am assuming that all of the 
> cores listed at
> 
> http://www.xilinx.com/ipcenter/coregen/11_2_datasheets.htm
> 
> are freely available for users of the Web Edition software?
> 

Um, my mistake - the cores are marked with a check mark if "Additional 
License Required."

The Memory Interface Generator (MIG) appears to be free for use along 
with a license.  I don't think that users of the Web Interface have to 
pay for the license, though.

So is the MIG all that is required to interface with the various types 
of SDRAM?

Thanks again for your help, Andy.

Article: 142729
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 13:24:19 -0600
Links: << >>  << T >>  << A >>

> The Memory Interface Generator (MIG) appears to be free for use along 
> with a license.  I don't think that users of the Web Interface have to 
> pay for the license, though.
> 
> So is the MIG all that is required to interface with the various types 
> of SDRAM?
> 

Perhaps another question now would be, "Does Altera have something 
similar to the MIG from Xilinx"?

Article: 142730
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 13:33:30 -0600
Links: << >>  << T >>  << A >>

> 
> Perhaps another question now would be, "Does Altera have something 
> similar to the MIG from Xilinx"?

...and I don't think so, since searching for IP in the Altera IP 
Megastore shows that there are only reference designs available for 
SDRAM, but not a freely-licensable SDRAM controller.

Here's a link to the IP Megastore from Altera:
http://www.altera.com/products/ip/ipm-index.html

Xilinx also has an IP search engine:
http://www.xilinx.com/ipcenter/index.htm

By searching for SDRAM on the Xilinx website, this shows the Memory 
Interface Generator:
http://www.xilinx.com/products/ipcenter/MIG.htm

So it appears that each company lists the cores/megafunctions which are 
available to license.  There is no guarantee that the software will tell 
you the licensing agreements.  These need to be found via the search 
engines for IP on either the Xilinx or Altera website.

Does the MIG from Xilinx generate everything that is required for SDRAM 
access?




Article: 142731
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 13:44:09 -0600
Links: << >>  << T >>  << A >>

> Does the MIG from Xilinx generate everything that is required for SDRAM 
> access?
> 

http://www.xilinx.com/products/ipcenter/MIG.htm

Th MIG from Xilinx is indeed a freeware tool - but is there something 
else that is required to work with SDRAM?  I don't think so; it appears 
that the MIG is standalone.



Article: 142732
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 13:55:42 -0600
Links: << >>  << T >>  << A >>
Nicholas Kinar wrote:
> 
>> Does the MIG from Xilinx generate everything that is required for 
>> SDRAM access?
>>
> 
> http://www.xilinx.com/products/ipcenter/MIG.htm
> 
> Th MIG from Xilinx is indeed a freeware tool - but is there something 
> else that is required to work with SDRAM?  I don't think so; it appears 
> that the MIG is standalone.
> 
> 

Yes again - the documentation for the MIG tool does indeed seem to 
produce everything that is required for SDRAM memory interfacing.  More 
efficient cores, however, would be available for purchase.

Article: 142733
Subject: sharing sdram and parallel nor flash address/data bus using xilinx
From: john1529 <monirk@gmail.com>
Date: Fri, 28 Aug 2009 13:40:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
The custom  board that I am working on has a SDRAM and parallel NOR-
FLASH, and they share the same address and data I/0 pins in the FPGA.
SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller.
Since they use different memory controllers I need to implement some
logic in order to multiplex signals that come from the controllers to
the external pins. Data buses are bidirectional which can only be
connected to the external pins. Is there any work (logic code) has
been done to share the same IO pins to access SDRAM and FLASH ? Any
suggestions will be very helpful to me in order to implement logic to
access both sdram and flash using a single bit file.

Article: 142734
Subject: Re: Is free-to-use IP included with downloadable FPGA tools?
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Fri, 28 Aug 2009 15:41:14 -0600
Links: << >>  << T >>  << A >>

> 
> So it appears that each company lists the cores/megafunctions which are 
> available to license.  There is no guarantee that the software will tell 
> you the licensing agreements.  These need to be found via the search 
> engines for IP on either the Xilinx or Altera website.
> 


In the Xilinx Core Generator, the software will tell you the licensing 
agreements in the "IP Catalog."  In particular, it appears that anything 
listed with a half-open lock symbol is available to simulate, but not to 
  work with in hardware.

The Memory Interface Generator (MIG) is not marked with the half-open 
lock symbol, so it does not appear to require any other licensing fee.

Article: 142735
Subject: Re: sharing sdram and parallel nor flash address/data bus using
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Fri, 28 Aug 2009 23:54:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 28, 11:40=A0pm, john1529 <mon...@gmail.com> wrote:
> The custom =A0board that I am working on has a SDRAM and parallel NOR-
> FLASH, and they share the same address and data I/0 pins in the FPGA.
> SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller.
> Since they use different memory controllers I need to implement some
> logic in order to multiplex signals that come from the controllers to
> the external pins. Data buses are bidirectional which can only be
> connected to the external pins. Is there any work (logic code) has
> been done to share the same IO pins to access SDRAM and FLASH ? Any
> suggestions will be very helpful to me in order to implement logic to
> access both sdram and flash using a single bit file.

inout buses can be split to _I _O _T and recombined as needed in EDK
but i am pretty sure you CAN NOT use SDRAM/mpmc and NOR/mch_emc
when address/data io pins are shared

mpmc assumes it can always start sdram cycle when needed, there is
no wait for ready signal for arbiter
and the mpmc requests may still be pending when nor controller wants
to acces the bus, so it would be conflicts..

BUMMER!

Antti


Article: 142736
Subject: Re: Mixed language simulation on the cheap
From: Alan Fitch <alan.fitch@spamtrap.com>
Date: Sat, 29 Aug 2009 16:28:03 +0100
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:
> I only speak VHDL.  Unfortunately, the memory interface generator in
> ISE 11.2 for Spartan-6 only speaks Verilog.  Specifically, the device
> models underneath are in the silly encrypted Verilog format, so I can't
> even go spelunking around.
> 
> So far, Modelsim XE Starter (free) has been sufficient for all my
> simulation needs.  In order to do mixed language simulation, however,
> I'd need to step up to Modelsim PE, which I just had quoted to me for
> slightly under $10K for a one year license.
> 
> All I really need it for is to simulate out my memory interface stuff;
> I have very little interest in adding lots of mixed language
> programming to my world.  And so ten kilobucks is really quite the
> chunk of change for solving one problem.
> 
> Does anyone know of any better solutions for mixed language
> simulation?  I had been thinking this would cost me somewhere in the
> $2K ballpark; at $10K I'd be better off sticking with "program and
> pray".
> 

Does this help?

http://www.xilinx.com/support/answers/33118.htm

regards
Alan
-- 
Alan Fitch
Doulos

Article: 142737
Subject: Does ModelSim or any simulator software have a function similar to
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sat, 29 Aug 2009 12:24:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
The standard function any logic analizer does is to set a trigger
condition and to set two numbers of sample data  before and after the
trigger condition in order to show the sample waveform window. By
doing things this way it saves a lot of memory for a logic analyzer,
because engineers are only interested in the signal wave window around
the trigger condition around which an error really happens.

Does ModelSim or any simulator software have the function similar to
the above standard function any logic analizer has?

Thank you.

Weng

Article: 142738
Subject: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 29 Aug 2009 21:07:38 +0100
Links: << >>  << T >>  << A >>
On Sat, 29 Aug 2009 12:24:17 -0700 (PDT), Weng Tianxiang wrote:

>The standard function any logic analizer does is to set a trigger
>condition and to set two numbers of sample data  before and after the
>trigger condition in order to show the sample waveform window. By
>doing things this way it saves a lot of memory for a logic analyzer,
>because engineers are only interested in the signal wave window around
>the trigger condition around which an error really happens.
>
>Does ModelSim or any simulator software have the function similar to
>the above standard function any logic analizer has?

Look up the "when" command in ModelSim.  It allows you to set up
fairly complex trigger conditions (much more complex than you
could do with a logic analyzer).  When the trigger fires, you
can execute a Tcl script that will start or stop logging of
signals to the waveform dump file.

I don't think you will find the "center trigger" feature
in a simulator.  The reason for this is that file storage
space (for waveform dumps) is cheap; it's logging the data
that is expensive.  So there's no special benefit in
having a pre-trigger buffer in the way you get in a logic
analyzer, where buffering is the limited resource.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 142739
Subject: Re: Does ModelSim or any simulator software have a function similar
From: KJ <kkjennings@sbcglobal.net>
Date: Sat, 29 Aug 2009 13:09:49 -0700 (PDT)
Links: << >>  << T >>  << A >>

>
> Does ModelSim or any simulator software have the function similar to
> the above standard function any logic analizer has?
>

Yes, they're called 'breakpoints'.

KJ

Article: 142740
Subject: low power FPGA
From: Amit <amit.kohan@gmail.com>
Date: Sat, 29 Aug 2009 15:11:11 -0700 (PDT)
Links: << >>  << T >>  << A >>

Hello group,

I'm about to do some study and work on lower power FPGA but totally
new to this topic. I am told that this topic is an architecture base
concept (I'm not sure yet) but what matters to me now is just finding
a source and learning about it.

Your help will be appreciated,

Regards,
amit


Article: 142741
Subject: Re: Does ModelSim or any simulator software have a function similar
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sat, 29 Aug 2009 16:41:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 29, 1:07=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sat, 29 Aug 2009 12:24:17 -0700 (PDT), Weng Tianxiang wrote:
> >The standard function any logic analizer does is to set a trigger
> >condition and to set two numbers of sample data =A0before and after the
> >trigger condition in order to show the sample waveform window. By
> >doing things this way it saves a lot of memory for a logic analyzer,
> >because engineers are only interested in the signal wave window around
> >the trigger condition around which an error really happens.
>
> >Does ModelSim or any simulator software have the function similar to
> >the above standard function any logic analizer has?
>
> Look up the "when" command in ModelSim. =A0It allows you to set up
> fairly complex trigger conditions (much more complex than you
> could do with a logic analyzer). =A0When the trigger fires, you
> can execute a Tcl script that will start or stop logging of
> signals to the waveform dump file.
>
> I don't think you will find the "center trigger" feature
> in a simulator. =A0The reason for this is that file storage
> space (for waveform dumps) is cheap; it's logging the data
> that is expensive. =A0So there's no special benefit in
> having a pre-trigger buffer in the way you get in a logic
> analyzer, where buffering is the limited resource.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
I have a project continuously running more than 20 days to get an
error. In my project I have many assert statements to make sure the
design is going well. If there is an error, the design stops.

But I couldn't open the waveform window under ModelSim when starting
the simulation, the reason is very simple: any size of hard disk would
be filled up within one day simulation.

I would like the ModelSim or other simulation software to have the
following function:
It has two windows to accept two numbers to specify how many clocks
before and after the point where assert statement fails to generate
waveform window data.

For example, 10k, 200. It means the software always keeps latest 10k
clocks of waveforms and when an assert statement fails, it continue
running for another 200 clocks and saves 10k+200 clocks of waveforms.

If ModelSim has the above function, it may be called breakpoint
function.

1. Start a project as usual;
2. Open waveform window and load its *.do file;
3. Set up Breakpoint window two numbers: number of clocks to record
waveforms before the break point and number of clocks to record
waveforms after the break point;
4. Run ModelSim with waveoform window opened and *.do file loaded;
5. When you manually stop its running or the running stops because an
assert statement fails, its shows latest waveforms of specified number
of clocks.

It execution in code is very simple:
1. Run as usual without drawing waveform window;
2. Generate waveform data into a buffer zone whose size is fixed based
on the two numbers;
3. When an assert statement fails, continue run another number of
clocks; then stop drawing waveform window with all collected data.

The differences between this method and currrent waveform window
method are:
1. The size of waveform data never grow beyond the size of specified
number of clocks.
2. When stopped manually or automatically (by failed assert
statement), it show the latest wavefors of specified number of clocks.

The above behavior exactly likes the logical analyser break point
function.

The method you mention cannot resolve my problem: if you figure out an
error condition in a when command, then start dumping data, there are
two situations:
1. If waveform window is opened and *.do file was loaded, hard disk
would have been full long before the error condition is met;
2. If it starts log waveform data, it is too later, because the
critical error situation has passed.

If I have any misunderstand, please let me know.

Thank you.

Weng

Article: 142742
Subject: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
From: "murlary@gmail.com" <water9580@yahoo.com>
Date: Sat, 29 Aug 2009 22:32:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@googlemail.c=
om"
<antti.luk...@googlemail.com> wrote:
> On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote:
>
> > who have the available  wrapper?
>
> wau do you think its only the wrapper you need?
> ask PLDA what their USB 3.0 IP cores costs
> then think how likely is to get a free IP
>
> Antti
> asics.ws also has usb 3.0 solutions i think

i only need this wrapper.

Article: 142743
Subject: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Sat, 29 Aug 2009 23:02:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wrote:
> On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@googlemail=
.com"
>
> <antti.luk...@googlemail.com> wrote:
> > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote:
>
> > > who have the available  wrapper?
>
> > wau do you think its only the wrapper you need?
> > ask PLDA what their USB 3.0 IP cores costs
> > then think how likely is to get a free IP
>
> > Antti
> > asics.ws also has usb 3.0 solutions i think
>
> i only need this wrapper.

1) contact PLDA
2) contact asics.ws
3) write yourself

Antti
PS look at your rating:
you have been rated 20 times, and the rating score is 1 out 5,
means that.. [insert here....]

there is no need for wrapper if you dont have the USB 3.0 IP
but if you have the IP, you would also have the wrapper..







Article: 142744
Subject: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Sun, 30 Aug 2009 08:48:23 +0100
Links: << >>  << T >>  << A >>

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:59730a19-3192-4625-97dc-491f71a5cfb9@p10g2000prm.googlegroups.com...
On Aug 29, 1:07 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
..
>Hi Jonathan,
>I have a project continuously running more than 20 days to get an
>error.

20 days in my book sounds totally unworkable, are you using an OEM version of 
Modelsim? In that case you might have hit the OEM limit and Modelsim will simply 
grind to a halt (1% of PE). If you explain what you are trying to do than you 
might get some useful suggestions on how to improve your simulation time.

>In my project I have many assert statements to make sure the
>design is going well. If there is an error, the design stops.
>
>But I couldn't open the waveform window under ModelSim when starting
>the simulation, the reason is very simple: any size of hard disk would
>be filled up within one day simulation.

You can also turn logging off (-nolog) for say the first 19 days and turn it 
back on again on day 20. You can also use the WLFSizeLimit  variable to limit 
the wlf file size (see manual/modelsim.ini).

>I would like the ModelSim or other simulation software to have the
>following function:
>It has two windows to accept two numbers to specify how many clocks
>before and after the point where assert statement fails to generate
>waveform window data.

That is a good option, log an Enhancement Request with Mentor. However, the 
WLFTimeLimit variable might be able to help you (not tried myself)

; Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
WLFTimeLimit = {100 ms}


Hans
www.ht-lab.com



Article: 142745
Subject: Re: low power FPGA
From: "Phil Jessop" <phil@noname.org>
Date: Sun, 30 Aug 2009 09:18:28 +0100
Links: << >>  << T >>  << A >>

"Amit" <amit.kohan@gmail.com> wrote in message 
news:fd878c01-f12c-48d3-997e-7fe570fbc111@u38g2000pro.googlegroups.com...
>
> Hello group,
>
> I'm about to do some study and work on lower power FPGA but totally
> new to this topic. I am told that this topic is an architecture base
> concept (I'm not sure yet) but what matters to me now is just finding
> a source and learning about it.
>
> Your help will be appreciated,
>
> Regards,
> amit
>

look at z series

http://www.altera.com/products/devices/cpld/max2/overview/mx2-overview.html



Article: 142746
Subject: Re: low power FPGA
From: "HT-Lab" <hans64@ht-lab.com>
Date: Sun, 30 Aug 2009 09:38:53 +0100
Links: << >>  << T >>  << A >>

"Phil Jessop" <phil@noname.org> wrote in message 
news:wdKdneMv5MtIqAfXnZ2dnUVZ8kmdnZ2d@brightview.co.uk...
>
> "Amit" <amit.kohan@gmail.com> wrote in message 
> news:fd878c01-f12c-48d3-997e-7fe570fbc111@u38g2000pro.googlegroups.com...
>>
>> Hello group,
>>
>> I'm about to do some study and work on lower power FPGA but totally
>> new to this topic. I am told that this topic is an architecture base
>> concept (I'm not sure yet) but what matters to me now is just finding
>> a source and learning about it.
>>
>> Your help will be appreciated,
>>
>> Regards,
>> amit
>>
>
> look at z series
>
> http://www.altera.com/products/devices/cpld/max2/overview/mx2-overview.html

or

http://www.actel.com/products/solutions/power/comparison.aspx
http://www.siliconbluetech.com/

Hans
www.ht-lab.com




Article: 142747
Subject: Re: program spartan3 under linux
From: Thorsten Kiefer <toki78@gmx.net>
Date: Sun, 30 Aug 2009 15:47:10 +0200
Links: << >>  << T >>  << A >>
Antti.Lukats@googlemail.com wrote:

> On Aug 28, 12:51 am, Thorsten Kiefer <tok...@gmx.net> wrote:
>> Hi,
>> I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the
>> Digilent USB/JTAG cable.
>> I find ISE 11.1 too slow under Windows, so I want to use it with Linux.
>> My question is : is it possible to program the FPGA under Linux ?
>> Xilprg is too old. Export from digilent is discontinued and not available
>> for Linux.
>> Are there any alternatives ?
>>
>> Best Regards
>> Thorsten
> 
> alternative:
> do not use Digilent [ ]
> Antti
> 
> I have some products with digilent on board usb and that doesnt work
> on windows either
> so i made a firm promise to me not to use the digilent cable whenever
> possible
> this doesnt include the XUP cable what is cloned xilinx platform
> cable, that one work
> as it is not designed by digilent

Hi,
thanks for the hint !
What FPGA vendor and development board would you suggest for
development on Linux ?

Best wishes
Thorsten



Article: 142748
Subject: Re: Does ModelSim or any simulator software have a function similar
From: gabor <gabor@alacron.com>
Date: Sun, 30 Aug 2009 06:57:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 3:48=A0am, "HT-Lab" <han...@ht-lab.com> wrote:
> "Weng Tianxiang" <wtx...@gmail.com> wrote in message
>
> news:59730a19-3192-4625-97dc-491f71a5cfb9@p10g2000prm.googlegroups.com...
> On Aug 29, 1:07 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
> ..
>
> >Hi Jonathan,
> >I have a project continuously running more than 20 days to get an
> >error.
>
> 20 days in my book sounds totally unworkable, are you using an OEM versio=
n of
> Modelsim? In that case you might have hit the OEM limit and Modelsim will=
 simply
> grind to a halt (1% of PE). If you explain what you are trying to do than=
 you
> might get some useful suggestions on how to improve your simulation time.
>
> >In my project I have many assert statements to make sure the
> >design is going well. If there is an error, the design stops.
>
> >But I couldn't open the waveform window under ModelSim when starting
> >the simulation, the reason is very simple: any size of hard disk would
> >be filled up within one day simulation.
>
> You can also turn logging off (-nolog) for say the first 19 days and turn=
 it
> back on again on day 20. You can also use the WLFSizeLimit =A0variable to=
 limit
> the wlf file size (see manual/modelsim.ini).
>

The problem with that is that it's not obvious that the wlf will
contain the most recent portion of the trace.  More likely it
contains from the time it was started until it got full.  What
you need, and what the logic analyzer has, is a ring buffer that
has a fixed size (up to your disk space limit) and starts
overwriting the oldest data when it hits that size.  I don't
think ModelSim has that now.  It would seem simple enough
to add, though.  The waveform viewer already deals with
lacking portions of the log, for example when you add signals
during the simulation run, you'll see "no data" until the
simulation time that the signal was added.

> >I would like the ModelSim or other simulation software to have the
> >following function:
> >It has two windows to accept two numbers to specify how many clocks
> >before and after the point where assert statement fails to generate
> >waveform window data.
>
> That is a good option, log an Enhancement Request with Mentor. However, t=
he
> WLFTimeLimit variable might be able to help you (not tried myself)
>
> ; Limit WLF file by time, as closely as possible,
> ; to the specified amount of simulation time. When the limit is exceeded
> ; the earliest times get truncated from the file.
> WLFTimeLimit =3D {100 ms}
>
> Hanswww.ht-lab.com


Article: 142749
Subject: Re: program spartan3 under linux
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Sun, 30 Aug 2009 07:34:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 4:47=A0pm, Thorsten Kiefer <tok...@gmx.net> wrote:
> Antti.Luk...@googlemail.com wrote:
> > On Aug 28, 12:51 am, Thorsten Kiefer <tok...@gmx.net> wrote:
> >> Hi,
> >> I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the
> >> Digilent USB/JTAG cable.
> >> I find ISE 11.1 too slow under Windows, so I want to use it with Linux=
.
> >> My question is : is it possible to program the FPGA under Linux ?
> >> Xilprg is too old. Export from digilent is discontinued and not availa=
ble
> >> for Linux.
> >> Are there any alternatives ?
>
> >> Best Regards
> >> Thorsten
>
> > alternative:
> > do not use Digilent [ ]
> > Antti
>
> > I have some products with digilent on board usb and that doesnt work
> > on windows either
> > so i made a firm promise to me not to use the digilent cable whenever
> > possible
> > this doesnt include the XUP cable what is cloned xilinx platform
> > cable, that one work
> > as it is not designed by digilent
>
> Hi,
> thanks for the hint !
> What FPGA vendor and development board would you suggest for
> development on Linux ?
>
> Best wishes
> Thorsten- Hide quoted text -
>
> - Show quoted text -

Using FPGA/tools with Linux (short version)
By Antti Lukats, August 2009

Option 1:
Get a PC with preinstalled WinXP/Vista and forget the attempts to use
FPGA tools under linux
This option saves lots of frustration and is worth the money spent

Option 2:
Get a PC with preinstalled WinXP/Vista, connect of FPGA hardware,
programming cables etc
and programming/debug software, download utility, on chip logic
analyzer, boundary scan tools, etc
to the win box
Use linux machine via shell scripts to run "vendor flow" synthesis,
P&R, etc

Option 3:
Be real DIE HARD Hero and do it all on single linux box

Yes, I know.. things can be made to work on linux, there
are plenty of success stories of how the heros have won
the battle and fixed xilinx cable driver issues under linux.
I know.

But if you want the ALL BUNDLE, meaning development
tools and utilities for 5 different FPGA vendors, + special
tools for 3rd parties, then you just have to have one win
box no matter how hard you may hate that solution.

for me its quite simple: some tools i use, just DO NOT exist for linux
or there is licensing problem under linux, or then there is known
hardware/driver problem under linux.
as I want and need tools for ALL vendors, i have no choice as
to have win box, be it slow, whatever, it works.

- end of story -

Thorsten, you CAN use any board under windows
just be prepared of trouble.. some of it you already tasted.

Xilinx USB cable, it sometimes works under linux, so
if you get it working then you can pretty much choose
any board you want.

but as long as you can get some jtag cable working
then no board wo do, well

http://www.demandperipherals.com/products.html

this is designed for linux
so if you can get FTDI drivers installed then that board
should work instantly

I am not recommending that board as it too expensive
for the features it has, but if some one really needs it
all to be done under linux, then that board would configure
over virtual uart

Antti

























































Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search