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> > So this is the chip you are using? > > http://www.atmel.com/dyn/resources/prod_documents/doc32015.pdf > Yes, that is the exact chip. Thank you so much for looking at the datasheet, Frank! > From the datasheet there are at least the following ports, which could be > used for communicating with the FPGA: > > - SRAM interface: Yes, the FPGA can behave like a SRAM. This is as simple > as accessing a SRAM from a FPGA, just the other way around > This is probably the best way to go because of the easy way of accessing the FPGA. > - SSC interface: With 150 MHz master clock, this works up to 75 MHz, so > should be fine for reading the ADCs > > I've used the SRAM interface with another system with a CPU and a FPGA. > From the CPU side this is the simplest communication way, because you just > write and read from memory locations. The FPGA gets the chipselect, decodes > the address and provides the data or reads in the data. Maybe DMA transfer > is possible, too. > Agreed. This is probably the easiest way to proceed. > SSC is another nice interface. I've used this in another Atmel chip (9g20) > with PDC transfer. This makes it really easy, compared to the usual DMA > setup procedure: You just setup the number of words you want to receive, > the address to which it should write and then it reads the SSC interface > and issues an interrupt when done. The drawback would be, that you are at > the limit with the speed for the SSC for 400 kHz for 8 ADCs, but it should > work. > I've never used the SSC interface, but it is certainly worth a try. > With SRAM you'll have lots of bandwith. Make sure to clock the FPGA with > the master clock, then you don't need to do edge detection and the like. > Maybe this works: Use block RAM for a small ringbuffer for the ADC and DAC > values, generate interrupts on FIFO thresholds and use the DMA on the CPU > side to transfer the data. SRAM PCB routing to the FPGA could be more > difficult than the SSC interface. > Yes, I think that SRAM is the way to go. The ringbuffer is really a neat idea and certainly something to try.Article: 142701
> > If I understand it correctly, you don't need to do some realtime > calculation for the DAC in response to the ADC? You just generate 1 s of > pre-calculated data at the DAC and at the same time read 1 s data from the > ADCs? > Yes, you are right about this, Frank. There is no realtime calculation required for the DAC output. (At least not for my system.) The input signal is a pre-generated Maximum Length Sequence (MLS), which could be either stored as a look-up table or generated using a Linear Feedback Shift Register (LFSR). Since the length of the MLS is (2^N - 1), where N is a number, the sequence length can grow quite quickly. So it is perhaps better to generate the MLS using a LFSR. I believe that this can be done quite easily with a FPGA. If N = 14, then 2^14 - 1 = 16383 is the length of the sequence. If there is SRAM or SDRAM attached to the FPGA, then perhaps this sequence could be generated before even sampling from the ADCs. The value of N could be much, much larger than just N = 14. Values of N = 20 or N = 25 may be used. The Maximum Length Sequence is produced by the DAC, and the output of the system is sampled using a number of ADCs. Since I initially made this post, I've reduced the number of ADCs from 8 to 6. So there are now only 6 ADCs in the system that I am designing. ******* Let me try and work out a plausible way of attaining what I want to obtain from this system. Does this sound like a logical way of proceeding? Could you suggest a FPGA for what I am trying to do? What should be the master clock speed? ******* Here are links to the datasheets for the ADC and the DAC: ADC: http://www.analog.com/static/imported-files/data_sheets/AD7690.pdf DAC: http://www.ti.com/lit/gpn/dac8580 Rather than using an ADC and DAC with parallel buses, I'm using parts with serial buses. What I am trying to do is reduce the PCB footprint so that I can fit 6 ADCs and 1 DAC on the same PCB. A similar ADC or DAC with a parallel bus would have a large number of pins. Each AD7690 has only 10 pins, whereas the DAC8580 has only 16 pins. -------------- (1) Use the FPGA to set up a 30 MHz clock, and initialize a counter. (2) The DAC, a Texas Instruments DAC8580, also operates with a 30 MHz serial clock. The first 16 rising edges of the 30 MHz clock are used to shift in a 16-bit voltage output word to the DAC. At the 17th rising edge of the clock, the voltage word has been passed by the DAC to a latch and the resulting voltage is produced on the output pin of the DAC. (3) On the 17th rising edge of the clock, have the FPGA trigger the /CONVERT pins of all 6 ADCs. All /CONVERT pins are triggered at the same time. (4) At least 10 ns after the /CONVERT pin has been triggered, the conversion result produced by each ADC should be available. If a pull-up resistor is placed on the MISO pin of each AD7690 ADC, the ADC will apparently drop the pin down low when the conversion data is available. (As shown in the datasheet, there are a number of other bus interfaces available.) Then the FPGA must apply a clock with at least a 15 ns period to the serial bus of each ADC to read out the 18-bit conversion result. Each 18-bit ADC is on a separate SPI bus attached to the FPGA. So all of the ADCs can be read at the same time. Reading all of the ADCs at the same time will take 2.7e-7 seconds, less than the 400 kHz sampling period of 2.5e-6 seconds. (5) The data from each ADC is transferred to SRAM or SDRAM for storage. (6) While data is being read from the ADCs, the 30 MHz clock on the FPGA is still ticking away, and the counter continues counting the rising edges of this clock. On the 75th rising edge of the clock, the counter is reset to zero. By this time, the data will have been read from each of the ADCs. Also on the 75th rising edge of the clock, the FPGA begins shifting in another word to the DAC. Since the counter has been reset to zero, on the 17th rising edge of the clock the /CONVERT pin is triggered again. The cycle then contines from (3) to (5) above. (7) For example, the conversion cycle continues for 1 second. This means, I think, that ((400000sps)(18 bits)(6 ADCs))/(8 bytes) = 5.4 MB of data has been accumulated. The data can then be read from the FPGA via the SRAM interface, SSC interface, as you have suggested. Or perhaps the master microcontroller could treat the FPGA as a slave SPI device. This would be significantly slower, I think, than the other methods that you have proposed.Article: 142702
On Aug 25, 5:45=A0pm, Fabian Schuh <xe...@nntp.xeroc.org> wrote: > icefish711 <icefish...@163.com> schrieb: > > > > > > > I am working on the EARP,xilinx using ISE9.1i02 and planahead9.2.7. I t= ried > > to designed a hard marco in Virtex2p and follow the guide book of xilin= x. > > But i have problem in my hard marco when implement the PAR,the error is > > below: > > > ERROR: Macro bm_base_prm is located incorrectly on a region boundary. > > =A0 =A0 =A0 =A0The external portion of the slice macro appears inside t= he region > > boundary. > > =A0 =A0 =A0 =A0The following external nets connect to slice macro bm_ba= se_prm but > > illegally cross the region boundary.Nets crossing region boundaries mus= t be > > defined in the slice macro. > > =A0 =A0 =A0 =A0 =A0 =A0 Net "dip_base_prm[0]" > > =A0 =A0 =A0 =A0 =A0 =A0 Net "dip_base_prm[1]" > > =A0 =A0 =A0 =A0 =A0 =A0 Net "dip_base_prm[2]" > > =A0 =A0 =A0 =A0 =A0 =A0 Net "dip_base_prm[3]" > > =A0Net dip_base_prm is the line between the dymatic moudle and hadr mar= co. > > It is very strangely that when I used xilinx's marco, it worked. But my > > hard marco is not work when all other's configuration is the same. > > > can anyone help out of this problem.Thanks. > > Can you post the relevant UCF section for the REGIONS and the LOC of your > macros? > > best regards > =A0-- Fabian Schuh Such problems arise due to improper placements of the macros. The macro must straddle across the module boundary and according to the error, it is not properly placed. Since you are using a custom hard macro, I would suggest you to go through the process of macro generation again and review the documentation to generate macro. Regards, MoazzamArticle: 142703
How would it be possible to set the FPGA up as an SSC bus slave? Is there a megafunction available for this type of bus?Article: 142704
Nicholas Kinar <n.kinar@usask.ca> wrote:
>Hello--
>
>I'm setting up a circuit where I need to write data to a DAC at the same
>time as read data from 8 ADCs.
>
>I need to shift a data word out to the DAC to set an output voltage. At
>the same time, I need to read data from each ADC.
>
>The DAC and the ADCs all communicate over SPI. The maximum sampling
>rate of each 18-bit ADC is 400 kHz. The maximum update rate of each
>16-bit DAC is 400 kHz, the same as the sampling rate as the ADC.
>
>Sampling from each ADC is triggered using a /TRIGGER pin. I believe
>that it is possible to daisy-chain the ADCs.
>
>Perhaps the best way to do this is to use a FPGA. I suppose that I
>would set up a separate SPI bus for each ADC and DAC, and separate /CS
>lines. All of the ADCs and DACs would not be on the same SPI bus.
I'd daisy chain the whole lot and use an LPC2000 series controller
from NXP. The 2nd SPI interface has a FIFO (both RX and TX) which is 8
words deep.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142705> I'd daisy chain the whole lot and use an LPC2000 series controller > from NXP. The 2nd SPI interface has a FIFO (both RX and TX) which is 8 > words deep. > Neat idea; I'll look into this. Thanks, Nico!Article: 142706
Nicholas Kinar wrote: > How would it be possible to set the FPGA up as an SSC bus slave? Is > there a megafunction available for this type of bus? I don't know, if there is a megafunction available for SSC. I've developed my own version. It is about 300 lines of VHDL code, provides SSC send and receive functions, with a protocol which provides a virtual RAM interface to other entities, checksum bits and with interrupt generation, if the a threshold is reached. It is for transfering continous multichannel audio samples up to 192 kHz in both directions. The other enties which are accessed by the SSC RAM interface are mainly ringubffers, but some other information can be requested with other virtual addresses. But it is closed source for a customer, so I can't publish it. But I would suggest to use SRAM, if you are in the designing phase of a board and if you can layout it, because then the protocol overhead is simpler and you can add some more ADCs later, if needed. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142707
Nicholas Kinar <n.kinar@usask.ca> wrote:
>
>>
>> So this is the chip you are using?
>>
>> http://www.atmel.com/dyn/resources/prod_documents/doc32015.pdf
>>
>
>Yes, that is the exact chip. Thank you so much for looking at the
>datasheet, Frank!
>
>
>> From the datasheet there are at least the following ports, which could be
>> used for communicating with the FPGA:
>>
>> - SRAM interface: Yes, the FPGA can behave like a SRAM. This is as simple
>> as accessing a SRAM from a FPGA, just the other way around
>>
>
>This is probably the best way to go because of the easy way of accessing
> the FPGA.
>
>
>> - SSC interface: With 150 MHz master clock, this works up to 75 MHz, so
>> should be fine for reading the ADCs
>>
>> I've used the SRAM interface with another system with a CPU and a FPGA.
>> From the CPU side this is the simplest communication way, because you just
>> write and read from memory locations. The FPGA gets the chipselect, decodes
>> the address and provides the data or reads in the data. Maybe DMA transfer
>> is possible, too.
>>
>
>Agreed. This is probably the easiest way to proceed.
You can make life much easier if the memory bus is synchronous (i.e.
has a clock to which all bus transactions are aligned).
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142708> > You can make life much easier if the memory bus is synchronous (i.e. > has a clock to which all bus transactions are aligned). > Will do; I'll make the bus synchronous. Thanks Nico!Article: 142709
> > I don't know, if there is a megafunction available for SSC. I've developed > my own version. It is about 300 lines of VHDL code, provides SSC send and > receive functions, with a protocol which provides a virtual RAM interface > to other entities, checksum bits and with interrupt generation, if the a > threshold is reached. It is for transfering continous multichannel audio > samples up to 192 kHz in both directions. The other enties which are > accessed by the SSC RAM interface are mainly ringubffers, but some other > information can be requested with other virtual addresses. But it is closed > source for a customer, so I can't publish it. Okay, 300 lines doesn't seem to be that bad. I'm not especially fluent in VHDL, but it might be possible to do this as well in Verilog. > > But I would suggest to use SRAM, if you are in the designing phase of a > board and if you can layout it, because then the protocol overhead is > simpler and you can add some more ADCs later, if needed. > Yes, I'll give SRAM a try. Thanks Frank!Article: 142710
Hi, I recently received a On-Demand Webinars email to watch Altera radar signal processing webcast. I did watched the show two times and found the webcast is valuable and impressive with input data rate 2.8GBS and output with 8 channels with each 350MSS. It asked me to do some further reading to understand its full processing. Today I searched On-Demand Webinars with keyword "Altera" and found there is no Altera radar signal processing webcast at all for 2009-2007. Anyone knows there it is, please post its website address. Thank you. WengArticle: 142711
Hello-- I am trying to compare and contrast the differences between the freely-downloadable tools for FPGA development from the two largest vendors: Xilinx and Altera. What has always been puzzling for me is that there is often no easy way of determining if there is any IP available from the vendor for no additional charge. Since I am a researcher building circuits for research use there is little impetus for purchasing IP unless I really need it. For example, are there any SDRAM memory controllers available for gratis along with the freely downloadable development tools? What about other types of controllers (i.e. NAND flash controller, etc). In other words, I am looking for IP that I don't have to eventually purchase. I can simply use the IP over the course of my development cycle and in the final circuit. I already know about the OpenCores website, where the IP is under a permissive license, but is there anything similar (if not open source) availble from from these two companies? Which IP is free to freely use by a user of the software? And moreover, how do I know it is free to use along with the downloadable tools from these companies?Article: 142712
Nicholas Kinar <n.kinar@usask.ca> wrote: (snip) < What has always been puzzling for me is that there is often no easy way < of determining if there is any IP available from the vendor for no < additional charge. < Since I am a researcher building circuits for research use there is < little impetus for purchasing IP unless I really need it. (snip) < In other words, I am looking for IP that I don't have to eventually < purchase. I can simply use the IP over the course of my development < cycle and in the final circuit. That is a good question, which I am also interested in. As far as I know, much of it is free as long as it is used with the vendors devices. It seems, though, that there are still complications distributing source code. That is, you can't necessarily (as far as I know) distribute the generated source, even if the recipient is allowed to use it. Especially not use it in open source projects. That seems to me to still be a problem in need of a solution. -- glenArticle: 142713
On Aug 27, 4:57=A0pm, Nicholas Kinar <n.ki...@usask.ca> wrote: > Hello-- > > I am trying to compare and contrast the differences between the > freely-downloadable tools for FPGA development from the two largest > vendors: Xilinx and Altera. > > In other words, I am looking for IP that I don't have to eventually > purchase. =A0I can simply use the IP over the course of my development > cycle and in the final circuit. > > Which IP is free to freely use by a user of the software? =A0And moreover= , > how do I know it is free to use along with the downloadable tools from > these companies? The easiest way to determine the free IP available is to download the free tool versions. With the tools, you should be able to access their IP Core builder program. The free of charge IP cores are easy to notice, because they are available to build. Unfortunately this doesn't work in all cases, as there are IP cores that require a license to be requested from the vendor even though the vendor will supply the IP core free of charge. Good luck, I'm interested in seeing what you find.Article: 142714
> > That is a good question, which I am also interested in. As far > as I know, much of it is free as long as it is used with the vendors > devices. It seems, though, that there are still complications > distributing source code. That is, you can't necessarily (as > far as I know) distribute the generated source, even if the > recipient is allowed to use it. Especially not use it in > open source projects. That seems to me to still be a problem > in need of a solution. > It would be really neat if someone was to start up a FPGA/CPLD company with completely open-source, free software IP. This still qualifies as IP, but with a permissive license which would qualify as "Free Software." In the real world, things are different. I would wonder if Xilinx or Altera provides freely-available controllers for SDRAM and other types of memory. For example, are these the plugins that ship with the freely-downloadable version of Altera's Quartus II? Are they free for general use by the user, or is a license fee ultimately required once the circuit is complete? I think it's okay to distribute your own source code under a permissive license, but then again, you would have to ensure that the chosen license also allows for integration of your code along with the proprietary IP. Perhaps the best way to proceed would be to distribute Verilog or VHDL code with a permissive MIT/BSD license, and have the user simply use IP distributed with the freely-downloadable software from the vendor's website.Article: 142715
> > The easiest way to determine the free IP available is to download the > free tool versions. With the tools, you should be able to access > their IP Core builder program. The free of charge IP cores are easy > to notice, because they are available to build. Unfortunately this > doesn't work in all cases, as there are IP cores that require a > license to be requested from the vendor even though the vendor will > supply the IP core free of charge. > > Good luck, I'm interested in seeing what you find. I've downloaded Quartus II Web Edition 9.0 to determine which cores are available from Altera. By choosing Tools->MegaWizard Plug-In Manager->Create a new custom megafunction variation it is apparent that there are a number of installed plugins under the headings, "Arithmetic," "Communications," "DSP," "Gates," "I/O", "Interfaces", "JTAG-accessible Extensions," "Memory Compiler," and "Storage." I've gone ahead and built the DDR2 SDRAM High Performance Memory Controller under the Interfaces->Memory Controllers group. The vendor is Altera. It builds without complaining. So does this mean that I am only allowed to evaluate it before purchase? Does this mean that the core is time-limited? Can I use this core in my final circuit without paying a license? Is it limited in any way?Article: 142716
Hi, I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the Digilent USB/JTAG cable. I find ISE 11.1 too slow under Windows, so I want to use it with Linux. My question is : is it possible to program the FPGA under Linux ? Xilprg is too old. Export from digilent is discontinued and not available for Linux. Are there any alternatives ? Best Regards ThorstenArticle: 142717
On Aug 28, 12:51=A0am, Thorsten Kiefer <tok...@gmx.net> wrote: > Hi, > I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the Digil= ent > USB/JTAG cable. > I find ISE 11.1 too slow under Windows, so I want to use it with Linux. > My question is : is it possible to program the FPGA under Linux ? > Xilprg is too old. Export from digilent is discontinued and not available > for Linux. > Are there any alternatives ? > > Best Regards > Thorsten alternative: do not use Digilent [ ] Antti I have some products with digilent on board usb and that doesnt work on windows either so i made a firm promise to me not to use the digilent cable whenever possible this doesnt include the XUP cable what is cloned xilinx platform cable, that one work as it is not designed by digilentArticle: 142718
Antti.Lukats@googlemail.com wrote: > On Aug 23, 11:39 pm, Frank Buss <f...@frank-buss.de> wrote: >> Robert Kaiser (FH) wrote: >> > I'm currently trying to "get into" VHDL. Bought a few books for a >> > start. Now, I feel it is time to get one of those starter kits to try >> > out the examples from the books. Hence my question: can anyone >> > recommend a "good" starter kit? My criteria so far (please suggest >> > others): >> >> > - should suffice for implementing up to a 32-bit CPU core (e.g. >> > MIPS-alike) - Linux-based development (also Windows, but I guess that >> > goes without saying) >> > - "hip" (i.e. not obsolete) >> > - easy/quick to obtain (I'm in Germany) >> > - low cost >> > - good educational value (I'm planning on using it for teaching later) >> >> For Germany this shop has some nice boards: >> >> http://shop.trenz-electronic.de/catalog/ >> >> Use one from Xilinx, if you want to use Linux, because I didn't manage to >> run the Altera IDE (Quartus) on Linux with Wine. There is a commercial >> version of Quartus which runs on Linux, but it is expensive. If you use >> Windows, it doesn't matter which vendor you use. Quartus is a bit easier >> to use, but the Xilinx has improved ISE, too, compared to versions some >> years ago. >> >> If you want some low-cost system, take a look at this page: >> >> http://shop.trenz-electronic.de/catalog/default.php?cPath=1_48 >> >> But maybe it is not "hip" :-) For a hip board, take a look at this board: >> >> http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html >> >> You can buy it online in the Altera shop, no problem from Germany. >> >> There are some daughter boards available. The right ones depends on what >> you want to do with it. I've bought this one, for general purpose >> development, because it is very difficult to use the HSTC connector >> without an adapter: >> >> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No... >> >> -- >> Frank Buss, >> f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de > > just a forward statement, Trenz will have very soon S3ADSP low cost > module in the shop > I have seen the product photos, low cost connectors too :) > Trenz may offer educational discounts too, please contact them about > this > > Antti Many thanks, Frank and Antti, for your suggestions. I purchased the GOP_XC3S200 Kit for a start and I'm doing my first steps now.. Does anyone know of a good hands-on quick start Tutorial on how to get the Xilinx WebKit going under Linux? Thanks! RobArticle: 142719
who have the available wrapper?Article: 142720
On Aug 28, 11:01=A0am, water <water9...@yahoo.com> wrote: > who have the available =A0wrapper? wau do you think its only the wrapper you need? ask PLDA what their USB 3.0 IP cores costs then think how likely is to get a free IP Antti asics.ws also has usb 3.0 solutions i thinkArticle: 142721
Nicholas Kinar <n.kinar@usask.ca> wrote:
>
>> I'd daisy chain the whole lot and use an LPC2000 series controller
>> from NXP. The 2nd SPI interface has a FIFO (both RX and TX) which is 8
>> words deep.
>>
>
>Neat idea; I'll look into this. Thanks, Nico!
You might need to parallel multiple SPI interfaces to get to your
required bit rate (one SPI interface as master, the other one as
slave; clock out externally connected to clock in). You can also look
into the LPC1700 series. These are even faster than the LPC2000
series.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142722Nico Coesel wrote: > Nicholas Kinar <n.kinar@usask.ca> wrote: > >>> I'd daisy chain the whole lot and use an LPC2000 series controller >>> from NXP. The 2nd SPI interface has a FIFO (both RX and TX) which is 8 >>> words deep. >>> >> Neat idea; I'll look into this. Thanks, Nico! > > You might need to parallel multiple SPI interfaces to get to your > required bit rate (one SPI interface as master, the other one as > slave; clock out externally connected to clock in). You can also look > into the LPC1700 series. These are even faster than the LPC2000 > series. > I am getting lots of good ideas from this particular thread. Thanks Nico! The LPC1700 series looks particularly good.Article: 142723
Now I'm in the process of downloading the ISE Webpack Edition from Xilinx. After logging into the Xilinx account, under Support->Product Download and Licensing there is the heading "Create a new license file." Under the heading there is a button which is marked "Add Evaluation and No Charge IP Cores to Product Table." Clicking on the button will bring up a list of evaluation and no-charge IP cores that are available for licensing. Some IIC and PCI Express licenses for particular FPGAs are available at no additional charge.Article: 142724
On Aug 27, 2:40=A0pm, Nicholas Kinar <n.ki...@usask.ca> wrote: > It would be really neat if someone was to start up a FPGA/CPLD company > with completely open-source, free software IP. =A0This still qualifies as > IP, but with a permissive license which would qualify as "Free Software." That's the whole rationale for opencores.org. Of course, if you've tried to use one of their cores, you quickly get annoyed by the lack of useful documentation. -a
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