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glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >austin <austin@xilinx.com> wrote: >< This is when once a key is programmed into the part, the part no >< longer will accept any bitstream, only a bitstream encrypted with that >< key (which we do not support today for any family). > >It seems that in that case, one could always replace the FPGA with >an unkeyed one. Yes the machinery for removing/installing BGA >devices is specialized, but if the desire is there it will be found. I assume that the intent is that when the bitstream is created in "match-the-FPGA's-efuse-key" mode, then that bitstream wouldn't work with a keyless FPGA. That would obstruct overbuilding and cloning even if the system could be accessed to copy the ROM -- *provided* that the FPGA key-programming was securely controlled, of course. The pirate would then have to resort to functional testing of the FPGA to recreate the original design. So an FPGA efuse key is a really good idea, and I think that Xilinx should hurry up and implement it, but I admit that I can understand the overheads that this would cause for Xilinx and that they are wary of it for all the reasons that Austin gave. And "Gandhi" does seem to be concerned about products like printers etc. where people would have access to the system. I was just a bit puzzled why he thought that the spec for a purely RAM-based FPGA was being misrepresented -- I mean, what is there to misunderstand? -- Dave FarranceArticle: 142351
wire [OUT_WIDTH-1:0] output; wire [15:0] temp; I want to assign temp to output assign output = temp; but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH > 16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth of output. What is the best way to do this? ThanksArticle: 142352
On Aug 5, 3:38=A0pm, "blak...@gmail.com" <blak...@gmail.com> wrote: > wire =A0[OUT_WIDTH-1:0] =A0output; > wire =A0[15:0] =A0 =A0 =A0 =A0 temp; > > I want to assign temp to output > > assign output =3D temp; > > but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH > > 16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth > of output. > > What is the best way to do this? > > Thanks Are you saying you want the output to have the upper bits of temp if WIDTH is less than 16? i.e. if WIDTH =3D 12: assign output =3D temp[15:4] + (|temp[3:0]); // high 12 bits plus roundingArticle: 142353
On Aug 5, 3:48=A0pm, gabor <ga...@alacron.com> wrote: > On Aug 5, 3:38=A0pm, "blak...@gmail.com" <blak...@gmail.com> wrote: > > > wire =A0[OUT_WIDTH-1:0] =A0output; > > wire =A0[15:0] =A0 =A0 =A0 =A0 temp; > > > I want to assign temp to output > > > assign output =3D temp; > > > but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH > > > 16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth > > of output. > > > What is the best way to do this? > > > Thanks > > Are you saying you want the output to have the upper bits of > temp if WIDTH is less than 16? =A0i.e. if WIDTH =3D 12: > > assign output =3D temp[15:4] + (|temp[3:0]); =A0// high 12 bits plus > rounding Yes you are right. But I want to sign extend if OUT_WIDTH is > 16 and round like you showed if OUT_WIDTH < 16 in a parameterized way. Can I combine these two operations?Article: 142354
First I'm very happy that my post is getting such input. Thank you. glen: >If it sells more hardware, even though the use is different, >it doesn't seem bad. Assuming that the hardware sale price >includes the price for the FPGA design, then it isn't likely >that someone will find an affordable use for the hardware. Maybe all are not in agreement on this. Many products are sold as loss-leaders and sold with very thin margins which are not good enuff for company to survive. The hardware platforms enable the company to sell soft intellectual property, songs, videos, iTunes, printer cartridges, DSP algorithms, video/audio processing algorithms, etc. A common misperception that selling more hardware for hobbyists to hack is good for the company when the company is making profit in different area. Hardware profits are margin thin in many markets, the soft IP is the item of value. The price point is chosen to enable the hardware to sell in more areas, the profit to be made by the purchase of the soft IP (which may not be part of hte product sold but plugged into the product - a game for instance, a movie for instance) by the customr of the product at a later time. If my company selling PCB which takes video in and does "face recognition" as hardware algorithm in FPGA, my company may take loss or break even on hardware to make market share with plan of selling updates of new face recognition method or new capability (higher resolution, better edge detection). >If someone copies the PCB, then sue for copyright infringement. This is an intellectual construct though isn't it rather than practical approach? gotta find copier, gotta find PCB is copied, hire lawyers, hire lawyers in native country (China?), dipose witnesses, get trial dates. Many years will go by and many $$ for company to spend with potnetial lost of market. Better for Design engineer to design in this insurance to prevent cloning, overbuilding, misuse of product or misuse of product in a way that is not in company best interest. >But absolutely in concurrence with Mr. Austin, it does not prevent >overbuilding,reverse engineering, cloning. However, the FPGA design that is encapsulated in the encrypted bitstream *is* secure. >agreed Mr. Dave Expecting it to protect the rest of the system is analogous to expecting that the firmware protection in your PC's disk drive should protect the firmware of your PC's graphics card. If you want to secure your system, then you need system security. >Very much agreed. I have similar conclusion. At first I thought AES encryption was security against these things as literature says it. But it is only the case if you plan on programming your own keys or have third party. http://www.altera.com/corporate/promotions/ads/a/stratix2a.html I read this paper and thought it was interesting. http://www.cl.cam.ac.uk/~sd410/papers/fpga_security.pdf System level solution is needed. FPGA vendors do the job they need to do, protect your design. no problem I think. System engineer has to design to protect against trojans, hacking, tampering across all FPGAs and configuration devices, but at same time enable functional test, jtag test and in-the-field secure updates. Probably this is all outside of FPGA vendor responsiblity and field. I just was under thought of 'common knowledge' AES encryption solves this and only recently through HOST and more research and your input learning that it is not enough, even for commercial product. or at least some risk in not designing in insurance. < 1) getting passwords from users/admin/embedded < 2) getting OTHER keys (not FPGA key) in system < 3) snoop system to hack and potentially unlock unpaid-for features < (turn low end product into high end product) < 4) learn enough about system to build compatible plug-ins (games, < software, songs, videos, printer cartridges) which < may not be part of economic strategy. Glen: Maybe, but are these really easier with a new bitstream attack? If one can float the I/O pins and put logic probes on the device, it might be about as easy. Otherwise, they are design failures of some kind. I do not have proof or evidence that it is easier (yet, I am searching google still). I know this: It is not easy to probe signals today directly. There is no physical access to probe. The signals are not TTL only. SERDES, SSTL etc, very speedy signals. Best way is to use FPGA that is present to capture? Use JTAG to access FPGA design which is snooping? < "cant prevent hardware from being used for other things" sounds < like simple statement but many hardware products are sold at < loss or break-even or very low margin in order to make < market share. Printers for example. Company makes money on < consumables or plug-ins to the platform. I have seen many printers that sell for less than the cost of the ink cartridges included. If someone can find a use for that printer, even not requiring any modifications, it would seem to be a loss to the manufacturer. > Correct. that is my point, so i take it this is agreement. >Youtube show how to turn printers into carving plotters, sign makers, >3d printers, x-y pen plotters, CNC drilling machine, etc. While I think that >is cool I like tinkering, I have to think about my company money success >company providing low-cost low-margin 'tinkering platform' and not intended money >maker in printer cartridges. Thisis just example, It is true for many products I think >money made elsewhere so 'open' hardware is not good for that company. Open >hardware is good like open source code but only when that is business model of >company. < Xbox is example - which is really just Intel PC sold at loss < to get market to sell games and internet service. Was Hacked < to run linux which is embarassment for Microsoft < but also a loss of $200 for each xbox purchased to run linux. As far as I know, there hasn't been a rush to buy them as linux systems. It may be $200 loss to MS, but it may still be more than it would cost to buy a similar PC. >where did u get the data? Linux-Xbox org is international http://en.wikipedia.org/wiki/Xbox_Linux http://www.xbox-linux.org/wiki/Main_Page Maybe misunderstand. MSFT sells Xbox at a LOSS, it is a PC for all practical purposes. So there is not a way to get a similar PC for less (no other manufacture making PCs at loss - at least intentionally) hence its attractiveness to break it out for linux by groups seeking low cost hardware. < Cisco low end router can be made into high end router with < hack patch - loss of revenue for Cisco. The software can check for some feature in the FPGA code. Otherwise, it is a normal software copyright question. >yes this gets to the point very well to illustrate. that feature maybe just a 'bit' to set to 1 or 0 >or maybe just a bitstream difference. If store 'plain' version bitstream in Virtex5 NOR flash >and send new bitstream 'super version' to store in second bitstream area of NOR flash, >very easy for one to read FLASH with JTAG and have second bitstream. Which then you >provide to other users of your product with just 'plain bitstram' via Internet. Not good I think. >encryption no help here unless you take trouble to program different key in each FPGA, >not easy/practical Well, there is a story about an IBM computer (I believe System/3) that came in 32K and 64K models, the difference was the position of a switch. People learned about this and turned the switch, but had to remember to turn it back when the machine was being serviced. (They were usually leased, not sold.) >good example this is same thing but for today PCB with FPGA. >don't let customer/internet hackers discover the 'figurative switch' In the case of the Cisco router, it would normally require different software (ROM) for the high end router. If someone can get that ROM contents, unencrypted FPGA code isn't likely to help, and it is a copyright violation in any case. See above, this is not good security approach to rely on copyright protection < Reader who say 'if simple to mimik then u don't need encryption, < engineer will build from scratch' maybe missing the point. They are to < build a bit data by scratch that is their intent, to have their design < in place to do bad things. steal user password (not fpga key), monitor < keyboard input, monitor USB connection, insert 'time bomb' to stop < system functioning at critical time of need. Possible, but how likely? The encrypted FPGA code stops (for this discussion) reverse engineering of that code. It doesn't stop one from removing the FPGA and splicing into the pads. In the case of password stealing, it doesn't stop one from making a similar looking box that steals passwords but with completely different content. > correct. Lots of ways to do it, this is just one of many. However, given > the choice of reprogramming a flash over JTAG and depop a 1152 ball >BGA, the jtag appraoch may be attractive. and easier than making different >PCB. Monitoring keyboard input or USB signals is much easier than writing new code for the FPGA. No-one will pick your expensive door lock if you leave the windows open. >Maybe harder to monitor keyboard or USB without dection of user >or remotely without physical access. I am thinking of FPGA based >system where keyboard or USB goes right to FPGA - so there it might >be attractive to load FPGA with design to capture the keystrokes. >Similar to running software program on Windows to spoof windows login >average user will ctrl-alt-delete and type in username/login, which program >just takes and records and then produces 'error'or logs off. Years ago colleagues >and I spoofed RS232 unix login and workers would enter username and password >just to show it could be done. No need to develop entire FPGA or entire software >just enough to get user to enter details. Many many ways to compromise >system if non-authenticated bitstream is present. < if I have embedded powerpc based fpga it maybe quiet easy for attacker < to get it to boot linux and have design which monitor keyboard input < for admin logins and store or send over internet. The interfaces are < all standard so easy to develop. If you can do that without access to the box, then it is a design failure. If I have access to the box, then there are too many other ways to attack the system. > Correct and we agree here too - design failure. But very common design >failure - updates over internet, JTAG and no security. identify it as design failure, >but that does not make it go away or solve the problem. If you google many many leading companies with this design failure so it is not say just the horrible engineer. good engineers on iPhone (not fpga) hacked with JTAG. >access to box is quite possible >and JTAG programming of flash is a very used method, so not sure why other methods >are considered first. China incident where US fighter had to land in China, much was >done to destroy documents, but consider hardware left behind like that, modified wiht >trojan and then given back to US. Not good. >commerical area is similar, voting machines, slot machines, routers (flash reprogrammed) thanks again everyone for input. i am going to try to learn more. Best Wishes, RajArticle: 142355
Rajesh Gandhi <rgandhi4086@gmail.com> wrote: (snip, I wrote) <>If it sells more hardware, even though the use is different, <>it doesn't seem bad. Assuming that the hardware sale price <>includes the price for the FPGA design, then it isn't likely <>that someone will find an affordable use for the hardware. < Maybe all are not in agreement on this. Many products are sold < as loss-leaders and sold with very thin margins which are not < good enuff for company to survive. In that case, there are other ways to do it. Grocery stores often use loss leaders, and limit the quantity to each customer to control it. They can't control what I do with the product after I get it home. I could, for example, feed it to my cat even though that wasn't what they expected. < The hardware platforms enable the company to sell soft intellectual < property, < songs, videos, iTunes, printer cartridges, DSP algorithms, video/audio < processing algorithms, etc. A common misperception that selling more < hardware for hobbyists to hack is good for the company when the < company is making profit in different area. Hardware profits are < margin thin in many markets, the soft IP is the item of value. The < price point is chosen to enable the hardware to sell in more areas, < the profit to be made by the purchase of the soft IP (which may not be < part of hte product sold but plugged into the product - a game for < instance, a movie for instance) by the customr of the product at a < later time. In most cases, the mass market software sells in large enough quantities to overcome a small side usage. If not, then a new business model is needed. Note that no grocery items are protected by AES, and yet they seem to be able to seel them and make a profit. < If my company selling PCB which takes video in and does < "face recognition" as hardware algorithm in FPGA, my company may take < loss or break even on hardware to make market share with plan of < selling updates of new face recognition method or new capability < (higher resolution, better edge detection). Say someone finds out that your product makes a good practice baseball. (Not likely, but just for now.) How can you stop people from buying it for that use? No encryption is likely to be able to do that. (Well, say a store sells apples as a loss leader. They might make good practice baseballs.) Personally, I believe that loss leaders make bad business practice, but I am happy to buy them and use them for other things. They might even violate trade laws. <>If someone copies the PCB, then sue for copyright infringement. < This is an intellectual construct though isn't it rather than < practical approach? < gotta find copier, gotta find PCB is copied, hire lawyers, hire < lawyers in native country < (China?), dipose witnesses, get trial dates. Many years will go by < and many $$ for < company to spend with potnetial lost of market. Better for Design < engineer to design in < this insurance to prevent cloning, overbuilding, misuse of product or < misuse of product in a way that is not in company best interest. I believe that you can stop it from being imported without doing so much work. Likely you can't stop sales in China, anyway. (snip, I wrote) < Maybe, but are these really easier with a new bitstream attack? < If one can float the I/O pins and put logic probes on the < device, it might be about as easy. Otherwise, they are design < failures of some kind. < I do not have proof or evidence that it is easier (yet, I am < searching google still). < I know this: It is not easy to probe signals today directly. < There is no physical access to probe. The signals are not TTL only. < SERDES, SSTL etc, very speedy signals. OK, but then how do you know what signals to put on any FPGA pin? If you unsolder the FPGA you can get to the pins. AES won't stop that. < Best way is to use FPGA that is present to capture? < Use JTAG to access FPGA design which is snooping? If you really don't know what pin goes where, it is unlikely that this will help. < < Xbox is example - which is really just Intel PC sold at loss < < to get market to sell games and internet service. Was Hacked < < to run linux which is embarassment for Microsoft < < but also a loss of $200 for each xbox purchased to run linux. < As far as I know, there hasn't been a rush to buy them as < linux systems. It may be $200 loss to MS, but it may still < be more than it would cost to buy a similar PC. <>where did u get the data? Linux-Xbox org is international < http://en.wikipedia.org/wiki/Xbox_Linux < http://www.xbox-linux.org/wiki/Main_Page How many are being used that way, compared to how many MS sells? < Maybe misunderstand. MSFT sells Xbox at a LOSS, it is a PC for < all practical purposes. So there is not a way to get a similar PC for < less (no other manufacture making PCs at loss - at least < intentionally) < hence its attractiveness to break it out for linux by groups < seeking low cost hardware. Buy used. Most likely less than a new Xbox. (snip) < Monitoring keyboard input or USB signals is much easier than writing < new code for the FPGA. No-one will pick your expensive door lock < if you leave the windows open. (snip) -- glenArticle: 142356
On Aug 5, 3:48=A0pm, gabor <ga...@alacron.com> wrote:
> On Aug 5, 3:38=A0pm, "blak...@gmail.com" <blak...@gmail.com> wrote:
>
> > wire =A0[OUT_WIDTH-1:0] =A0output;
> > wire =A0[15:0] =A0 =A0 =A0 =A0 temp;
>
> > I want to assign temp to output
>
> > assign output =3D temp;
>
> > but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH >
> > 16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth
> > of output.
>
> > What is the best way to do this?
>
> > Thanks
>
> Are you saying you want the output to have the upper bits of
> temp if WIDTH is less than 16? =A0i.e. if WIDTH =3D 12:
>
> assign output =3D temp[15:4] + (|temp[3:0]); =A0// high 12 bits plus
> rounding
How about:
assign output =3D (OUT_WIDTH < 16) ?
temp[15 -: OUT_WIDTH] + (|temp[0 +: 16-OUT_WIDTH])
: {{OUT_WIDTH-16{temp[15]}, temp};
Article: 142357blakaxe@gmail.com <blakaxe@gmail.com> wrote: > wire [OUT_WIDTH-1:0] output; > wire [15:0] temp; > I want to assign temp to output > assign output = temp; > but depending on OUT_WIDTH, I want to either sign extend(if OUTWIDTH > > 16 bits) or round(if OUT_WIDTH < 16 bits) temp to match the bitwidth > of output. > What is the best way to do this? What about assign output = $signed(temp[15:((15-OUT_WIDTH)<0)?0:(15-OUT_WIDTH)]; -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142358
Rajesh Gandhi wrote: > Hello, > > Is it possible that even though I use AES encrypted bitstream, another > trojan/bad bitstream that mimiked my design could be loaded into FPGA? > > Regards, > Raj Hi Raj, This whole discussion is moot if I find a guy in your MIS department and bung him $10k and a 6ft blonde with big lungs to give me the design files. HTH., Syms.Article: 142359
Hi Guys, I am doing a design in which a Micrel Gigabit ethernet phy is hooked up to a Spartan3A DSP using the GMII/MII interface. The transmit clock (GTX_CLK) in gigabit mode has to be sourced by the FPGA, but this signal becomes an input to the FPGA in the 10/100 mode. I would like to know what you be the best way to terminate this bi- directional signal on the PCB. I have looked at Xilinx ML405 dev and spartan 3A DSP dev kit schemetics, but both dont have any termination resistors. Cheers SudhirArticle: 142360
"Sudhir Singh" <Sudhir.Singh@email.com> wrote in message news:70bcd38e-19d7-4157-984d-4093191e615d@u16g2000pru.googlegroups.com... > Hi Guys, > I am doing a design in which a Micrel Gigabit ethernet phy is hooked > up to a Spartan3A DSP using the GMII/MII interface. The transmit clock > (GTX_CLK) in gigabit mode has to be sourced by the FPGA, but this > signal becomes an input to the FPGA in the 10/100 mode. > > I would like to know what you be the best way to terminate this bi- > directional signal on the PCB. I have looked at Xilinx ML405 dev and > spartan 3A DSP dev kit schemetics, but both dont have any termination > resistors. > > Can't you specify a default pullup in the UCF file so it's not left floating? Isn't it a 3.3V logic level so doesn't really need termination, unless it's trace is more than a few inches long?Article: 142361
Hello to everyone, I would like to as a simple question if anyone can help me. I am working on some project and I am using xilinx tools. I was wondering is there any posibility to use xilinx ise simulator for some easy and fast module check. I worked previosly wiht altera quartus simulator and their simulator and there was posibility to graphicly add values to the signal you simulate. it was very eays if you wnat fast to check some simple logic. wriiting a testbench to use modelsim simulation would took me for example 20 min and I could check this simple desing with 5 min if i could set those signals in ise simulator graphicaly. Is there maybe in modelsim some posibility to add signals graphicaly. thanks for answering ZoranArticle: 142362
On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote: > On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote: > >> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph >> <schvantzkoph@yahoo.com> wrote: >> >>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and >>>Altera FPGA tools? >> >> I'd also be very interested in Core7 vs Phenom II performance too (45nm >> AMD ie Phenom II 955 etc.) > > > We just got a new i7 machine for FPGA builds. It tested at just over > twice as fast as our high-end AMD box that was 2-3 years old. > > I will publish the results in this ng within a week or two, assuming I > can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx, > flexlm was a really good move.) It's been a week and we still can't get the Xilinx licensing working on the new machine, so I can't post any ISE11.2 results. I assume we will be able to get the licensing running soon, because I have told the local Xilinx reps that I won't be designing their parts into new products if we can't run the software. My last big design used an Altera FPGA, so they know I'm not joking. Here are the two machines: Old machine: AMD Phenom 9750 CPU 2.40GHz MSI K9A2-CD-F Motherboard (AMD 790X Chipset) 8GB Corsair TWIN2X2048-8500C5DF Xtreme CL5 DDR2 RAM (1066MHz) Windows XP Professional x64 Edition Version 2003 Service Pack 2 New machine: Intel Core i7 Extreme Edition 975 CPU 3.33GHz Asus Rampage-II-Extreme Motherboard (Intel X58 Chipset) 12GB OCZ Platinum Low-Voltage Triple Channel CL7 DDR3 RAM (1600MHz), Windows Server 2003 R2 Standard x64 Edition Service Pack 2. Using ISE8.2 SP3 (yes, 8.2) on an old test design that almost filled a medium sized fpga, we recorded a run time of 6 hours and 12 minutes for the older AMD machine, and 3 hours and 3 minutes for the new i7 machine. That's 2.03 times as fast. The runs contained XST, ngdbuild, map, par, etc. In both cases, the 32 bit version of software was used. Peak memory usage (during map) was just under 3GBytes. Map was run with the -speed option. Regards, AllanArticle: 142363
http://www.pldesignline.com/guest_blogs/219100182 After a long, and productive career, Peter is going to see to other things. He will be greatly missed here at Xilinx by all of us. I am sure you will join me in wishing him all the best. Now I am going to be greatly challenged to walk in his footsteps, and continue his tradition of excellence here at Xilinx. AustinArticle: 142364
On Thu, 06 Aug 2009 14:21:34 +0000, Allan Herriman wrote: > On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote: > >> On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote: >> >>> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph >>> <schvantzkoph@yahoo.com> wrote: >>> >>>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and >>>>Altera FPGA tools? >>> >>> I'd also be very interested in Core7 vs Phenom II performance too >>> (45nm AMD ie Phenom II 955 etc.) >> >> >> We just got a new i7 machine for FPGA builds. It tested at just over >> twice as fast as our high-end AMD box that was 2-3 years old. >> >> I will publish the results in this ng within a week or two, assuming I >> can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx, >> flexlm was a really good move.) > > > It's been a week and we still can't get the Xilinx licensing working on > the new machine, so I can't post any ISE11.2 results. I assume we will > be able to get the licensing running soon, because I have told the local > Xilinx reps that I won't be designing their parts into new products if > we can't run the software. My last big design used an Altera FPGA, so > they know I'm not joking. > > Here are the two machines: > > Old machine: > AMD Phenom 9750 CPU 2.40GHz > MSI K9A2-CD-F Motherboard (AMD 790X Chipset) 8GB Corsair > TWIN2X2048-8500C5DF Xtreme CL5 DDR2 RAM (1066MHz) Windows XP > Professional x64 Edition Version 2003 Service Pack 2 > > New machine: > Intel Core i7 Extreme Edition 975 CPU 3.33GHz Asus Rampage-II-Extreme > Motherboard (Intel X58 Chipset) 12GB OCZ Platinum Low-Voltage Triple > Channel CL7 DDR3 RAM (1600MHz), Windows Server 2003 R2 Standard x64 > Edition Service Pack 2. > > > Using ISE8.2 SP3 (yes, 8.2) on an old test design that almost filled a > medium sized fpga, we recorded a run time of 6 hours and 12 minutes for > the older AMD machine, and 3 hours and 3 minutes for the new i7 machine. > That's 2.03 times as fast. > > The runs contained XST, ngdbuild, map, par, etc. In both cases, the 32 > bit version of software was used. Peak memory usage (during map) was > just under 3GBytes. Map was run with the -speed option. > > Regards, > Allan I should have some results in a few days. I'm waiting on the delivery of a Thermalright Ultra 120 heatsink, I should have it tomorrow. I'm building a system with a 920, 12G of DDR3 1600 and an Asus motherboard.Article: 142365
Symon <symon_brewer@hotmail.com> wrote: (snip) > This whole discussion is moot if I find a guy in your MIS department and > bung him $10k and a 6ft blonde with big lungs to give me the design files. Yes. Well, not completely. In the case of gambling machines (mentioned by Austin) or voting machines (mentioned by me), one has to be prepared for an inside job. That would include someone leaving the company with the designs, or being bribed to leak them. Now, one might have an older design but that would be a lot better than trying to reverse engineer the whole system. The design of the complete system, then, must protect against a maintenance person with a fake ROM. For some systems, the value in cracking it might be much more than the cost of the hardware, even the entire production. See: http://www.cl.cam.ac.uk/~mgk2/Ftamper2.pdf consider class III attacks. -- glenArticle: 142366
glen herrmannsfeldt wrote: > > See: http://www.cl.cam.ac.uk/~mgk2/Ftamper2.pdf > Typo fix... http://www.cl.cam.ac.uk/~mgk25/tamper2.pdfArticle: 142367
Symon <symon_brewer@hotmail.com> wrote: > glen herrmannsfeldt wrote: >> See: http://www.cl.cam.ac.uk/~mgk2/Ftamper2.pdf > Typo fix... > http://www.cl.cam.ac.uk/~mgk25/tamper2.pdf Oops. When I cut/paste it comes out with %2F for each /, which I had to replace. Also, they come out in dard red in my editor, which seems to recognize URLs, making it hard to see the mistake. thanks. -- glen From pcw@www.karpy.com Thu Aug 06 10:00:30 2009 Path: unlimited.newshosting.com!dartmaster!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.megapath.net!news.megapath.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 06 Aug 2009 12:01:37 -0500 From: Peter Wallace <pcw@www.karpy.com> Subject: Re: Peter Alfke Date: Thu, 06 Aug 2009 10:00:30 -0700 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2009.08.06.17.00.30.225509@www.karpy.com> Newsgroups: comp.arch.fpga References: <4b118e5d-4545-400e-976a-7df7df8c516f@2g2000prl.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 26 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.80.167.54 X-Trace: sv3-PZ3lcLsUnbBW98L12Draeh+mvTWaStVS2T/A7bTdZ3U+A5bj4CV+fSLDB1egWkgJXhrpaTfYKAvue8f!WzQOMNHrZY0DDlymeE1dw3QIMJNPFUVFC5fpL9D53raP2gSV5UUOJEAFBIpaUbHc9fViTEshq+pP!YcUHJWrlHls1 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 1771 Xref: unlimited.newshosting.com comp.arch.fpga:119045 On Thu, 06 Aug 2009 07:23:34 -0700, austin wrote: > http://www.pldesignline.com/guest_blogs/219100182 > > After a long, and productive career, Peter is going to see to other > things. > > He will be greatly missed here at Xilinx by all of us. > > I am sure you will join me in wishing him all the best. > > Now I am going to be greatly challenged to walk in his footsteps, and > continue his tradition of excellence here at Xilinx. > > Austin All the best Peter Alfke! I've always appreciated his wisdom and gentle didactic ways and have greatly enjoyed and learned from his Xilinx papers and posts here. Peter WallaceArticle: 142368
Kevin, It is here: https://bugzilla.mentor.com/show_bug.cgi?id=240 Note it is IR 2132, however it is bugzilla issue 240. Best, JimArticle: 142369
On Aug 6, 12:10=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Symon <symon_bre...@hotmail.com> wrote: > > (snip) > > > This whole discussion is moot if I find a guy in your MIS department an= d > > bung him $10k and a 6ft blonde with big lungs to give me the design fil= es. > > Yes. =A0Well, not completely. =A0In the case of gambling machines > (mentioned by Austin) or voting machines (mentioned by me), one has > to be prepared for an inside job. =A0That would include someone leaving > the company with the designs, or being bribed to leak them. > > Now, one might have an older design but that would be a lot better > than trying to reverse engineer the whole system. =A0The design of > the complete system, then, must protect against a maintenance person > with a fake ROM. =A0For some systems, the value in cracking it might > be much more than the cost of the hardware, even the entire production. > > See: =A0http://www.cl.cam.ac.uk/~mgk2/Ftamper2.pdf > > consider class III attacks. > > -- glen to say moot because of bribe is not complete picture. only when bribe is guaranteed 100% success is it safe to ignore all other security. we do not leave jail unlocked because somone may be able to bribe the guard. It may be very more likely that bribe to get design files is quite difficult for attacker compared to developing non-encrypted trojan bitstream when Trojan bitstream is the word i used before to describe the non- authorized bitstream which may affect outcome of voting machine or gaming machine or other. its not believed by this group at the moment but trojan bitstream may not need to mimik all internal fpga functionality of the authorized bitstream in order for attacker to be successful with hacking or providing unauthorized results (show 3 cherry on slot machine). except for open hardware platforms and hobbyist fpga based PCBs, risk doesnt seem worth loss, better to add system level protect fpga bitstream from trojan and non-authorized bitstream. which i will try to do. RajeshArticle: 142370
sorry part is missing > attacker compared to developing non-encrypted trojan bitstream when product in the field, captured by enemy, needing service or simply purchased.Article: 142371
Rajesh Gandhi <rgandhi4086@gmail.com> wrote: (snip) < to say moot because of bribe is not complete picture. < only when bribe is guaranteed 100% success is it safe < to ignore all other security. we do (snip) < authorized bitstream which may affect outcome of voting < machine or gaming machine or other. < its not believed by this group at the moment but trojan < bitstream may not need to mimik all internal fpga < functionality of the authorized bitstream in < order for attacker to be successful with hacking or < providing unauthorized results (show 3 cherry on slot machine). With just the device, tracing enough wires to write a new bitstream would be difficult. With the schematic and possibly an old version of the HDL source it might be very easy. Then a maintenance person (another bribe) puts in the replacement ROM with the modified code. But as Austin says, they don't claim protection for this case. -- glenArticle: 142372
On Aug 6, 10:00=A0pm, Peter Wallace <p...@www.karpy.com> wrote: > On Thu, 06 Aug 2009 07:23:34 -0700, austin wrote: > >http://www.pldesignline.com/guest_blogs/219100182 > > > After a long, and productive career, Peter is going to see to other > > things. > > > He will be greatly missed here at Xilinx by all of us. > > > I am sure you will join me in wishing him all the best. > > > Now I am going to be greatly challenged to walk in his footsteps, and > > continue his tradition of excellence here at Xilinx. > > > Austin > > All the best Peter Alfke! > > I've always appreciated his wisdom and gentle didactic ways > and have greatly enjoyed and learned from his Xilinx papers and > posts here. > > Peter Wallace Peter galvanized many engineers to look beyond the obvious and establish an in depth understanding of the problems. It is always a great pleasure in reading his application notes and answers at this discussion forum. I wish him health and pleasures in this new diemension of life. Regards, MoazzamArticle: 142373
On Aug 7, 5:59=A0am, Moazzam <moazzamhuss...@gmail.com> wrote: > On Aug 6, 10:00=A0pm, Peter Wallace <p...@www.karpy.com> wrote: > > > > > On Thu, 06 Aug 2009 07:23:34 -0700, austin wrote: > > >http://www.pldesignline.com/guest_blogs/219100182 > > > > After a long, and productive career, Peter is going to see to other > > > things. > > > > He will be greatly missed here at Xilinx by all of us. > > > > I am sure you will join me in wishing him all the best. > > > > Now I am going to be greatly challenged to walk in his footsteps, and > > > continue his tradition of excellence here at Xilinx. > > > > Austin > > > All the best Peter Alfke! > > > I've always appreciated his wisdom and gentle didactic ways > > and have greatly enjoyed and learned from his Xilinx papers and > > posts here. > > > Peter Wallace > > Peter galvanized many engineers to look beyond the obvious and > establish an > in depth understanding of the problems. It is always a great pleasure > in reading > his application notes and answers at this discussion forum. > > I wish him health and pleasures in this new diemension of life. > > Regards, > Moazzam I'll declare I'm a Xilinx employee, but only for the last 5-6 years and I've been using Xilinx devices for the past 20 years, my whole career so far, on and off. During that whole time, I've followed Peter's output both on the internet and in print (before there even was a "web"!), and his articles and postings have been highly informative and enjoyable (often helping to steer me in the right direction in the early days!) I never had the pleasure to meet him, being based in Scotland, but I found most of all that I warmed very much to his gentle tutorial style, his obvious enthusiasm and a kindly nature. I wish him all the best in his retirement (although I fully expect he'll still be around and contributing, albeit less officially than before!) All the best, Peter. Cheers, SteveArticle: 142374
Peter has been a great help for all of us here and even one of the reasons to choose Xilinx over their competition. I wish him well and hope that there is someone at Xilinx ready to pick up where he left! :) /Mikhail
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