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Based on my experience with another PHY I don't think this pin should be ever bidirectional unless you switch between MII and GMII modes on the fly. In the MII mode a PHY chip is supposed to have an internal source termination. If it doesn't or if you can't find out whether it does it might be worth adding a series resistor close to the PHY pin. In the GMII mode the source termination should be on the FPGA side. If you need to switch between the modes put the resistor in the middle of the trace. It is not ideal, but will porbably work just fine. Also, on the FPGA side instead of using a resistor you might be able to limit the buffer strength, which will have a similar effect. /Mikhail "Sudhir Singh" <Sudhir.Singh@email.com> wrote in message news:70bcd38e-19d7-4157-984d-4093191e615d@u16g2000pru.googlegroups.com... > Hi Guys, > I am doing a design in which a Micrel Gigabit ethernet phy is hooked > up to a Spartan3A DSP using the GMII/MII interface. The transmit clock > (GTX_CLK) in gigabit mode has to be sourced by the FPGA, but this > signal becomes an input to the FPGA in the 10/100 mode. > > I would like to know what you be the best way to terminate this bi- > directional signal on the PCB. I have looked at Xilinx ML405 dev and > spartan 3A DSP dev kit schemetics, but both dont have any termination > resistors. > > > Cheers > Sudhir > >Article: 142376
"Fredxx" <fredxx@spam.com> wrote in message news:h5ei4a$ffh$1@news.eternal-september.org... > > Isn't it a 3.3V logic level so doesn't really need termination, unless > it's trace is more than a few inches long? > The level is pretty much irrelevant, it's the rise time relative to the length of the trace what matters. /MikhailArticle: 142377
Hi, What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISEArticle: 142378
Hi!
I'm a newbie at verilog. I'm tryin to write to a block ram module, but I
don't know how to make it work.
Here's the module:
module ram_mod (clk, //Rellotge
en, //Byte Enable
we, //Write Enable
a, //Read/Write Address
di, //Data Input
do); //Data Output
input clk;
input en;
input we;
input [14:0] a;
input [7:0] di;
output [7:0] do;
reg [7:0] ram [14:0]; //32*1024 (1byte d'ample, 32Kbits de llarg)
reg [14:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
$display("ram[a] = %b[%b], di = %b, en = %b, we = %b, do = %b, read_a =
%b", ram[a], a, di, en, we, do, read_a);
end
assign do = ram[read_a];
endmodule
I copied it from xst document
(http://www.xilinx.com/itp/xilinx5/pdf/docs/xst/xst.pdf page 170) so I
think it right.
And that's what I do to access to the memory:
module mod_mem_tb;
reg clk;
reg en;
reg we;
reg [14:0] a;
reg [7:0] di;
wire [7:0] do;
reg [7:0] do_final;
//Per comprovar que no s'ha produit cap error
reg error_counter;
ram_mod ram (
.clk (clk), //Rellotge
.en (en), //Byte Enable
.we (we), //Write Enable
.a (a), //Read/Write Address
.di (di), //Data Input
.do (do) //Data Output
);
initial
begin : TB
//Inicialitzem totes les variables
error_counter <= 0;
clk <= 0;
en <= 0;
we <= 0;
a <= 0;
di <= 0;
do_final <= 0;
$display("\ttemps\tclk\ten\twe\ta\t\tdi\t\tdo\t\tdo_final");
$monitor("%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b",
$time,
clk,
en,
we,
a,
di,
do,
do_final);
#10 a <= 15'b100100000001001;
we <= 1;
en <= 1;
di <= 8'b11111111;
//Posem totes les variables d'escriptura a 0
#20 en = 0;
we = 0;
a = 0;
di = 0;
//Inicialitzem per a la lectura
#10 a = 15'b100100000001001;
en = 1;
do_final = do;
//Posem a 0 de nou
#10 en = 0;
a = 0;
#40
$finish;
end
always
#5 clk = !clk;
endmodule
And the output is the following:
# temps clk en we a di do do_final
# 0 0 0 0 000000000000000 00000000 xxxxxxxx 00000000
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = xxxxxxxxxxxxxxx
# 5 1 0 0 000000000000000 00000000 xxxxxxxx 00000000
# 10 0 1 1 100100000001001 11111111 xxxxxxxx 00000000
# ram[a] = xxxxxxxx[100100000001001], di = 11111111, en = 1, we = 1, do =
xxxxxxxx, read_a = xxxxxxxxxxxxxxx
# 15 1 1 1 100100000001001 11111111 xxxxxxxx 00000000
# 20 0 1 1 100100000001001 11111111 xxxxxxxx 00000000
# ram[a] = xxxxxxxx[100100000001001], di = 11111111, en = 1, we = 1, do =
xxxxxxxx, read_a = 100100000001001
# 25 1 1 1 100100000001001 11111111 xxxxxxxx 00000000
# 30 0 0 0 000000000000000 00000000 xxxxxxxx 00000000
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 35 1 0 0 000000000000000 00000000 xxxxxxxx 00000000
# 40 0 1 0 100100000001001 00000000 xxxxxxxx xxxxxxxx
# ram[a] = xxxxxxxx[100100000001001], di = 00000000, en = 1, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 45 1 1 0 100100000001001 00000000 xxxxxxxx xxxxxxxx
# 50 0 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 55 1 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# 60 0 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 65 1 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# 70 0 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 75 1 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# 80 0 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
# ram[a] = xxxxxxxx[000000000000000], di = 00000000, en = 0, we = 0, do =
xxxxxxxx, read_a = 100100000001001
# 85 1 0 0 000000000000000 00000000 xxxxxxxx xxxxxxxx
So it's not writing into memory. Can you help me?
Thank you in advance
Article: 142379On Aug 7, 12:14=A0pm, "nskri" <ansga...@gmail.com> wrote: > Hi! > > I'm a newbie at verilog. I'm tryin to write to a block ram module, but I > don't know how to make it work. > > Here's the module: > > module ram_mod (clk, =A0 =A0//Rellotge > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 en, =A0 =A0 //Byte Enable > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 we, =A0 =A0 //Write Enable > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 a, =A0 =A0 =A0//Read/Write Address > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 di, =A0 =A0 //Data Input > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 do); =A0 =A0//Data Output > > input clk; > input en; > input we; > input [14:0] a; > input [7:0] di; > > output [7:0] do; > > reg [7:0] ram [14:0]; //32*1024 (1byte d'ample, 32Kbits de llarg) What you describe here is 8 bits wide and only 15 elements. I think you should write: reg [7:0] ram [0:32767]; //32*1024 (1byte d'ample, 32Kbits de llarg) This would be 32K bytes. HTH, GaborArticle: 142380
I think I'm seeing a bug in ISE 11.1 where the RTL and technology schematics don't get updated after editing and rerunning synthesis. When I edit my source VHDL and change the entity ports, for example, and then rerun synthesis, the RTL schematic viewer insists on showing me the old schematic with the old ports. The strange thing is, in FPGA Editor I see the new signals just fine. Exiting Project Navigator and restarting it brings everything up to date. This applies to any kind of edit, not just changing the entity ports. I'm using ISE 11.1. Anyone else run into this?Article: 142381
jadwin79 wrote: > I think I'm seeing a bug in ISE 11.1 where the RTL and technology > schematics don't get updated after editing and rerunning synthesis. > > When I edit my source VHDL and change the entity ports, for example, > and then rerun synthesis, the RTL schematic viewer insists on showing > me the old schematic with the old ports. The strange thing is, in > FPGA Editor I see the new signals just fine. Exiting Project Navigator > and restarting it brings everything up to date. > > This applies to any kind of edit, not just changing the entity ports. > > I'm using ISE 11.1. Anyone else run into this? Yes I've seen this. I haven't had time yet to report it to Xilinx - and anyway, I want to see if it still happens in 11.2. I found that even doing a project cleanup didn't work - you had to go into the project folder and delete files that weren't deleted by the project cleanup, regards Alan -- Alan Fitch DoulosArticle: 142382
Hi, I am testing a piece of hardware on ML-561(Virtex5). I plan to provide the inputs from a bram pre-loaded with the input cases and the outputs will be written to another bram. I want to read the output data stored in that bram to my PC using Xilinx ISE10.1. How can I do that? Please help. Thank you. Shamanth.Article: 142383
On Aug 6, 7:21=A0am, Allan Herriman <allanherri...@hotmail.com> wrote: > Using ISE8.2 SP3 (yes, 8.2) on an old test design that almost filled a > medium sized fpga, we recorded a run time of 6 hours and 12 minutes for > the older AMD machine, and 3 hours and 3 minutes for the new i7 machine. = =A0 > That's 2.03 times as fast. Thanks for the data. Since it was ISE8.2, I assume that the software couldn't take advantage of the additional cores? It should be interesting to see how much of a difference the multi-threaded place & route in ISE11 makes.Article: 142384
Dear All,
I am encountering some troubles with quartus fitter, the fitter auto
assign a pin on an already assign pin here is the report of the
fitter :
Info: Fitter is performing an Auto Fit compilation, which may decrease
Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device
migration later, you may need to change the pin assignments as they
may be incompatible with other devices
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location G7
Info: Pin ~nCSO~ is reserved at location K9
Info: Pin ~LVDS195p/nCEO~ is reserved at location AD25
Error: Can't place multiple pins assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin iSW[7] is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin ~LVDS195p/nCEO~ is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
So I don't already understand where the pin LVDS195p/nCEO come from
and even more why the fitter put it on an assigned pin
(I am working on a Terasic board and I put the pin as it was given
with exemple)
Best Regards
Article: 142385
Dear All,
I am encountering some troubles with quartus fitter, the fitter auto
assign a pin on an already assign pin here is the report of the
fitter :
Info: Fitter is performing an Auto Fit compilation, which may decrease
Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device
migration later, you may need to change the pin assignments as they
may be incompatible with other devices
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location G7
Info: Pin ~nCSO~ is reserved at location K9
Info: Pin ~LVDS195p/nCEO~ is reserved at location AD25
Error: Can't place multiple pins assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin iSW[7] is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin ~LVDS195p/nCEO~ is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
So I don't already understand where the pin LVDS195p/nCEO come from
and even more why the fitter put it on an assigned pin
(I am working on a Terasic board and I put the pin as it was given
with exemple)
Thx for your help
Article: 142386>On Aug 7, 12:14=A0pm, "nskri" <ansga...@gmail.com> wrote: >> Hi! >> >> I'm a newbie at verilog. I'm tryin to write to a block ram module, but I >> don't know how to make it work. >> >> Here's the module: >> >> module ram_mod (clk, =A0 =A0//Rellotge >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 en, =A0 =A0 //Byte Enable >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 we, =A0 =A0 //Write Enable >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 a, =A0 =A0 =A0//Read/Write Address >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 di, =A0 =A0 //Data Input >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 do); =A0 =A0//Data Output >> >> input clk; >> input en; >> input we; >> input [14:0] a; >> input [7:0] di; >> >> output [7:0] do; >> >> reg [7:0] ram [14:0]; //32*1024 (1byte d'ample, 32Kbits de llarg) > >What you describe here is 8 bits wide and only 15 elements. I think >you should write: > >reg [7:0] ram [0:32767]; //32*1024 (1byte d'ample, 32Kbits de llarg) > >This would be 32K bytes. > >HTH, >Gabor > Hi Gabor, thank you! You were right, I just changed that and everything works fine now. But I don't undersand why it works now, I mean, [0:32767] means that there are about 32000 bits for choosing the address, and this is much more than 32000 memory positions (wich would require 15 bits only). So, where's my mistake? Can u help me? Thanks again,Article: 142387
On Sat, 08 Aug 2009 06:35:43 -0500, "nskri" wrote:
>But I don't undersand why it works now, I mean, [0:32767] means that there
>are about 32000 bits for choosing the address, and this is much more than
>32000 memory positions (wich would require 15 bits only).
In Verilog,
reg [7:0] A;
means an 8-bit vector, as you know.
But this:
reg A[0:7];
is an array of eight single-bit values. The first value is A[0].
The last value is A[7].
Your memory
reg [7:0] mem [0:32767];
is an array of 32768 words; each word is 8 bits wide. The
address you need for those words is, of course, only 15 bits
wide because a 15-bit address can hold values in the range
0 to 32767.
Your mistake, I guess, is to imagine that the second subscript
represents the ADDRESS. It doesn't. It represents the large
number of memory LOCATIONS.
Here's a common way to describe such things:
module parameterized_memory
#( parameter ADDRESS_BITS = 15, // number of adrs bits
DATA_BITS = 8 )
( input [ADDRESS_BITS-1:0] Address
, input [DATA_BITS-1:0] WriteData
, output [DATA_BITS-1:0] ReadData
, ...);
// Knowing the address width, compute the number
// of addressable memory locations. For example,
// with 4 address bits you can address 16 locations.
// This is 16 = 2**4 but in Verilog it's better to do...
parameter NUMBER_OF_LOCATIONS = 1 << ADDRESS_BITS;
// Declare the memory array
reg [DATA_BITS-1:0] mem [0:NUMBER_OF_LOCATIONS-1];
// write to the memory
always @(posedge clock)
if (write_enable)
mem[Address] <= WriteData;
// .... etc, etc, ....
Hope this clarifies things a little.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 142388On Aug 6, 9:23=A0am, austin <aus...@xilinx.com> wrote: > http://www.pldesignline.com/guest_blogs/219100182 > > After a long, and productive career, Peter is going to see to other > things. > > He will be greatly missed here at Xilinx by all of us. > > I am sure you will join me in wishing him all the best. > > Now I am going to be greatly challenged to walk in his footsteps, and > continue his tradition of excellence here at Xilinx. > > Austin Best of luck to you! Peter will be missed.Article: 142389
On Thu, 6 Aug 2009 07:23:34 -0700 (PDT), austin@xilinx.com wrote: > After a long, and productive career, Peter is going to > see to other things. If there is any justice in the world, that's going to be one hell of a retirement party. Peter has done the same thing for FPGAs that Horowitz and Hill did for analog electronics: impeccable clarity of thought, allied to impeccable clarity of presentation. Way back, I admired the thoroughness and readability of those Zilog data sheets (remember the 8530 SCC?) without ever knowing who created them. Now I know, and I still admire (and often wish I could do half as well). In these days of gratuitous complexity and obfuscation, Peter's ability to make difficult things look easy without sacrificing rigour is of the greatest value and, as others have said, will be sadly missed. Thanks, and best wishes. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 142390
austin <austin@xilinx.com> wrote: < http://www.pldesignline.com/guest_blogs/219100182 < After a long, and productive career, Peter is going to see < to other things. < He will be greatly missed here at Xilinx by all of us. < I am sure you will join me in wishing him all the best. When I was in graduate school one day in the lounge they had a retirement ceremony for a professor. There was cake and punch (sure to attract students), and some words about his work and how much he would be missed. In the end, was some thing like "we hope this won't interfere too much with your work." I do hope that once in a while he will still read and post to comp.arch.fpga. Bet yes, I wish him the best! thanks for all your contributions. -- glenArticle: 142391
I don't know how old this mail is, but i have been searching the net and found it. I have just started this tutorial: http://www.fpga4fun.com/10BASE-T1.html good luckArticle: 142392
austin <austin@xilinx.com> wrote:
>http://www.pldesignline.com/guest_blogs/219100182
>
>After a long, and productive career, Peter is going to see to other
>things.
>
>He will be greatly missed here at Xilinx by all of us.
>
>I am sure you will join me in wishing him all the best.
>
>Now I am going to be greatly challenged to walk in his footsteps, and
>continue his tradition of excellence here at Xilinx.
Well, if Peter is no longer employed by Xilinx he is free to post
whatever he wants in this newsgroup :-)
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142393On Aug 8, 2:26=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > > Well, if Peter is no longer employed by Xilinx he is free to post > whatever he wants in this newsgroup :-) > Nico, I was never ever held back, censored or reprimanded by Xilinx management. After the end of this month I will no longer be an employee, but still a shareholder of Xilinx. And I owe this company a lot of gratitude, financial, intellectual, and emotional. It was "the best years of my life". So don't expect me to divulge any "dirty secrets", whatever you might imagine them to be. And thanks for all the friendly comments that came in. Feels like a eulogy... PeterArticle: 142394
Hi I need to compute an evarage of an analog input sampled by a ADC The evarage is defined for several positive peaks sum, devided in the number of peaks so it changes all the time. I need this for an audio effect design. The main problem is how to exactly "catch" the peak sample that is closest to the real positive peak in the input volatage sampled . How do I do that what is the algorythm in simple words ? Thanks BarNashArticle: 142395
On Aug 9, 12:01=A0pm, "BarNash" <therighti...@gmail.com> wrote: > Hi > > I need to compute an evarage of an analog input > sampled by a ADC > The evarage is defined for =A0several positive peaks sum, devided in the > number of peaks > so it changes all the time. > > I need this for an audio effect design. > The main problem is how to exactly "catch" the > peak sample that is closest to the real positive peak > in the input volatage sampled . > > How do I do that what is the algorythm in simple words ? > > Thanks > BarNash why not look here: http://www.beis.de/Elektronik/DPLCM/DPLCM.html ? AnttiArticle: 142396
On Aug 9, 12:45=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 9 Aug 2009 11:01:52 +0200, "BarNash" <therighti...@gmail.com> wro= te: > >Hi > > >I need to compute an evarage of an analog input > >sampled by a ADC > >The evarage is defined for =A0several positive peaks sum, devided in the > >number of peaks > >so it changes all the time. > > >I need this for an audio effect design. > >The main problem is how to exactly "catch" the > >peak sample that is closest to the real positive peak > >in the input volatage sampled . > > >How do I do that what is the algorythm in simple words ? > > >Thanks > >BarNash > > Doing some research on "everage", I found this. > > http://en.wikipedia.org/wiki/Edna_Everage > > - Brian- Hide quoted text - > > - Show quoted text - coool! brings a real good smile ;) Antti PS, if you look my other reply, i was able to withstand my usual style of commenting (to people with serious spelling issues)Article: 142397
On Sun, 9 Aug 2009 11:01:52 +0200, "BarNash" <therightinfo@gmail.com> wrote: >Hi > >I need to compute an evarage of an analog input >sampled by a ADC >The evarage is defined for several positive peaks sum, devided in the >number of peaks >so it changes all the time. > >I need this for an audio effect design. >The main problem is how to exactly "catch" the >peak sample that is closest to the real positive peak >in the input volatage sampled . > >How do I do that what is the algorythm in simple words ? > >Thanks >BarNash > Doing some research on "everage", I found this. http://en.wikipedia.org/wiki/Edna_Everage - BrianArticle: 142398
On Sun, 9 Aug 2009 02:43:07 -0700 (PDT), Antti Lukats wrote: >PS, if you look my other reply, i was able to withstand >my usual style of commenting That's probably a pity. The OP has already floated this question in comp.lang.vhdl, where he received not only polite correction of the spelling mistake but also some interesting and thought-provoking suggestions. It seems that he is too idle to think about a reply there, but instead simply copy/pasted his question here. Some folk are beyond help. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 142399
Hi Mikhail, Thanks for your reply. You said that the clock pin should never be bidirectional unless on the fly switching is needed. Are you saying that regardless of what ever speed the line is operating at (10/100/1000 Mbps), the PHY will always have the interface to the MAC operating at 1000Mbps, i.e in GMII? The Micrel PHY I am looking at has a boot strap option of starting in GMII/MII mode, I couldn't see anything to force a GMII only mode. I am wondering whether PHY switches to MII when it finds a 10/100 Mbps device at the other end, and switches to GMII if it finds a 1000Mbps device. Thanks Sudhir
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