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Austin, When you say both do you mean GTP and GTX, or all three including MGT ? I am considering connecting a V4FX chip to a V5FX using Aurora protocol and running at 3.36 Gbps. It is working fine between two V4FXs. Thanks, /Mikhail "austin" <austin@xilinx.com> wrote in message news:150e9b8f-2fd1-424d-ab75-e81e2fbc60a6@m3g2000pri.googlegroups.com... > Mikhail, > > They are both designed to standards, so they are compatible if each is > using the same standard (same rate, and data format). > > Of one note, check the common mode voltages for the standard: in some > cases AC coupling is required, (although I think this is only true for > the lower voltage GTX to higher supply voltage GTP).Article: 142501
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
>DJ Delorie <dj@delorie.com> wrote:
>
>< Frank Buss <fb@frank-buss.de> writes:
><> This would be a lifetime project for most students. I think starting with
><> low-level gates is a good idea.
>
>< Keep in mind the original question - what should a Spartan-6 board be?
>< I think most of the people getting such an eval board would want
>< something that pushed the envelope, not something trivial.
>
>< Besides, students can always add a low-level gate as a peripheral ;-)
>
>At FCCM95 I was part of a discussion on how to teach digital
>logic in the future. I was figuring that in not so many years
>TTL gates would be gone. It seems that they are still available
>for now, though. Much of the discussion was that FGPA companies
>should have free software that beginners could use. That problem
>seems to have been solved.
'TTL' logic will never go away. In most cases an FPGA is just way too
expensive. Many of the circuits I design just need a simple flipflop
or a single gate.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142502nico@puntnl.niks (Nico Coesel) writes: > 'TTL' logic will never go away. In most cases an FPGA is just way too > expensive. Many of the circuits I design just need a simple flipflop > or a single gate. I don't know about that... with CPLDs under $1 I see an opportunity for a company to produce a range of CPLDs that vary only in footprint and power connections, so that they can be used to replace anything else. It would be a handy RMA tool :-)Article: 142503
On Aug 12, 7:32=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Aug 12, 11:40=A0am, Test01 <cpan...@yahoo.com> wrote: > > > On Aug 12, 6:21=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > I am not trying to test the specifics of OSERDES and ISERDES in > > design1. =A0Design1 contans a split transaction serial bus exerciser > > that I need to use to test design2. =A0But design1 uses OSERDES and > > ISERDES primitves to serilize the bit stream of the split transaction > > bus as it was intended for normal I/O application. =A0Here I am trying > > to figure out if I can use design1 as is to test design2. =A0It seems > > that at minimum I need to replace the ISERDES and OSERDES with my own > > serilizer and derserilizer verilog models to keep the low effort > > level. I am trying to avoid designing design1 from scratch in order to > > You have three options, listed from worst to best (in my opinion) > 1. =A0Bring the design 1 SERDES outputs out to I/O pins and modify the > board to connect these outputs to the inputs pins of design 2. > 2. =A0Re-read the second and third paragraph of my previous post and > implement that instead. =A0You do not need to write code for a > serializer or a deserializer in order to implement the combined > function of both. =A0To do this you don't need to hack up design 1, you > simply need to change the top level I/O of design 1 and design 2 to > have a wider parallel interface and connect them together either with > a bank of flops or a fifo as I suggested previously. =A0Since this > interface is all internal to the FPGA no I/O pin modifications to the > board are required. > 3. =A0The best option is to simulate the system. =A0Instantiate design 1 > and design 2, connect the I/O appropriately, model other parts on the > PCBA if necessary. =A0Set up any other stimulus as required, run the > simulation and verify that the design operates properly. =A0This is the > best and most accurate way of getting your design correct. =A0Once > skilled in this process it is far more productive than debug on > hardware > > Kevin Jennings Thanks for the feedback. One more caveat to this is that the Design1 outout is DDR type. I am not sure if it is easy to generate the DDR data stream internally. OSERDES and ISERDES and IDDR are capable but they are for external I/O. it just seems that I need to connect design1 and design2 at the parallel interface and not the serial interfaceArticle: 142504
I only speak VHDL. Unfortunately, the memory interface generator in ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device models underneath are in the silly encrypted Verilog format, so I can't even go spelunking around. So far, Modelsim XE Starter (free) has been sufficient for all my simulation needs. In order to do mixed language simulation, however, I'd need to step up to Modelsim PE, which I just had quoted to me for slightly under $10K for a one year license. All I really need it for is to simulate out my memory interface stuff; I have very little interest in adding lots of mixed language programming to my world. And so ten kilobucks is really quite the chunk of change for solving one problem. Does anyone know of any better solutions for mixed language simulation? I had been thinking this would cost me somewhere in the $2K ballpark; at $10K I'd be better off sticking with "program and pray". -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 142505
Nico Coesel <nico@puntnl.niks> wrote: (snip) < 'TTL' logic will never go away. In most cases an FPGA is just way too < expensive. Many of the circuits I design just need a simple flipflop < or a single gate. It seems that way, though I wasn't so convinced in 1995. Today I do wonder if digital cameras will completely replace film in not so many years. The transition is much faster than I would have thought. PAL chips at the right price might be a good replacement for many TTL chips. Otherwise, it seems that SOIC versions of TTL are becoming increasingly popular. -- glenArticle: 142506
On Aug 13, 4:03=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > I only speak VHDL. =A0Unfortunately, the memory interface generator in > ISE 11.2 for Spartan-6 only speaks Verilog. =A0Specifically, the device > models underneath are in the silly encrypted Verilog format, so I can't > even go spelunking around. > > So far, Modelsim XE Starter (free) has been sufficient for all my > simulation needs. =A0In order to do mixed language simulation, however, > I'd need to step up to Modelsim PE, which I just had quoted to me for > slightly under $10K for a one year license. > > All I really need it for is to simulate out my memory interface stuff; > I have very little interest in adding lots of mixed language > programming to my world. =A0And so ten kilobucks is really quite the > chunk of change for solving one problem. > > Does anyone know of any better solutions for mixed language > simulation? =A0I had been thinking this would cost me somewhere in the > $2K ballpark; at $10K I'd be better off sticking with "program and > pray". > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Hello Rob, The ISIM simulator that comes with ISE supports mixed VHDL and Verilog simulation. It comes standard with all editions of ISE. Look here: http://www.xilinx.com/tools/logic.htm, and click on the ISIM link for details. Regards, John McCaskill Faster Technology Xilinx Authorized Training Provider http://www.fastertechnology.com/training.htmlArticle: 142507
Rob Gaddi wrote:
> Does anyone know of any better solutions for mixed language
> simulation? I had been thinking this would cost me somewhere in the
> $2K ballpark; at $10K I'd be better off sticking with "program and
> pray".
Or infer the block ram from vhdl code.
-- Mike Treseler
Article: 142508On Thu, 13 Aug 2009 15:24:19 -0700 Mike Treseler <mtreseler@gmail.com> wrote: > Rob Gaddi wrote: > > > Does anyone know of any better solutions for mixed language > > simulation? I had been thinking this would cost me somewhere in the > > $2K ballpark; at $10K I'd be better off sticking with "program and > > pray". > > Or infer the block ram from vhdl code. > > -- Mike Treseler Not block RAM. Giant complex multiple FIFO interface to external DDR2. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 142509
Rob Gaddi schrieb: > I only speak VHDL. Unfortunately, the memory interface generator in > ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device > models underneath are in the silly encrypted Verilog format, so I can't > even go spelunking around. > > So far, Modelsim XE Starter (free) has been sufficient for all my > simulation needs. In order to do mixed language simulation, however, > I'd need to step up to Modelsim PE, which I just had quoted to me for > slightly under $10K for a one year license. > > All I really need it for is to simulate out my memory interface stuff; > I have very little interest in adding lots of mixed language > programming to my world. And so ten kilobucks is really quite the > chunk of change for solving one problem. > > Does anyone know of any better solutions for mixed language > simulation? I had been thinking this would cost me somewhere in the > $2K ballpark; at $10K I'd be better off sticking with "program and > pray". > Aldec recently had an offer of their mixed-language windows simulator ActiveHDL for around $1,600. As far as I remember though, that was per year. So it might not be quite what you are looking for, assuming the offer is even still available in the first place. It is largely script compatible to modelsim.Article: 142510
On Aug 13, 10:03=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > I only speak VHDL. =A0Unfortunately, the memory interface generator in > ISE 11.2 for Spartan-6 only speaks Verilog. =A0Specifically, the device > models underneath are in the silly encrypted Verilog format, so I can't > even go spelunking around. > > So far, Modelsim XE Starter (free) has been sufficient for all my > simulation needs. =A0In order to do mixed language simulation, however, > I'd need to step up to Modelsim PE, which I just had quoted to me for > slightly under $10K for a one year license. > > All I really need it for is to simulate out my memory interface stuff; > I have very little interest in adding lots of mixed language > programming to my world. =A0And so ten kilobucks is really quite the > chunk of change for solving one problem. > > Does anyone know of any better solutions for mixed language > simulation? =A0I had been thinking this would cost me somewhere in the > $2K ballpark; at $10K I'd be better off sticking with "program and > pray". > You can synthesize the design to a netlist then use netgen to get a functional simulation model. They are not fast but do the job. Cheers, Andy.Article: 142511
On Aug 13, 11:10=A0am, "MM" <mb...@yahoo.com> wrote: > Austin, > > When you say both do you mean GTP and GTX, or all three including MGT ? = =A0I > am considering connecting a V4FX chip to a V5FX using Aurora protocol and > running at 3.36 Gbps. It is working fine between two V4FXs. > > Thanks, > /Mikhail MGT is an ancronym that means Multi-Gigabit Transcevier. Each of the Virtex families had a different cell name that was used with the tools. V-II Pro GT V-II ProX GT10 V-4 GT11 V-5 GTP_DUAL & GTX_DUAL V-6 GTXE1 S-6 GTPA1_DUAL So long as the data rate (1.0G, 2.0G, 3.36G, 6.5G etc) is supported by the particular technology any MGT will be able to talk to any other MGT. If this didn't work then it wouldn't be a viable technology. The only caveat that needs to be added is that above applies to AC coupled links. If a link is DC coupled then you need to ensure that the transmitter is providing electrical levels that are compatable with the receiver. Always AC couple your links unless you absolutely must DC couple them. Ed McGettigan -- Xilinx Inc.Article: 142512
On Thu, 13 Aug 2009 14:03:07 -0700, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >I only speak VHDL. Unfortunately, the memory interface generator in >ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device >models underneath are in the silly encrypted Verilog format, so I can't >even go spelunking around. > >So far, Modelsim XE Starter (free) has been sufficient for all my >simulation needs. In order to do mixed language simulation, however, >I'd need to step up to Modelsim PE, which I just had quoted to me for >slightly under $10K for a one year license. > >All I really need it for is to simulate out my memory interface stuff; >I have very little interest in adding lots of mixed language >programming to my world. And so ten kilobucks is really quite the >chunk of change for solving one problem. > >Does anyone know of any better solutions for mixed language >simulation? I had been thinking this would cost me somewhere in the >$2K ballpark; at $10K I'd be better off sticking with "program and >pray". In ISE10, ISIM sort of works, and can handle Verilog memory models with some limitations. ISIM ought to work at least as well in ISE11, Xilinx appeared to be paying a lot of attention to improving it. The limitations are (in ISE10) (a) Verilog memories can only be instantiated at the top level of the testbench, not in e.g. an entity representing a SODIMM. (This can be worked around, but it gets extremely painful for bidirectional signals). And (b) connecting >1 memory module to the data bus (even with correctly wired chip selects) doesn't work. (This is painful because the timing calibration only works on the higher addressed memories and your testbench probably wants to address the lower addressed memories; you can't leave either half unpopulated and populating both doesn't work) If you can live with these limitations, ISIM may be worth a look. As a bonus, it's also cross-platform; you're not tied to Windows. Either or both of these limitations may have been fixed in ISE11, but I was left with the distinct impression by the Webcase folks that ISE12 was more likely. The lack of VHDL memory models isn't Xilinx's fault; they supply the formerly excellent Micron models, and Micron seem to have stopped supplying VHDL models witd the DDR1 generation of memory. But if MIG has stopped producing VHDL memory cores, I regard that as a seriously bad development. Say it isn't so... - BrianArticle: 142513
Hi All, 1.Added a new User Delay and Constraint Editor panel. You can add, delete, or update User Delays or Constraints. 2 .These User Delays and User Constraints are saved at the top of the .tim file. 3.Changing a User Delay or User Constraint updates every one of the same type in the diagram. 4.Files created with previous versions are converted to this new format when saved. 5.Added Python Interpreter, Jython 2.5. Now you can write scripts in Python. 6.Execute Python scripts using the same script dialog for the beanshell scripts or from Jython command line window. 7.Included start_app.py script in the install directory that will start the TimingAnalyzer from a Jython command line window. 8.Updated spice_pwl.bsh. This beanshell script generates spice piece wise linear test vectors for DigitalBus. 9.Included dff.py. This Python script shows how to generate a timing diagram for a D Flip Flop. Anyone interested in helping convert the Java scripts (in the scripts dir) to Python should let me know. Dan Fabrizio www.timing-diagrams.comArticle: 142514
On 8=D4=C214=C8=D5, =C9=CF=CE=E71=CA=B136=B7=D6, Mike Treseler <mtrese...@g= mail.com> wrote: > braver wrote: > > In the past , I can leave the ouput port of sub module as blank , and > > no problem happen . > > Can some one give me some advice. > > Synthesis works from port to port on the top module/entity. > No ports, no gates. > > -- Mike Treseler In the past , when I instantiate some IP like fifo , I don't connect some port like wr_count .It never affect synthesizer.Article: 142515
Ed, Thank you very much for the comforting information. /Mikhail "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:48407903-5cd3-446a-b981-c3ec9ab21cd8@a37g2000prf.googlegroups.com... On Aug 13, 11:10 am, "MM" <mb...@yahoo.com> wrote: > Austin, > > When you say both do you mean GTP and GTX, or all three including MGT ? I > am considering connecting a V4FX chip to a V5FX using Aurora protocol and > running at 3.36 Gbps. It is working fine between two V4FXs. > > Thanks, > /Mikhail MGT is an ancronym that means Multi-Gigabit Transcevier. Each of the Virtex families had a different cell name that was used with the tools. V-II Pro GT V-II ProX GT10 V-4 GT11 V-5 GTP_DUAL & GTX_DUAL V-6 GTXE1 S-6 GTPA1_DUAL So long as the data rate (1.0G, 2.0G, 3.36G, 6.5G etc) is supported by the particular technology any MGT will be able to talk to any other MGT. If this didn't work then it wouldn't be a viable technology. The only caveat that needs to be added is that above applies to AC coupled links. If a link is DC coupled then you need to ensure that the transmitter is providing electrical levels that are compatable with the receiver. Always AC couple your links unless you absolutely must DC couple them. Ed McGettigan -- Xilinx Inc.Article: 142516
"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message news:20090813140307.000017fb@unknown... >I only speak VHDL. Unfortunately, the memory interface generator in > ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device > models underneath are in the silly encrypted Verilog format, so I can't > even go spelunking around. I assume they use SecureIP in which case you need a "new" Swift interface license. This is a lot cheaper than a PE VHDL+Verilog license. Hans www.ht-lab.com > > So far, Modelsim XE Starter (free) has been sufficient for all my > simulation needs. In order to do mixed language simulation, however, > I'd need to step up to Modelsim PE, which I just had quoted to me for > slightly under $10K for a one year license. > > All I really need it for is to simulate out my memory interface stuff; > I have very little interest in adding lots of mixed language > programming to my world. And so ten kilobucks is really quite the > chunk of change for solving one problem. > > Does anyone know of any better solutions for mixed language > simulation? I had been thinking this would cost me somewhere in the > $2K ballpark; at $10K I'd be better off sticking with "program and > pray". > > -- > Rob Gaddi, Highland Technology > Email address is currently out of orderArticle: 142517
Hi all I have a (Verilog, RTL) description of a memory block, that I know synthesizes to BRAM(s). I am using this to create 64k of system memory, letting XST split the block into discrete BRAM's. (cue the '64k should be enough for everyone!' line). The entire flow for the complete design takes ~1hr from .v to .bit (it includes a fair number of other parts as well). The memory itself is declared as: //synthesis attribute ram_style of prom is block reg [RAM_WIDTH-1:0] prom [(2**RAM_ADDR_BITS)-1:0]; Despite it being named prom, its actually a RAM; I just want to preload data into it. So really, its a PRAM. If I add initialization code, like thus, initial begin prom[0] <= 64'h013800000f802020; prom[1] <= 64'h01fc00000f802020; .... prom[8191] <= 64'h0000000000000000; end then XST stops for a long time on this module. The entire flow completes, but it takes about 12 hours in total. Does anyone happen to know why XST spends a lot of time here? (I've been assuming its trying to find patterns in the binary data, and tries map to a shift register or otherwise optimize, but I could very well be wrong). Also, is there a way of telling XST that it shouldn't be spending the time but just map it to BRAMs? Thanks in advance for any ideas / pointers / documentation I've missed! //OscarArticle: 142518
On Aug 14, 8:27=A0am, Oscar <o.al...@gmail.com> wrote:
> Hi all
>
> I have a (Verilog, RTL) description of a memory block, that I know
> synthesizes to BRAM(s). I am using this to create 64k of system
> memory, letting XST split the block into discrete BRAM's. (cue the
> '64k
> should be enough for everyone!' line). The entire flow for the
> complete
> design takes ~1hr from .v to .bit (it includes a fair number of
> other parts as well).
>
> The memory itself is declared as:
>
> //synthesis attribute ram_style of prom is block
>
> reg [RAM_WIDTH-1:0] prom [(2**RAM_ADDR_BITS)-1:0];
>
> Despite it being named prom, its actually a RAM; I just want to
> preload data into it. So really, its a PRAM.
> If I add initialization code, like thus,
>
> initial begin
>
> prom[0] <=3D 64'h013800000f802020;
> prom[1] <=3D 64'h01fc00000f802020;
> ....
> prom[8191] <=3D 64'h0000000000000000;
>
> end
>
> then XST stops for a long time on this module. The entire flow
> completes, but it takes about 12 hours in total. Does anyone happen to
> know why XST spends a lot of time here? (I've been assuming its trying
> to find patterns in the binary data, and tries map to a shift register
> or otherwise optimize, but I could very well be wrong). Also, is there
> a
> way of telling XST that it shouldn't be spending the time but just map
> it to BRAMs?
>
> Thanks in advance for any ideas / pointers / documentation I've
> missed!
>
> //Oscar
It's sometimes hard to second-guess what something as
complex as XST is doing in this case. I would suggest trying
a different approach to initialization, however. Using
$readmemh in the initial block like:
initial begin
$readmemh ("initial_prom_data.hex", prom);
end
Also make sure your memory logic matches the templates
in the XST guide.
One note on the data file (initial_prom_data.hex). The
Verilog LRM says that the data file can include address
pointers for partial loading. It also states that you
can delimit the values with any whitespace. XST is
more finicky. It requires one entry per line and will
not handle addresses (@00100 for example) or Verilog
comments, which the LRM also allows. Furthermore XST
will not actually initialize your memory unless the
file has exactly the number of elements of your memory
array. All that being said, I've never seen this
process take a long time during synthesis and it may
be worth the headache in your case.
The other workaround, as distasteful as it may be to
purists, is to generate the memory with CoreGen and
a .coe file for initialization. This allows you to
specify the RAM primitives and provides a module
with just the ports and address sizes you need.
Regards,
Gabor
Article: 142519Normally in order to generate the DDR stream I put ODDR or OSERDES primitve but that goes out of the FPGA. Is it possible to generate double data rate stream in the Virtex4 fabric? This is just for getting better understanding of the V4 fabric is capable of. It seems that for my application I just need to remove the serial comonents between design1 and design2 and run paralllel single data rate interface between themArticle: 142520
On Aug 14, 4:52=A0pm, Test01 <cpan...@yahoo.com> wrote: > Normally in order to generate the DDR stream I put ODDR or OSERDES > primitve but that goes out of the FPGA. =A0Is it possible to generate > double data rate stream in the Virtex4 fabric? =A0This is just for > getting better understanding of the V4 fabric is capable of. > > It seems that for my application I just need to remove the serial > comonents between design1 and design2 and run paralllel single data > rate interface between them you are asking the wrong questions! i assume you want to have DUAL clock edge flip-flop inside the fabric? well it isnt there. you need either to use 2x clock, or then use clock as MUX signal both not so nice way for you i assume. but there really is no reason to use DDR inside the FPGA... if you want to test DDR then take solder iron and connect some FPGA pins as short circuit loopback, and run the test with real DDR signal AnttiArticle: 142521
On Aug 14, 4:52=A0pm, Test01 <cpan...@yahoo.com> wrote: > Normally in order to generate the DDR stream I put ODDR or OSERDES > primitve but that goes out of the FPGA. =A0Is it possible to generate > double data rate stream in the Virtex4 fabric? =A0This is just for > getting better understanding of the V4 fabric is capable of. > > It seems that for my application I just need to remove the serial > comonents between design1 and design2 and run paralllel single data > rate interface between them did you try single IO loopback? use OSERDES and read back without IOB FF the same signal? then you should have the DDR signal back into FPGA without the need for soldering iron AnttiArticle: 142522
On Aug 14, 10:30=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Aug 14, 4:52=A0pm, Test01 <cpan...@yahoo.com> wrote: > > > Normally in order to generate the DDR stream I put ODDR or OSERDES > > primitve but that goes out of the FPGA. =A0Is it possible to generate > > double data rate stream in the Virtex4 fabric? =A0This is just for > > getting better understanding of the V4 fabric is capable of. > > > It seems that for my application I just need to remove the serial > > comonents between design1 and design2 and run paralllel single data > > rate interface between them > > did you try single IO loopback? > use OSERDES > and read back without IOB FF the same signal? > then you should have the DDR signal back into FPGA without the need > for soldering iron > > Antti This is a better solution. Internal loop-back is great.Article: 142523
Since fabric flops are SDR-only, you need a two bit encoding scheme
such that either bit can affect the decoded single bit output. XOR is
one common encoding scheme that has this behavior. XNOR is another.
Thus, you can emulate a DDR flop with two SDR flops (opposite edge
clocked) and three XOR gates.
process (clk, rst) is
begin
if rst then -- boolean rst
qr <= '0';
elsif rising_edge(clk) then
qr <= dr xor qf; -- registered encode
end if;
end process;
process (clk, rst) is
begin
if rst then
qf <= '0';
elsif falling_edge(clk) then
qf <= df xor qr; -- registered encode
end if;
end process;
q <= qr xor qf; -- combinatorial decode
Both dr and df can be driven by a single DDR signal, or separately
driven by SDR signals.
Or in several sythesis tools, you can roll it all into one process
using variables:
combined: process (clk, rst) is
variable qr, qf : std_logic;
begin
if rst then
qr := '0';
qf := '0';
elsif rising_edge(clk) then
qr := dr xor qf; -- registered encode
elsif falling_edge(clk) then
qf := df xor qr; -- registered encode
end if;
q <= qr xor qf; -- combinatorial decode
end process combined;
Andy
Article: 142524
DJ Delorie <dj@delorie.com> wrote:
>
>nico@puntnl.niks (Nico Coesel) writes:
>> 'TTL' logic will never go away. In most cases an FPGA is just way too
>> expensive. Many of the circuits I design just need a simple flipflop
>> or a single gate.
>
>I don't know about that... with CPLDs under $1 I see an opportunity
>for a company to produce a range of CPLDs that vary only in footprint
>and power connections, so that they can be used to replace anything
>else. It would be a handy RMA tool :-)
Ever looked at the price, size and power consumption of tiny logic in
a sot23-5 package?
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
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