Messages from 141350

Article: 141350
Subject: Re: set dont touch in Xilinx Xst
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 19 Jun 2009 12:31:53 -0700
Links: << >> << T >> << A >>

On Fri, 19 Jun 2009 07:49:15 -0700 (PDT), Serkan
<oktem@su.sabanciuniv.edu> wrote:

>Is there a "set_dont_touch" equaivalent version of Xilinx Xst
>attribute. Or is it only in synopsys?.

Serkan,

There are various attributes in Xst which, in combination, can give
you similar results: "keep", "keep_hierarchy",
"equivalent_register_removal". But usually it takes more effort than
an ASIC tool to keep things in XST.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Article: 141351
Subject: Preselection counter in verilog
From: "Dr. Thomas Ansorg" <dl7jsk@online.de>
Date: Fri, 19 Jun 2009 22:45:45 +0200
Links: << >> << T >> << A >>

Hello all!
I need a preselection counter that divides the 50 MHz clock of my 
Spartan-3E-board down to 20 MHz. Since I have no clue about verilog, only 
vhdl, would someone please post me the source code?

Tom

Article: 141352
Subject: Re: Virtex 2 Pro IO Banks Vcco
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Fri, 19 Jun 2009 13:49:20 -0700
Links: << >> << T >> << A >>

Manfred wrote:
> Hi all,
> I'm having the following problem: I'm trying to interface a XUP Virtex-II
> Pro Development System with a CMOS camera, and the output voltage on the
> board's expansion connectors is 2.5V for logic '1', no matter what
> IOSTANDARD is specified in the ucf file. I understand this is because the
> Vcco for the io bank is 2.5V. (However, in the schematic it shows that for
> the IO Banks that relate to the expansion connectors, Vcco=3.3V.)
> My question is if it possible to change the Vcco supply voltage by any
> sw/hw means.
> Thank you in advance.
> 

If you are using the LT_USER_IO, these pins are connected through an IDT 
Quickswitch device to FPGA.  The IDT QuickSwitch will clip the waveform 
at approximately VCC - 1V.  The board that you are using has VCC set to 
3.3V, so the output will be limited to ~2.3V under nominal conditions. 
Changing the VCC of the QuickSwitch can not be easily accomplished.

The HS_USER_IO are connected directly from the FPGA to the connector and 
would get you the 3.3V that you are looking for.

Ed McGettigan
--
Xilinx Inc.

Article: 141353
Subject: Lookup table in VHDL?
From: "John Speth" <johnspeth@yahoo.com>
Date: Fri, 19 Jun 2009 14:29:19 -0700
Links: << >> << T >> << A >>

Can anyone point me to a discussion or good example of a VHDL lookup table 
implementation that will work with Altium Designer?

I'm a newbie at VHDL programming.  I'm a long time expert at embedded SW.

I've searched the web but I can't find any good examples for Altium 
Designer.  Below is a great example that is targeted for a Xilinx FPGA and 
Xilinx library in which an existing library RAM part is called out and then 
it's followed by a table of initialization.  I think it's what I'm after but 
I don't have the knowledge to manipulate it correctly.

Thanks, John Speth.

Example follows:

module sine_tab ( clk, addr, out );
  input clk;
  input [9:0] addr;
  output [17:0] out;

  wire clk;
  wire [9:0] addr;
  wire [17:0] out;
  wire [15:0] DOA;
  wire [1:0] DOPA;

  assign out = {DOPA,DOA};

// Sine/Cosine Lookup Table init data for DDS
// Auto-generated by mk_sc_lut_param.c
// Dual port block RAM as ROM used because of address range.
// Clocks are not used.

  RAMB16_S18_S18 RAMB_SINE_TAB (
                 .DOA ( DOA ),
                 .DOB (),
                 .DOPA ( DOPA ),
                 .DOPB (),
                 .ADDRA ( addr ),
                 .ADDRB ( addr ),
                 .CLKA ( clk ),
                 .CLKB ( 1'b0 ),
                 .DIA ( 16'hFFFF ),
                 .DIB ( 16'hFFFF ),
                 .DIPA ( 2'b11 ),
                 .DIPB ( 2'b11 ),
                 .ENA ( 1'b1 ),
                 .ENB ( 1'b1 ),
                 .SSRA ( 1'b0 ),
                 .SSRB ( 1'b0 ),
                 .WEA ( 1'b0 ),
                 .WEB ( 1'b0 )
                 );

defparam RAMB_SINE_TAB.INIT_00 = 
256'h0C2C0B630A9A09D10908083F077606AD05E4051B0452038902C001F7012E0065;
defparam RAMB_SINE_TAB.INIT_01 = 
256'h18BB17F217291660159814CF1406133D127411AB10E210190F500E870DBE0CF5;
defparam RAMB_SINE_TAB.INIT_02 = 
256'h2546247D23B522EC2224215B20921FCA1F011E381D701CA71BDE1B151A4D1984;
defparam RAMB_SINE_TAB.INIT_03 = 
256'h31CB3103303B2F732EAA2DE22D1A2C522B892AC129F929302868279F26D7260E;
defparam RAMB_SINE_TAB.INIT_04 = 
256'h3E493D813CBA3BF23B2A3A62399B38D3380B3743367B35B334EB3423335B3293;
defparam RAMB_SINE_TAB.INIT_05 = 
256'h4ABD49F6492F486847A146DA4612454B448443BD42F5422E4167409F3FD83F10;
defparam RAMB_SINE_TAB.INIT_06 = 
256'h5725565F559954D2540C5346527F51B950F2502C4F654E9F4DD84D114C4A4B84;
defparam RAMB_SINE_TAB.INIT_07 = 
256'h638062BB61F66130606B5FA55EE05E1A5D545C8F5BC95B035A3D597758B157EB;
...etc....

Article: 141354
Subject: Re: Lookup table in VHDL?
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 19 Jun 2009 15:03:38 -0700
Links: << >> << T >> << A >>

John Speth wrote:
> Can anyone point me to a discussion or good example of a VHDL lookup table 

http://mysite.verizon.net/miketreseler/sync_rom.vhd

Article: 141355
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: lenz19@gmx.de
Date: Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
Links: << >> << T >> << A >>

Rob, John thanks for reply.


>> 2. R => not R, S => not S


That's the point.
Your suggestion would infer an inverter realized in a LUT.
I don't want to infer extra inverter logic in the CLB. I want the
inverter for free.

In the Storage Elements Section of the User Guide for Spartan it is
statet that
"All signals have programmable polarity; the default active-High
function is described."

So, I am looking for a way to configure the polarity of the set/reset
signals of a FDRSE.


>> Out of curiosity, why would you need to be directly instantiating flops?


I want to use the three inputs (set, reset and data) of the FDRSE at
the same time
without infering extra LUT-Logic.

Something like this:

Connect signal a to set-input, signal b to reset-input and signal c to
data-input.


Thanks for your contribution.

Article: 141356
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 19 Jun 2009 17:19:52 -0700
Links: << >> << T >> << A >>

On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
lenz19@gmx.de wrote:

> Rob, John thanks for reply.
> 
> 
> >> 2. R => not R, S => not S
> 
> 
> That's the point.
> Your suggestion would infer an inverter realized in a LUT.
> I don't want to infer extra inverter logic in the CLB. I want the
> inverter for free.
> 

That's why there's a synthesis tool that's able to perform
optimization.  Last I checked, if you go back in to the FPGA Editor
and look in on what you've got, you'll find that XST will very
happily have collapsed those inverters into the free ones built into
the slice.

You seem to be of the opinion that it's necessary for you to outsmart
the synthesis tools.  As I said earlier, it's really rarely the case.
If you code:

process(clk, r, s)
begin
  if (r = '1') then
    q <= '0';
  elsif (s = '1') then
    q <= '1';
  elseif rising_edge(clk) then
    q <= d;
  end if;
end process;

You'll find that the synthesis tool still gives you exactly what you
wanted, without you having to slog through unnecessary direct
instatiation.  The people telling you that it doesn't work haven't updated their opinions since the mid 1990s.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 141357
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: lenz19@gmx.de
Date: Fri, 19 Jun 2009 17:35:31 -0700 (PDT)
Links: << >> << T >> << A >>

On 20 Jun., 02:19, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
>
> len...@gmx.de wrote:
> > Rob, John thanks for reply.
>
> > >> 2. R =3D> not R, S =3D> not S
>
> > That's the point.
> > Your suggestion would infer an inverter realized in a LUT.
> > I don't want to infer extra inverter logic in the CLB. I want the
> > inverter for free.
>
> That's why there's a synthesis tool that's able to perform
> optimization. =A0Last I checked, if you go back in to the FPGA Editor
> and look in on what you've got, you'll find that XST will very
> happily have collapsed those inverters into the free ones built into
> the slice.
>
> You seem to be of the opinion that it's necessary for you to outsmart
> the synthesis tools. =A0As I said earlier, it's really rarely the case.
> If you code:
>
> process(clk, r, s)
> begin
> =A0 if (r =3D '1') then
> =A0 =A0 q <=3D '0';
> =A0 elsif (s =3D '1') then
> =A0 =A0 q <=3D '1';
> =A0 elseif rising_edge(clk) then
> =A0 =A0 q <=3D d;
> =A0 end if;
> end process;
>
> You'll find that the synthesis tool still gives you exactly what you
> wanted, without you having to slog through unnecessary direct
> instatiation. =A0The people telling you that it doesn't work haven't upda=
ted their opinions since the mid 1990s.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

I will try this and give you a feedback whether it worked or not.

Thank you for sharing your knowledge.

Article: 141358
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Sat, 20 Jun 2009 04:12:09 +0000 (UTC)
Links: << >> << T >> << A >>

On 2009-06-19, john <jprovidenza@yahoo.com> wrote:
> I believe XST will not directly infer DDR output flops.  At least it
> didn't used to be
> able to do this.  I've always had to instantiate DDR output flops.

Another reason to manually instantiate a flip-flop is when the synthesis tool
is doing something suboptimal. For example, I've noticed that XST relatively
often places my critical path on the SR input of flip-flops even though that
path is quite a bit slower than the D input. In those cases I usually
instantiate the flip-flop manually to control what is going on.

(It is possible that a synthesis keep option would also help here though instead
of manually instantiating the flip-flop.)

/Andreas

Article: 141359
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Fri, 19 Jun 2009 22:51:40 -0700
Links: << >> << T >> << A >>

Rob Gaddi wrote:
> On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
> lenz19@gmx.de wrote:
> 
>> Rob, John thanks for reply.
>>
>>
>>>> 2. R => not R, S => not S
>>
>> That's the point.
>> Your suggestion would infer an inverter realized in a LUT.
>> I don't want to infer extra inverter logic in the CLB. I want the
>> inverter for free.
>>
> 
> That's why there's a synthesis tool that's able to perform
> optimization.  Last I checked, if you go back in to the FPGA Editor
> and look in on what you've got, you'll find that XST will very
> happily have collapsed those inverters into the free ones built into
> the slice.
> 
> You seem to be of the opinion that it's necessary for you to outsmart
> the synthesis tools.  As I said earlier, it's really rarely the case.
> If you code:
> 
> process(clk, r, s)
> begin
>   if (r = '1') then
>     q <= '0';
>   elsif (s = '1') then
>     q <= '1';
>   elseif rising_edge(clk) then
>     q <= d;
>   end if;
> end process;
> 
> You'll find that the synthesis tool still gives you exactly what you
> wanted, without you having to slog through unnecessary direct
> instatiation.  The people telling you that it doesn't work haven't updated their opinions since the mid 1990s.
> 

The code above is not equivalent to FDRSE, but this code is:

process (clk)
begin
    if rising_edge(clk) then
      if (r = '1') then
         q <= '0';
      elsif (s = '1') then
         q <= '1';
      elsif (ce = '1') then
         q <= d;
      end if;
end process;

Ed McGettigan
--
Xilinx Inc.

Article: 141360
Subject: Re: Preselection counter in verilog (Verilog Version)
From: "Phil Jessop" <phil@noname.org>
Date: Sat, 20 Jun 2009 15:38:02 +0100
Links: << >> << T >> << A >>


"Dr. Thomas Ansorg" <dl7jsk@online.de> wrote in message 
news:h1gtdt$oig$1@online.de...
> Hello all!
> I need a preselection counter that divides the 50 MHz clock of my 
> Spartan-3E-board down to 20 MHz. Since I have no clue about verilog, only 
> vhdl, would someone please post me the source code?
>
> Tom
>
>

Sorry, this is Verilog version (other one was VHDL).




module Test006(
 CK_50MHz,
 CK_20MHz,
 Q
);


input CK_50MHz;
output CK_20MHz;
output [2:0] Q;

wire [2:0] Q_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_2;
reg SYNTHESIZED_WIRE_4;





lpm_counter1 b2v_inst(
 .clock(SYNTHESIZED_WIRE_3),
 .q(Q_ALTERA_SYNTHESIZED));


always@(posedge SYNTHESIZED_WIRE_3)
begin
 begin
 SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_2;
 end
end

assign SYNTHESIZED_WIRE_3 = CK_50MHz ^ SYNTHESIZED_WIRE_4;

assign SYNTHESIZED_WIRE_2 =  ~SYNTHESIZED_WIRE_4;

assign CK_20MHz = Q_ALTERA_SYNTHESIZED[2];


assign Q = Q_ALTERA_SYNTHESIZED;

endmodule




Phil

Article: 141361
Subject: Re: Lookup table in VHDL?
From: "John Speth" <johnspeth@yahoo.com>
Date: Sat, 20 Jun 2009 15:19:26 GMT
Links: << >> << T >> << A >>


"Mike Treseler" <mtreseler@gmail.com> wrote in message 
news:7a2g9qF1t3fvsU1@mid.individual.net...
> John Speth wrote:
>> Can anyone point me to a discussion or good example of a VHDL lookup 
>> table
>
> http://mysite.verizon.net/miketreseler/sync_rom.vhd

Thanks Mike!  Just what I needed.

Article: 141362
Subject: TimingAnalyzer is now freeware
From: timinganalyzer <timinganalyzer@gmail.com>
Date: Sat, 20 Jun 2009 08:51:43 -0700 (PDT)
Links: << >> << T >> << A >>

Hi All,

I just wanted to let you know that the TimingAnalyzer is now licensed
as freeware.   I just don't have the time needed to make a high
quality commercial product but I do want to keep the development
moving forward and continue to fix problems and add new features as
time permits.

Recently, I have become very interested in Python and using it to
develop similar type cad programs.  My plan is to convert the
TimingAnalyzer Java to Python with mostly a scripting interface for
building complex timing diagrams, doing timing analysis,  creating
testbenches and testvectors from waveform diagrams,
and creating timing diagrams from simulation VCD files.  Most all of
this is text based work anyway.

Developing professional GUIs is very time consuming for me.  This has
been my bottleneck with the program all along.  With a command line
interface,  you will execute a script and in one window,  and view and
edit and print the timing diagram shown in another window.   Like
Matlab interface.

If anyone is interested in helping with the development,  I will make
this an open source project.   Just let me know if your interested.

Thanks,
Dan Fabrizio

Article: 141363
Subject: Re: Preselection counter in verilog (Verilog Version)
From: "Dr. Thomas Ansorg" <dl7jsk@online.de>
Date: Sat, 20 Jun 2009 18:03:19 +0200
Links: << >> << T >> << A >>

Thanx!

Article: 141364
Subject: How to access Plx 8311 doorbell register?
From: "john.lv" <guochenglv@gmail.com>
Date: Sat, 20 Jun 2009 09:21:39 -0700 (PDT)
Links: << >> << T >> << A >>

hi all,
   I use 8311 to bridge the Local bus and the PCIe. I want to access
the doorbell registers with FPGA. I have read the data sheet, and did
as the datasheet mentioned. However, it still can't work.
did anybody do same work before? Please give me some advice.
thanks a lot!

Article: 141365
Subject: Re: TimingAnalyzer is now freeware
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Sat, 20 Jun 2009 09:24:37 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 20, 6:51=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote:
> Hi All,
>
> I just wanted to let you know that the TimingAnalyzer is now licensed
> as freeware. =A0 I just don't have the time needed to make a high
> quality commercial product but I do want to keep the development
> moving forward and continue to fix problems and add new features as
> time permits.
>
> Recently, I have become very interested in Python and using it to
> develop similar type cad programs. =A0My plan is to convert the
> TimingAnalyzer Java to Python with mostly a scripting interface for
> building complex timing diagrams, doing timing analysis, =A0creating
> testbenches and testvectors from waveform diagrams,
> and creating timing diagrams from simulation VCD files. =A0Most all of
> this is text based work anyway.
>
> Developing professional GUIs is very time consuming for me. =A0This has
> been my bottleneck with the program all along. =A0With a command line
> interface, =A0you will execute a script and in one window, =A0and view an=
d
> edit and print the timing diagram shown in another window. =A0 Like
> Matlab interface.
>
> If anyone is interested in helping with the development, =A0I will make
> this an open source project. =A0 Just let me know if your interested.
>
> Thanks,
> Dan Fabrizio

a link to your webpage would help
(for those who are lazy)

Antti

Article: 141366
Subject: Re: TimingAnalyzer is now freeware
From: chewie <timinganalyzer@gmail.com>
Date: Sat, 20 Jun 2009 10:28:48 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 20, 12:24=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jun 20, 6:51=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote:
>
>
>
> > Hi All,
>
> > I just wanted to let you know that the TimingAnalyzer is now licensed
> > as freeware. =A0 I just don't have the time needed to make a high
> > quality commercial product but I do want to keep the development
> > moving forward and continue to fix problems and add new features as
> > time permits.
>
> > Recently, I have become very interested in Python and using it to
> > develop similar type cad programs. =A0My plan is to convert the
> > TimingAnalyzer Java to Python with mostly a scripting interface for
> > building complex timing diagrams, doing timing analysis, =A0creating
> > testbenches and testvectors from waveform diagrams,
> > and creating timing diagrams from simulation VCD files. =A0Most all of
> > this is text based work anyway.
>
> > Developing professional GUIs is very time consuming for me. =A0This has
> > been my bottleneck with the program all along. =A0With a command line
> > interface, =A0you will execute a script and in one window, =A0and view =
and
> > edit and print the timing diagram shown in another window. =A0 Like
> > Matlab interface.
>
> > If anyone is interested in helping with the development, =A0I will make
> > this an open source project. =A0 Just let me know if your interested.
>
> > Thanks,
> > Dan Fabrizio
>
> a link to your webpage would help
> (for those who are lazy)
>
> Antti

Sorry about that.   The website is:

www.timing-diagrams.com

Article: 141367
Subject: Re: TimingAnalyzer is now freeware
From: Benjamin Krill <ben@codiert.org>
Date: Sat, 20 Jun 2009 19:33:30 +0200
Links: << >> << T >> << A >>

Hi Dan,


> > > Developing professional GUIs is very time consuming for me.  This has
> > > been my bottleneck with the program all along.  With a command line
> > > interface,  you will execute a script and in one window,  and view and
> > > edit and print the timing diagram shown in another window.   Like
> > > Matlab interface.

This descriptions sounds somehow like a program I used some time ago. Of
course not with the analyzing options you have implemented in your
TimingAnalyzer tool. 

http://drawtiming.sourceforge.net/

cheers
 ben

Article: 141368
Subject: Re: TimingAnalyzer is now freeware
From: chewie <timinganalyzer@gmail.com>
Date: Sat, 20 Jun 2009 10:51:38 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 20, 1:33=A0pm, Benjamin Krill <b...@codiert.org> wrote:
> Hi Dan,
>
> > > > Developing professional GUIs is very time consuming for me. =A0This=
 has
> > > > been my bottleneck with the program all along. =A0With a command li=
ne
> > > > interface, =A0you will execute a script and in one window, =A0and v=
iew and
> > > > edit and print the timing diagram shown in another window. =A0 Like
> > > > Matlab interface.
>
> This descriptions sounds somehow like a program I used some time ago. Of
> course not with the analyzing options you have implemented in your
> TimingAnalyzer tool.
>
> http://drawtiming.sourceforge.net/
>
> cheers
> =A0ben

Hi ben,

I did see that before and that is similar but my approach will be much
more
higher level thus easier.

For example:

micro =3D m68000()
micro.write(add, data, wait_states)
micro.read(add, wait_states).

or

add_clock(......)
add_signal(.....)
add_delay(......)
add_constraint(.....)
add_or_gate(....)
add_and_gate(....)
add_counter(....)
add_clock_jitter(.....)

analyze_clock_domains(.....)
analyze_worst_case_timings(....)
analyze_best_case_timings.

read_vcd(....)
vcd_2_timing_diagram(.....)
create_testvectors(.....)
create_testbench(....)

A lot of these functions are built into the program now so its a
matter of converting them java to python.  I won't have to spend most
of the time getting the user interface to look good and be friendly.
If this is made an open source project,  I would hope that others
would help with the development and new features and bug fixes will
happen very quickly.

-Dan

Article: 141369
Subject: Re: TimingAnalyzer is now freeware
From: OutputLogic <evgenist@gmail.com>
Date: Sat, 20 Jun 2009 18:37:10 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 20, 10:51=A0am, chewie <timinganaly...@gmail.com> wrote:
> On Jun 20, 1:33=A0pm, Benjamin Krill <b...@codiert.org> wrote:
>
>
>
>
>
> > Hi Dan,
>
> > > > > Developing professional GUIs is very time consuming for me. =A0Th=
is has
> > > > > been my bottleneck with the program all along. =A0With a command =
line
> > > > > interface, =A0you will execute a script and in one window, =A0and=
 view and
> > > > > edit and print the timing diagram shown in another window. =A0 Li=
ke
> > > > > Matlab interface.
>
> > This descriptions sounds somehow like a program I used some time ago. O=
f
> > course not with the analyzing options you have implemented in your
> > TimingAnalyzer tool.
>
> >http://drawtiming.sourceforge.net/
>
> > cheers
> > =A0ben
>
> Hi ben,
>
> I did see that before and that is similar but my approach will be much
> more
> higher level thus easier.
>
> For example:
>
> micro =3D m68000()
> micro.write(add, data, wait_states)
> micro.read(add, wait_states).
>
> or
>
> add_clock(......)
> add_signal(.....)
> add_delay(......)
> add_constraint(.....)
> add_or_gate(....)
> add_and_gate(....)
> add_counter(....)
> add_clock_jitter(.....)
>
> analyze_clock_domains(.....)
> analyze_worst_case_timings(....)
> analyze_best_case_timings.
>
> read_vcd(....)
> vcd_2_timing_diagram(.....)
> create_testvectors(.....)
> create_testbench(....)
>
> A lot of these functions are built into the program now so its a
> matter of converting them java to python. =A0I won't have to spend most
> of the time getting the user interface to look good and be friendly.
> If this is made an open source project, =A0I would hope that others
> would help with the development and new features and bug fixes will
> happen very quickly.
>
> -Dan


I agree. This could grow into a quite useful tool.

- outputlogic

http://outputlogic.com

Article: 141370
Subject: Re: FDRSE Spartan 3A - Active high/low set/reset
From: lenz19@gmx.de
Date: Sun, 21 Jun 2009 07:05:58 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 20, 7:51=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> Rob Gaddi wrote:
> > On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
> > len...@gmx.de wrote:
>
> >> Rob, John thanks for reply.
>
> >>>> 2. R =3D> not R, S =3D> not S
>
> >> That's the point.
> >> Your suggestion would infer an inverter realized in a LUT.
> >> I don't want to infer extra inverter logic in the CLB. I want the
> >> inverter for free.
>
> > That's why there's a synthesis tool that's able to perform
> > optimization. =A0Last I checked, if you go back in to the FPGA Editor
> > and look in on what you've got, you'll find that XST will very
> > happily have collapsed those inverters into the free ones built into
> > the slice.
>
> > You seem to be of the opinion that it's necessary for you to outsmart
> > the synthesis tools. =A0As I said earlier, it's really rarely the case.
> > If you code:
>
> > process(clk, r, s)
> > begin
> > =A0 if (r =3D '1') then
> > =A0 =A0 q <=3D '0';
> > =A0 elsif (s =3D '1') then
> > =A0 =A0 q <=3D '1';
> > =A0 elseif rising_edge(clk) then
> > =A0 =A0 q <=3D d;
> > =A0 end if;
> > end process;
>
> > You'll find that the synthesis tool still gives you exactly what you
> > wanted, without you having to slog through unnecessary direct
> > instatiation. =A0The people telling you that it doesn't work haven't up=
dated their opinions since the mid 1990s.
>
> The code above is not equivalent to FDRSE, but this code is:
>
> process (clk)
> begin
> =A0 =A0 if rising_edge(clk) then
> =A0 =A0 =A0 if (r =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D '0';
> =A0 =A0 =A0 elsif (s =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D '1';
> =A0 =A0 =A0 elsif (ce =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D d;
> =A0 =A0 =A0 end if;
> end process;
>
> Ed McGettigan
> --
> Xilinx Inc.- Hide quoted text -
>
> - Show quoted text -

That code worked. It describes a FDRSE with high-active set/reset.

If you change your code to this:

 process (clk)
 begin
     if rising_edge(clk) then
       if (r =3D '0') then
          q <=3D '0';
       elsif (s =3D '0') then
          q <=3D '1';
       elsif (ce =3D '1') then
          q <=3D d;
       end if;
 end process;

it becomes a FDRSE with low-active set/reset without LUT-Logic for the
inverter.

Article: 141371
Subject: Subtleties of Booth's Algorithm Implementation
From: rickman <gnuarm@gmail.com>
Date: Sun, 21 Jun 2009 15:27:09 -0700 (PDT)
Links: << >> << T >> << A >>

I needed a multiplier in a small footprint and Booth's Algorithm
seemed the appropriate approach since the numbers were signed.  I
looked up multiple references on the web (isn't that where all
knowledge is to be found?) and to make sure I understood the
algorithm, I jimmied up a version is Excel.  I thought I was having a
problem with the way I was building it Excel (it really shouldn't be
anyone's first choice for this sort of task...) as I could not get it
to work for all inputs.  I could get it to work for all multiplicands
other than -2**n-1.  Finally, I realized that ***NONE*** of the many
examples I found on the web were correct!  In order to work for all
inputs, the implementation has to allow for a -2**n-1 to be negated to
2**n-1 which requires an extra bit in the arithmetic!

Some examples do it all numerically, so you don't see this at all.
Others even combine the multiplier with the product to save register
bits, still, they don't add the extra bit at the msb.  I guess they
never tried their examples with -2**n-1 as a multiplicand...

It took me quite a while to realize this was the problem and not my
simulation.  Is this extra bit obvious to everyone or am I just a bit
slower than most?

Rick

Article: 141372
Subject: Re: Subtleties of Booth's Algorithm Implementation
From: Muzaffer Kal <kal@dspia.com>
Date: Sun, 21 Jun 2009 20:28:23 -0700
Links: << >> << T >> << A >>

On Sun, 21 Jun 2009 15:27:09 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:

>I needed a multiplier in a small footprint and Booth's Algorithm
>seemed the appropriate approach since the numbers were signed.  I
>looked up multiple references on the web (isn't that where all
>knowledge is to be found?) and to make sure I understood the
>algorithm, I jimmied up a version is Excel.  I thought I was having a
>problem with the way I was building it Excel (it really shouldn't be
>anyone's first choice for this sort of task...) as I could not get it
>to work for all inputs.  I could get it to work for all multiplicands
>other than -2**n-1.  Finally, I realized that ***NONE*** of the many
>examples I found on the web were correct!  In order to work for all
>inputs, the implementation has to allow for a -2**n-1 to be negated to
>2**n-1 which requires an extra bit in the arithmetic!
>

Assuming n is the number of bits of the inputs I think you mean
-2**(n-1) right? ie -8 = -2**3 is the most negative 4 bit two's
complement number. When two n bit numbers are multiplied you get a 2n
bit number. Continuing with our example, the number pair which
generates a sign inversion and largest magnitute change is -8 x -8 or
+64 ie 1000 x 1000 = 01000000. So the result of most negative n bit
number squared fits into the 2n bit result. So far I don't see a need
for any extra bits needed but I maybe missing something from your
description.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Article: 141373
Subject: Re: Subtleties of Booth's Algorithm Implementation
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sun, 21 Jun 2009 21:24:04 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 21, 8:28 pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Sun, 21 Jun 2009 15:27:09 -0700 (PDT), rickman <gnu...@gmail.com>
> wrote:
>
> >I needed a multiplier in a small footprint and Booth's Algorithm
> >seemed the appropriate approach since the numbers were signed.  I
> >looked up multiple references on the web (isn't that where all
> >knowledge is to be found?) and to make sure I understood the
> >algorithm, I jimmied up a version is Excel.  I thought I was having a
> >problem with the way I was building it Excel (it really shouldn't be
> >anyone's first choice for this sort of task...) as I could not get it
> >to work for all inputs.  I could get it to work for all multiplicands
> >other than -2**n-1.  Finally, I realized that ***NONE*** of the many
> >examples I found on the web were correct!  In order to work for all
> >inputs, the implementation has to allow for a -2**n-1 to be negated to
> >2**n-1 which requires an extra bit in the arithmetic!
>
> Assuming n is the number of bits of the inputs I think you mean
> -2**(n-1) right? ie -8 =3D -2**3 is the most negative 4 bit two's
> complement number. When two n bit numbers are multiplied you get a 2n
> bit number. Continuing with our example, the number pair which
> generates a sign inversion and largest magnitute change is -8 x -8 or
> +64 ie 1000 x 1000 =3D 01000000. So the result of most negative n bit
> number squared fits into the 2n bit result. So far I don't see a need
> for any extra bits needed but I maybe missing something from your
> description.
>
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com

Hi Rick,
The following context may give you a help you may need.

Find 3 =D7 -4, with m =3D 3 and r =3D -4, and x =3D 4 and y =3D 4:

A =3D 0011 0000 0
S =3D 1101 0000 0
P =3D 0000 1100 0
Perform the loop four times :
P =3D 0000 1100 0. The last two bits are 00.
P =3D 0000 0110 0. Arithmetic right shift.
P =3D 0000 0110 0. The last two bits are 00.
P =3D 0000 0011 0. Arithmetic right shift.
P =3D 0000 0011 0. The last two bits are 10.
P =3D 1101 0011 0. P =3D P + S.
P =3D 1110 1001 1. Arithmetic right shift.
P =3D 1110 1001 1. The last two bits are 11.
P =3D 1111 0100 1. Arithmetic right shift.
The product is 1111 0100, which is -12.
The above mentioned technique is inadequate when the multiplicand is
the largest negative number that can be represented (i.e. if the
multiplicand has 8 bits then this value is -128). One possible
correction to this problem is to add one more bit to the left of A, S
and P. Below, we demonstrate the improved technique by multiplying -8
by 2 using 4 bits for the multiplicand and the multiplier:

A =3D 1 1000 0000 0
S =3D 0 1000 0000 0
P =3D 0 0000 0010 0
Perform the loop four times :
P =3D 0 0000 0010 0. The last two bits are 00.
P =3D 0 0000 0001 0. Right shift.
P =3D 0 0000 0001 0. The last two bits are 10.
P =3D 0 1000 0001 0. P =3D P + S.
P =3D 0 0100 0000 1. Right shift.
P =3D 0 0100 0000 1. The last two bits are 01.
P =3D 1 1100 0000 1. P =3D P + A.
P =3D 1 1110 0000 0. Right shift.
P =3D 1 1110 0000 0. The last two bits are 00.
P =3D 0 1111 0000 0. Right shift.
The product is 11110000 (after discarding the first and the last bit)
which is -16.

It is copied from http://en.wikipedia.org/wiki/Booth_algorithm.

There is no modified Booth algorithm in wikipedia and you may have to
figure out how to adopt it to modified Booth algorithm.

Weng

Article: 141374
Subject: Re: set dont touch in Xilinx Xst
From: Serkan <oktem@su.sabanciuniv.edu>
Date: Sun, 21 Jun 2009 23:40:23 -0700 (PDT)
Links: << >> << T >> << A >>

On Jun 19, 10:31=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Fri, 19 Jun 2009 07:49:15 -0700 (PDT), Serkan
>
> <ok...@su.sabanciuniv.edu> wrote:
  thank you for your answer

  best regards



> >Is there a "set_dont_touch" equaivalent version of Xilinx Xst
> >attribute. Or is it only in synopsys?.
>
> Serkan,
>
> There are various attributes in Xst which, in combination, can give
> you similar results: "keep", "keep_hierarchy",
> "equivalent_register_removal". But usually it takes more effort than
> an ASIC tool to keep things in XST.
>
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com

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