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On Jul 2, 1:31=C2=A0pm, rickman <gnu...@gmail.com> wrote: > On Jul 2, 7:59=C2=A0am, Simon <wlpstx...@gmail.com> wrote: > > > Hi, guys, > > > I have been several years experience on FPGA networking application > > design, but I come up with the a question about math operation in > > FPGA. I need to perform Integral operation. I don't know if there is > > existing library which offer this function, or DSP? I think the last > > option is to run the integral library in the embedded PowerPC in > > Xilinx FPGA, but don't know how the performance is. Could anybody > > indicate how to achieve this goal? > > > Many thanks, > > > Yixuan > > An integral using continuous variables is essentially a multiply > operation with a continuous sum performed by an "integrator" circuit. > When using discrete time variable in digital logic, the multiply is > straight forward and often omitted since that is just a scale factor > and can be done elsewhere. =C2=A0The sum is now discrete and is a simple > matter of a continuous accumulation using an... accumulator. > > If you can provide some details of your signal and exactly what you > want to do, maybe we can give some additional advice? > > Rick Hi=EF=BC=8CRick, Regarding the integral I'm using it goes something like that: If f(x) is the function to be integrated then q =3D quadl(@(x) f(x),a,b,tol), where quadl approximately integrates the f(x) from a to b using an error tolerance tol. YixuanArticle: 141676
On Jul 3, 4:08=A0am, "Sundar S" <krishna....@gmail.com> wrote: > >On Jul 2, 7:59=3DA0am, Simon <wlpstx...@gmail.com> wrote: > >> Hi, guys, > > >> I have been several years experience on FPGA networking application > >> design, but I come up with the a question about math operation in > >> FPGA. I need to perform Integral operation. I don't know if there is > >> existing library which offer this function, or DSP? I think the last > >> option is to run the integral library in the embedded PowerPC in > >> Xilinx FPGA, but don't know how the performance is. Could anybody > >> indicate how to achieve this goal? > > >> Many thanks, > > >> Yixuan > > >An integral using continuous variables is essentially a multiply > >operation with a continuous sum performed by an "integrator" circuit. > >When using discrete time variable in digital logic, the multiply is > >straight forward and often omitted since that is just a scale factor > >and can be done elsewhere. =A0The sum is now discrete and is a simple > >matter of a continuous accumulation using an... accumulator. > > >If you can provide some details of your signal and exactly what you > >want to do, maybe we can give some additional advice? > > >Rick > > Integration is not just about summation of the discrete values. It could > also mean finding the area of the region encompassed by the given numbers > in Cartesian coordinates. Yixuan, if that's what you are looking for, you > may have to implement some adaptive quadrature algorithm. > The simplest way is to calculate the area as the curve builds for each an= d > every clock signal. Assuming that clock goes at the rate of one unit in > x-axis, you would need to evaluate int(n) =3D int(n-1) + 0.5 * diff(f(n), > f(n-1)) + min(f(n), f(n-1)), where f(n) is your function value at the nth > clock. > > http://sunnyeves.blogspot.com/ Hi, Sundar, I am thinking to use Xilinx Multiply Accumulator (MAC) core http://www.xilinx.com/support/documentation/ip_documentation/mac.pdf to do the integral. I don't know if it's feasible, or has anybody done this, or have better option. Thanks, YixuanArticle: 141677
I am trying to write a testbench using OVM. I am using HDL designer with Questsim. The problem I have is that when I compile a package using HDL designer I get the following error. ** Error: C:/HDS/ddr2/test_lib/hdl/xactr/pkt_driver.svh(10): near "#": syntax error, unexpected '#', expecting "IDENTIFIER" or '=' The problem seems to be related to the following statement :- ovm_blocking_get_port #(Packet) in_p; However if I open up Questsim and compile the sources there is no problem. So it seems to be something related to HDL designer that I have missed. The OVM package compiles fine and I have added the search path for the include files for the compilation so I am struggling to see what the problem is. Cheers JonArticle: 141678
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:-YKdnQ3GO8H2QNDXnZ2dnUVZ_q-dnZ2d@giganews.com... >I am trying to write a testbench using OVM. I am using HDL designer with > Questsim. The problem I have is that when I compile a package using HDL > designer I get the following error. > > ** Error: C:/HDS/ddr2/test_lib/hdl/xactr/pkt_driver.svh(10): near "#": > syntax error, unexpected '#', expecting "IDENTIFIER" or '=' > > The problem seems to be related to the following statement :- > > ovm_blocking_get_port #(Packet) in_p; > > However if I open up Questsim and compile the sources there is no problem. > So it seems to be something related to HDL designer that I have missed. The > OVM package compiles fine and I have added the search path for the include > files for the compilation so I am struggling to see what the problem is. > > Cheers > > Jon Try turning off the HDS parser checking under Options->Main->checks tab. The HDS SV parser is not as good as the Questa one. Hans www.ht-lab.comArticle: 141679
I have just found the solution from looking in the manual. It seems that OVM ships with two versions of ovm_pkg and you need to delete one of them to make it compile correctly. One of the ovm_pkg files is for simulators that dont support parameterisex classes so that is the reason for the error message.Article: 141680
On 3 Temmuz, 11:55, "The Lord of War" <maa105....@gmail.com> wrote: > eh no for what no for I cant use the sram that is onboard or no I have to > do some fancy stuff and calls to be able to use them? and if so what do i > need to do? > > thanks You have to observe the datasheet of the SRAM, the input output timing diagram, the connections between the SRAM and the FPGA. The array solution is not a logical solution since by creating an array you can not reach to the SRAM it only tries to create a memory inside the FPGA which will not be synthesizable.Article: 141681
On 20 June, 16:51, timinganalyzer <timinganaly...@gmail.com> wrote: > Hi All, > > I just wanted to let you know that the TimingAnalyzer is now licensed > as freeware. =A0 I just don't have the time needed to make a high > quality commercial product but I do want to keep the development > moving forward and continue to fix problems and add new features as > time permits. > > Recently, I have become very interested in Python and using it to > develop similar type cad programs. =A0My plan is to convert the > TimingAnalyzer Java to Python with mostly a scripting interface for > building complex timing diagrams, doing timing analysis, =A0creating > testbenches and testvectors from waveform diagrams, > and creating timing diagrams from simulation VCD files. =A0Most all of > this is text based work anyway. > > Developing professional GUIs is very time consuming for me. =A0This has > been my bottleneck with the program all along. =A0With a command line > interface, =A0you will execute a script and in one window, =A0and view an= d > edit and print the timing diagram shown in another window. =A0 Like > Matlab interface. > > If anyone is interested in helping with the development, =A0I will make > this an open source project. =A0 Just let me know if your interested. I prefer command-line interfaces in general. They are more flexible and can be automated. Good choice to move to Python as long as the speed holds up. You may want to inclulde comp.lang.python. JamesArticle: 141682
Rick, > 2) recompile all modules Sometimes "recompile all modules" may not work first time if the order of compilation has not been set properly. /MikhailArticle: 141683
"The Lord of War" <maa105.aub@gmail.com> wrote in message news:lIqdnYYs39EeWtDXnZ2dnUVZ_sGdnZ2d@giganews.com... > eh no for what no for I cant use the sram that is onboard or no I have to > do some fancy stuff and calls to be able to use them? and if so what do i > need to do? No, the fpga doesn't of itself know about the board. It doesn't know about the devices on the board. And it doesn't know the minutiae of operation of the devices on the board. As to what to do, it depends on what you're trying to do. An embedded system can use the Xilinx EDK to interface with the device, attach it to the peripheral bus, assign it room in the memory space, and build drivers to access and control the device from software. For a hardware only solution, start with the device's datasheet, and build the interface circuitry in the fpga. The "process" you can "call" to work with the device might already exist. They're more generally referred to as IP Cores. I expect you'll find the required IP Cores in the Xilinx tools. "Fancy stuff" on the fpga is more properly thought of as describing and connecting circuitry. It is not software "calls" using a strange new programming language. I hope you'll find that distinction helpful.Article: 141684
On Jul 2, 8:23=A0pm, steve <st...@aol.com> wrote: > On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote > (in article > <68320efd-477b-4818-95dd-d4639d7e2...@n19g2000vba.googlegroups.com>): > > > > > On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > >> On Jun 28, 5:09=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > > >>> Group for People Involved In the Design and Verification of FPGA's, > >>> other Programmable Logic , and CPLD's to Exchange Idea's and > >>> Techniques. You should have FPGA / CPLD Design / Verification on your > >>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to > >>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > >>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > >>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > >>> Synopsys, Aldec, NI, Altium, and Many Others. > > >>> Networking on LinkedIn can be a way to get technical questions > >>> answered. It can also be a way to meet contacts with expertise in > >>> other domains of knowledge other than your own. Additionally, many > >>> career enhancing contacts, and mentors can potentially found > >>> especially if one is at a smaller company that lacks the resources fo= r > >>> extensive internal networking. > > >>>http://www.linkedin.com/groups?about=3D&gid=3D56713 > > >>> Website:https://sites.google.com/site/fpgacpldgroup/ > > >> could you describe the last technical FPGA related question > >> that your linkedin networking group solved? > > >> unless you are able todo that, i see you repeated postings > >> to c.a.f. as complete spam > > >> Antti > > > Hi, I am one of the moderators at this group and I must be honest > > about it. =A0It is not a very technically oriented group. =A0I have tri= ed > > to make some technically oriented posts there with few responses. > > This did not seem to stimulate much in the way of subsequent new > > topics either. =A0I have also made an effort to separate the technical > > content from the recruiting content and gotten feedback that the > > recruiters are the ones paying the way for LinkedIn and cutting them > > out would be a mistake. > > > So I have given up on this group as well as other FPGA related groups > > at LinkedIn. =A0I have not removed myself from membership, but I can't > > say I recommend them unless you wish to use it for employment or self > > promotion. > > > Rick > > =A0I'm completely confused as to how you can have a FPGA =A0group that is= not =A0 > "technically orientated" , it would be like having a flower arranging cla= ss > without the flowers. There are other aspects to any occupation than just the technical issues. LinkedIn is oriented toward the business issues such as getting a job or filling a job. As much as I would like to see it be more technical, it seems like it is pretty firmly rooted in networking with technical discussions being secondary. Is it really that odd to consider? RickArticle: 141685
On Jul 2, 6:18=A0am, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi everybody, > I have to develop in quite a short time a quite complicated USB IP > core. > Can any body advice me which books to buy? > I began studying the USB2.0 spec but as you understand it's a spec and > it's quitly complicated to read for a newcomer > > Thanks in advance! Take a look at "USB Complete" by Jan Axelson. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 141686
On Jul 3, 9:18=A0am, James Harris <james.harri...@googlemail.com> wrote: > On 20 June, 16:51, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > > Hi All, > > > I just wanted to let you know that the TimingAnalyzer is now licensed > > as freeware. =A0 I just don't have the time needed to make a high > > quality commercial product but I do want to keep the development > > moving forward and continue to fix problems and add new features as > > time permits. > > > Recently, I have become very interested in Python and using it to > > develop similar type cad programs. =A0My plan is to convert the > > TimingAnalyzer Java to Python with mostly a scripting interface for > > building complex timing diagrams, doing timing analysis, =A0creating > > testbenches and testvectors from waveform diagrams, > > and creating timing diagrams from simulation VCD files. =A0Most all of > > this is text based work anyway. > > > Developing professional GUIs is very time consuming for me. =A0This has > > been my bottleneck with the program all along. =A0With a command line > > interface, =A0you will execute a script and in one window, =A0and view = and > > edit and print the timing diagram shown in another window. =A0 Like > > Matlab interface. > > > If anyone is interested in helping with the development, =A0I will make > > this an open source project. =A0 Just let me know if your interested. > > I prefer command-line interfaces in general. They are more flexible > and can be automated. > > Good choice to move to Python as long as the speed holds up. You may > want to inclulde comp.lang.python. > > James Thanks James. I did post a similar message on comp.lang.python. If there are some speed bottlenecks in Python, there is always the option of writing only those parts in a C extension.Article: 141687
In my design, I used the MIG2.3 DDR2 IP Core. In customization, I chose not to include the DCM inside, and I provide all the necessary clocks needed by the IP Core. Now the problem comes at the PAR stage. There is a new PAR warning: WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 =3D MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_clk0 * 4; ignored during timing analysis. This warning is related with the following UCF constraint: INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM =3D "TNM_PHY_INIT_DATA_SEL"; TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" =3D FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS "TS_SYS_clk0" * 4; And I am confused because when choosing DCM inside the IPCore would not cause this constraint to fail. There is something stranger that I checked the signal =91*/u_phy_init/u_ff_phy_init_data_sel=92, and I found that this signal will never drive any BRAMs. Did I get it right or there is some other points beyond my understanding.Article: 141688
MM wrote:
> Sometimes "recompile all modules" may not work first time if the order of
> compilation has not been set properly.
With vhdl-mode,
right-click, Speedbar, Generate Makefile
right-click, Speedbar, Make
does the trick.
-- Mike Treseler
Article: 141689
nachum wrote:
> I understand how to get it to run by using a .do file,
That's the easiest way I know to do it.
Write it once and use it a thousand times.
I use the modelsim gui to debug my work.
When I'm finished, I have a single shell command
that returns pass or fail.
-- Mike Treseler
Article: 141690"Derek Wallace" <del.wallace@gmail.com> wrote in message news:4A4D0A90.6030300@gmail.com... > Have a look at the tool from Duolog called Bitwise. Is a commercial > product > http://www.duolog.com/ > The price is not advertised, which usually means very expensive... /MikhailArticle: 141691
"rickman" <gnuarm@gmail.com> wrote in message news:8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com... On Jul 2, 8:23 pm, steve <st...@aol.com> wrote: > > There are other aspects to any occupation than just the technical > issues. LinkedIn is oriented toward the business issues such as > getting a job or filling a job. As much as I would like to see it be > more technical, it seems like it is pretty firmly rooted in networking > with technical discussions being secondary. > > Is it really that odd to consider? > > Rick A bigger problem is how technical discussions are set up (or at least used to be set up when I last looked) and viewed on LinkedIn. Answering questions is supposed to earn you points to improve your image. The questions remain active for only limited period of time upon expiration of which no one can contribute. Finally, you need to be a premium (read paid) member to be able to send a private message to another member. /MikhailArticle: 141692
On Jul 2, 11:08 pm, "Sundar S" <krishna....@gmail.com> wrote: > >On Jul 2, 7:59=A0am, Simon <wlpstx...@gmail.com> wrote: > >> Hi, guys, > > >> I have been several years experience on FPGA networking application > >> design, but I come up with the a question about math operation in > >> FPGA. I need to perform Integral operation. I don't know if there is > >> existing library which offer this function, or DSP? I think the last > >> option is to run the integral library in the embedded PowerPC in > >> Xilinx FPGA, but don't know how the performance is. Could anybody > >> indicate how to achieve this goal? > > >> Many thanks, > > >> Yixuan > > >An integral using continuous variables is essentially a multiply > >operation with a continuous sum performed by an "integrator" circuit. > >When using discrete time variable in digital logic, the multiply is > >straight forward and often omitted since that is just a scale factor > >and can be done elsewhere. The sum is now discrete and is a simple > >matter of a continuous accumulation using an... accumulator. > > >If you can provide some details of your signal and exactly what you > >want to do, maybe we can give some additional advice? > > >Rick > > Integration is not just about summation of the discrete values. It could > also mean finding the area of the region encompassed by the given numbers > in Cartesian coordinates. Yixuan, if that's what you are looking for, you > may have to implement some adaptive quadrature algorithm. > The simplest way is to calculate the area as the curve builds for each and > every clock signal. Assuming that clock goes at the rate of one unit in > x-axis, you would need to evaluate int(n) = int(n-1) + 0.5 * diff(f(n), > f(n-1)) + min(f(n), f(n-1)), where f(n) is your function value at the nth > clock. > > http://sunnyeves.blogspot.com/ That calculation looks complex, but isn't it really just int(n) = int(n-1) + 0.5 * (f(n) - f(n-1)) The 0.5 times the difference assumes that the function is a straight line between the two end points and when added to the min value is just the average of the two points. This is an approximation, but depending you your needs will be adequate. I would argue that for an arbitrary function, there is no advantage to using the average of each two points over just summing the points. Consider points 0 to N where N is a large number. N < f(n) = f(1) + f(2) + ... + f(N) < 1 N < avg(f(n),f(n-1) = 0.5 f(0) + f(1) + f(2) + ... + 0.5 * f(N) < 1 Notice that the only difference is that the average needs an extra input point to calculate the first average and that the two end points of the summation are halved. Numerically the difference between the two calculations is 0.5 * (f(n) - f(0)). It appears to me to be a very minuscule error to just add all the points without the complexity of averaging. I would bet that for any value of N, 256 or over, this error in the integral is much less than the error you get by the original straight line average approximation. In fact, whether you the average is correct or not depends on how you picture the error formation. This is too complex to draw here, but if you picture the sample as being centered in the region being integrated by adding that value, then the error is only a function of the second order components of f(x). To require an average calculation you are assuming that the area being calculated for a given point is the area *between* two points. I could explain this more fully, but it is very hard to do without a drawing. RickArticle: 141693
On Jul 3, 1:47=A0pm, "MM" <mb...@yahoo.com> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com... > On Jul 2, 8:23 pm, steve <st...@aol.com> wrote: > > > > > There are other aspects to any occupation than just the technical > > issues. =A0LinkedIn is oriented toward the business issues such as > > getting a job or filling a job. =A0As much as I would like to see it be > > more technical, it seems like it is pretty firmly rooted in networking > > with technical discussions being secondary. > > > Is it really that odd to consider? > > > Rick > > A bigger problem is how technical discussions are set up (or at least use= d > to be set up when I last looked) and viewed on LinkedIn. Answering questi= ons > is supposed to earn you points to improve your image. The questions remai= n > active for only limited period of time upon expiration of which no one ca= n > contribute. Finally, you need to be a premium (read paid) member to be ab= le > to send a private message to another member. > > /Mikhail I have not seen anything about points on LinkedIn. I think the only way to "improve" your image at LinkedIn is what you put in your profile. LinkedIn does not rate anyone that I am aware of. I think you may be remembering a different site than LinkedIn. They don't limit the time to reply to a discussion and I am not a paid member and I can send private messages. If I could find you, I would send you a private message to demonstrate, but there are a lot of Mikhails on LinkedIn. RickArticle: 141694
On Jul 2, 9:08=A0am, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > In the original message there is some kind of mixup, it speaks about 4x > PCIe, but 8 lanes, or did he want 2*4x PCIe. 4xPCIe with lowcost FPGAs > might also be quite challenging design. Sorry. My asumptions: PCI-e x 1 =3D2 differential pairs ( 2x Rx + 2* Tx ) PCI-e x 4 =3D 8 differential pairs ( 4x Rx + 4* Tx ) 1 lane =3D one differential pair It seems from your question that i should count 1 PCI-e lane as 2 diff. pairs ( 1Rx + 1 Tx ) ?Article: 141695
On Jul 2, 12:30=A0am, Nathan Bialke <nat...@bialke.com> wrote: > Your statement that Spartan-6 has only two lanes is incorrect; > although the integrated endpoint only supports one lane, there's > nothing stopping you from using all 8 transceivers in the design for > an 8 lane link. It just means you need to do a bit more work. I was under the impression that there are only enough fast serial I/O pins on the chip for PCI-e x1 ...Article: 141696
On Thu, 2 Jul 2009 04:59:02 -0700 (PDT), Simon <wlpstxzhd@gmail.com>
wrote:
>Hi, guys,
>
>I have been several years experience on FPGA networking application
>design, but I come up with the a question about math operation in
>FPGA. I need to perform Integral operation. I don't know if there is
>existing library which offer this function, or DSP? I think the last
>option is to run the integral library in the embedded PowerPC in
>Xilinx FPGA, but don't know how the performance is. Could anybody
>indicate how to achieve this goal?
What you need is called numerical integration. Depending on the level
of accuracy needed, there are various ways of accomplishing it but at
the basic level it is an accumulator of the values of the function
needed to be integrated. Suppose you want to integrate a function f(t)
from t=a to t=b. The crudes integration would be to assume function f
has an average value of (f(b)+f(a))/s over this range so you integral
is (b-a) * (f(b)+f(a))/2. A better way is to divide the range [a b]
into small Dt slots (say N of them) and then iterate over this set
which makes the result (a+b)/N*(sum{(i=0;i<N) f(a+i*Dt)} which
basically says that you make small rectangles from the area under f(t)
and every rectange has an area of its width (Dt) times the value of
the function at the left hand x coordinate of the function. For
"smooth" functions this usually gives a pretty good result if your N
is "large enough" compared to "smoothness" of the function.
Here is a reference http://en.wikipedia.org/wiki/Numerical_integration
which has further references.
-
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
Article: 141697"rickman" <gnuarm@gmail.com> wrote in message news:7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com... On Jul 3, 1:47 pm, "MM" <mb...@yahoo.com> wrote: > >I have not seen anything about points on LinkedIn. I think the only >way to "improve" your image at LinkedIn is what you put in your >profile. LinkedIn does not rate anyone that I am aware of. > >I think you may be remembering a different site than LinkedIn. They >don't limit the time to reply to a discussion and I am not a paid >member and I can send private messages. If I could find you, I would >send you a private message to demonstrate, but there are a lot of >Mikhails on LinkedIn. I should have put points in quote marks. There is no rating, but there is an option to see all the answers by a person. I am not confusing LinkedIn with another site but I might be confusing discussions in its groups with its Answers section though. With regards to the private mail, it seems as they have recently changed their policy. It used to be that you could only send a message to someone in your network, for anyone else the only type of message you could send was an invitation to join your network. /MikhailArticle: 141698
>"The Lord of War" <maa105.aub@gmail.com> wrote in message >news:lIqdnYYs39EeWtDXnZ2dnUVZ_sGdnZ2d@giganews.com... >> eh no for what no for I cant use the sram that is onboard or no I have to >> do some fancy stuff and calls to be able to use them? and if so what do i >> need to do? > >No, the fpga doesn't of itself know about the board. It doesn't know about >the devices on the board. And it doesn't know the minutiae of operation of >the devices on the board. > >As to what to do, it depends on what you're trying to do. An embedded system >can use the Xilinx EDK to interface with the device, attach it to the >peripheral bus, assign it room in the memory space, and build drivers to >access and control the device from software. For a hardware only solution, >start with the device's datasheet, and build the interface circuitry in the >fpga. The "process" you can "call" to work with the device might already >exist. They're more generally referred to as IP Cores. I expect you'll find >the required IP Cores in the Xilinx tools. > >"Fancy stuff" on the fpga is more properly thought of as describing and >connecting circuitry. It is not software "calls" using a strange new >programming language. I hope you'll find that distinction helpful. > > > I dont know but maybe (or definitely) you guys are way more advanced than me that's why I'm getting nothing, so to be clear I have an fpga board on it is the virtex 4 and lots of other chips including an sram module and a flash (scan disk) and something called linear flash all this is on the SAME board as the FPGA and what I'm trying to do is to use these modules to save information temporarily, so I need to save data in the sram (the one ONboard) to be able to use later. I'm using VHDL to code my project, and my question is; HOW can I use these resources which are on the same board. please help the declaring big array did not work. any tutorials or sample code is greatly appreciated thanks a lot guys and best of regardsArticle: 141699
On Fri, 03 Jul 2009 15:25:46 -0500, "The Lord of War" <maa105.aub@gmail.com> wrote: >>"The Lord of War" <maa105.aub@gmail.com> wrote in message >>news:lIqdnYYs39EeWtDXnZ2dnUVZ_sGdnZ2d@giganews.com... >>> eh no for what no for I cant use the sram that is onboard or no I have >to >>> do some fancy stuff and calls to be able to use them? and if so what do >i >>> need to do? >> >>No, the fpga doesn't of itself know about the board. It doesn't know >about >>the devices on the board. And it doesn't know the minutiae of operation >of >>the devices on the board. >> >>As to what to do, it depends on what you're trying to do. An embedded >system >>can use the Xilinx EDK to interface with the device, attach it to the >>peripheral bus, assign it room in the memory space, and build drivers to > >>access and control the device from software. For a hardware only >solution, >>start with the device's datasheet, and build the interface circuitry in >the >>fpga. The "process" you can "call" to work with the device might already > >>exist. They're more generally referred to as IP Cores. I expect you'll >find >>the required IP Cores in the Xilinx tools. >> >>"Fancy stuff" on the fpga is more properly thought of as describing and >>connecting circuitry. It is not software "calls" using a strange new >>programming language. I hope you'll find that distinction helpful. >> >> >> > >I dont know but maybe (or definitely) you guys are way more advanced than >me that's why I'm getting nothing, so to be clear I have an fpga board on >it is the virtex 4 and lots of other chips including an sram module and a >flash (scan disk) and something called linear flash all this is on the SAME >board as the FPGA and what I'm trying to do is to use these modules to save >information temporarily, so I need to save data in the sram (the one >ONboard) to be able to use later. I'm using VHDL to code my project, and my >question is; HOW can I use these resources which are on the same board. > >please help the declaring big array did not work. >any tutorials or sample code is greatly appreciated > >thanks a lot guys and best of regards Declaring an array in VHDL uses memory _inside_ the FPGA. You need to use memory _outside_ the FPGA. Imagine that the SRAM chip is connected to a microprocessor, instead of a FPGA. The micro and the SRAM chip communicate via Address lines, Data lines (I/O) and control lines (cs*, we*, rd, wr, etc). The micro puts out a valid address, and sets the control lines to read from or write to the SRAM chip. The data travels on the data lines (bus). So, the FPGA needs to do something similar; this is called a memory controller. The timing of the memory controller must match the specs of the SRAM chip. There may be existing IP for Virtex that already does this. Perhaps Xilinx's CoreGen creates one (look in ISE). Your VHDL "code" then uses the memory controller to communicate with the SRAM. HTH -Dave Pollum
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