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General Schvantzkoph <schvantzkoph@yahoo.com> writes: > The ability to change memories or registers has nothing to do with poor > coding practices. When you are running a hardware testbench it would be > incredibly useful to be able to change the contents of a register in real > time rather then having to place and route the design again. I seem to remember changing BRAM contents with FPGA editor. Should be faster than going through the whole place and route flow.Article: 145176
On Jan 30, 8:38=A0pm, Anssi Saari <a...@sci.fi> wrote: > General Schvantzkoph <schvantzk...@yahoo.com> writes: > > The ability to change memories or registers has nothing to do with poor > > coding practices. When you are running a hardware testbench it would be > > incredibly useful to be able to change the contents of a register in re= al > > time rather then having to place and route the design again. > > I seem to remember changing BRAM contents with FPGA editor. Should be > faster than going through the whole place and route flow. well yes you can also sometimes data2mem, but that isnt same things as chaning it over JTAG as it possible with Altera Quartus AnttiArticle: 145177
zanaticul wrote: > but i get an error: ERROR:HDLParsers:808 - > "D:/Work/fpga/projects/stopWatch/nr.vhd" Line 53. * can not have such > operands in this context. http://lmgtfy.com/?q=vhdl+stop+watchArticle: 145178
On 29 ene, 11:22, "jmunir" <jmu...@gts.tsc.uvigo.es> wrote: > Hi!, > > I have been working with Altera FPGAs for a long time and now I have to > deal with Xilinx ones. Until now, with Quartus II I have been able to > manage the content of different registers and memories with 'In system > memory editor' and I would like to do the same with Xilinx. I cannot find > the right application to do it. Could you tell me which one I need or how= I > can do it? > > Thanx > > J. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com To debuging proposes you can try JTAG loader, part of KCPSM3 and can be downloaded from Xilinx web site. May be you need do some "bricolage" but work fine. WalterArticle: 145179
> > To debuging proposes you can try JTAG loader, part of KCPSM3 and can > be downloaded from Xilinx web site. > May be you need do some "bricolage" but work fine. > > Walter Hi Walter, well it depends, for me, I can write own JTAG tools and JTAG IP cores as i please, and do get things done as needed. The OP question was more about FPGA vendor own support tools that use vendor JTAG tools and adapters and can modify the FPGA registers and BRAM in generic, without ANY support in user VHDL using the configuration logic bypass functions, its like partial dynamic reconfiguration, maybe it understood now better. This is possible and supported by Altera Quartus, and NOT supported by any Xilinx tools. AnttiArticle: 145180
On Jan 30, 10:41=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Jan 30, 11:18=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > > On Jan 30, 9:59=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > On Jan 30, 10:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > > On Jan 30, 7:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > > o=3Di; > > > > > > is not needed > > > > > > o=3D'1'; > > > > > > is sufficient > > > > > but Sufficient to test only the o=3D1 case, > > > > by making the OP under user control, you can test > > > > both H and L outputs with one compile ;) > > > > -jg > > > > Jim, it was not about TESTING the output, it was about creating an > > > EMPTY design. > > > there is no need to test anything with empty design :) > > > > Antti > > > The OP wanted to "measure the quiescent current of the xilinx FPGA", > > and that can vary with H & L, > > so the best test coverage is to check both. > > > He probably should also plot Icc vs Vin on a pin, so he can factor in > > non-cmos or level shifting effects, if needed. > > > -jg > > nono, he did not want measure the current in dependancy of the output > being driven high or low, in the matter of fact he would have > preffered the output to not be driven at all, so actually he should > have made a desing that is as small as possible, and has one output > that is always tristated. Hehe, if his REAL system is going to have no outputs driven, then you would be correct. However, in the real world, a vital part of "measuring the quiescent current" of a static system is to have the I/O lines at 'field likely' states. ie On my bench, I want to know if the pin state, or even Vi level, mattered. On many chips, it does. If you ignore this stuff, it can bite you! I'll admit I presumed the OP wanted a useful number. -jgArticle: 145181
I just installed Quartus II Web Edition 9.1 on linux. I compiled a simple test project and only then I noticed that simulation is unsupported! It's supported on the Windows version, so how come this discrepancy? Are we supposed to dump each and every edit onto the board and debug on the board? They might as well not offer the Web Edition on linux at all.Article: 145182
On Jan 30, 1:34=A0pm, "zanaticul" <cosminc...@yahoo.com> wrote: > Hello, > > i want to split a number for example 1234 in 4 numbers 1,2,3,4 > witch is the best way to do it? If you're just looking to display the binary value in decimal, do a quick search for "binary to bcd converter" and you should find nice little serial implementations that let you digest a digit at a time out of the original binary number. The serial implementation is quite nice. Since visual representation of the numbers doesn't have to occur at 50 MHz, the serial implementation is usually quite adequate. The first google hit shows the process extremely well: http://www.engr.udayton.edu/faculty/jloomis/ece314/notes/devices/binary_to_= BCD/bin_to_BCD.html - John_HArticle: 145183
Why not use XDL?
1.Get any ncd file targeting your x device and convert it to xdl format
('xdl -ncd2xdl anydesign.ncd')
2.copy the first (uncommented) line from the xdl file (contains target
device name) to a new file (e.g. empty.xdl)
3. convert the new xdl file back to ncd format ('xdl -xdl2ncd -force
empty_design.xdl empty_design.ncd')
4. create bit file ('bitgen -d empty_design.ncd')
4.profit :)
You could also use below python script
Regards,
Krzysztof
empty_design.py :
import os
xdl_content = '< put here first line from the xdl file with target device>'
empty_file = open("empty_design.xdl",'w')
empty_file.write(xdl_content)
empty_file.close()
os.system("xdl -xdl2ncd -force empty_design.xdl empty_design.ncd")
os.system("bitgen -d empty_design.ncd")
"EE EE" <eengr.usa@gmail.com> wrote in message
news:27dcf723-c9ad-4f45-b9f2-ec1b2d4268a2@x1g2000prb.googlegroups.com...
> Hi
> I want to synthesize a completely empty design, no clocks no combo and
> no sequential logic for a xilinx FPGA using ISE.
> THe problem is
> if I try to implement module dummy_fpga (); endmodule
> The tool synthesizes it but fails to translate it.
> I wanted to create an empty design with no inputs and no outputs and
> then use bit gen to float all unused IOs. This was I could measure the
> quiescent current of the xilinx FPGA.
> Any suggestions?
> Thanks
Article: 145184
Giorgos Tzampanakis wrote:
> I just installed Quartus II Web Edition 9.1 on linux. I compiled a simple
> test project and only then I noticed that simulation is unsupported! It's
> supported on the Windows version, so how come this discrepancy?
Use the modelsim-Altera starter for small designs:
https://www.altera.com/support/software/download/eda_software/modelsim/dnl-msim-65b-qii91.jsp
It is free and covers
Windows XP, Vista (32 bit)
RedHat Linux Enterprise 4 and 5 (32 bit)
SUSE Linux Enterprise 9.0 (32 bit)
-- Mike Treseler
Article: 145185Antti escribió: >> To debuging proposes you can try JTAG loader, part of KCPSM3 and can >> be downloaded from Xilinx web site. >> May be you need do some "bricolage" but work fine. >> >> Walter > > Hi Walter, > > well it depends, for me, I can write own JTAG tools and JTAG IP cores > as i please, and do get things done as needed. > > The OP question was more about FPGA vendor own support tools that use > vendor JTAG tools and adapters and can modify the FPGA registers and > BRAM in generic, without ANY support in user VHDL using the > configuration logic bypass functions, its like partial dynamic > reconfiguration, maybe it understood now better. This is possible and > supported by Altera Quartus, and NOT supported by any Xilinx tools. > > Antti > > Hi Antti, In my projects, many times I need write software/firmware and hardware only to debugging. I try to answer the original post; how solve a specific problem with a more or less simple general solution; JTAGLoader or a simple VHDL/Verilog UART plus a 8 U$D USB-RS232-TLL adapter can be used to modify a design for debugging without need write software, if the designer designs for verification. Others is Xilinx's tools, well, I use Xilinx's tools since many years, the tool is today (I use ISE 10) several times more friendly but not necessarily more productive than older Xilinx's tools. The Xilinx's tools are a complex piece of software and as T.Hoare sentence at '80. "There are two ways of constructing a software design: One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies. The first method is far more difficult." Thinking in my daily work, memory editor could be a nice feature but not necessarily in the firsts places of my list of necessary features. It may be a good exercise for us all, list the ISE features that we use daily, occasionally or never used and which features would be interesting to add. If we reach a consensus, Xilinx perhaps listen to us. Walter. --- news://freenews.netfront.net/ - complaints: news@netfront.net ---Article: 145186
On Jan 29, 5:35=A0pm, emeb <ebromba...@gmail.com> wrote: > On Jan 29, 2:57=A0pm, austin <aus...@xilinx.com> wrote: > > > > > Differential Power Attack has been known (and used) for many years > > now, (it is not new at all) > > > DPA was originally used to hack credit cards in Europe, and there are > > many other recorded (successful) attacks, as well. > > > CRI is making a lot of noise about their alleged crack of one Virtex > > II Pro, 3DES key (168 bits), on one platform designed to facilitate > > just such attacks. =A0Is this claim confirmed? =A0By whom? =A0If I load= ed > > the "secret" key, and I know the value, and then I claim I > > "discovered" its value ... seems that the real "key" here is to > > authentication: =A0who do you believe, and how can you be sure? =A0The > > 'motivation' for this seems unusually coincidental, as well... > > > They also own a lot of IP, for the express purpose of countering > > DPA .... and making money. =A0They are looking for business. =A0If you > > want to protect yourself from DPA (and you think their methods might > > work), and you are very rich, give them a call. =A0Seems they need > > money. =A0Don't we all! =A0See 'motivation', above. > > > The job of preventing ALL attacks, is known as anti tamper: =A0detect a= n > > attack, and remove all information of value (prevent the attack). > > > Anti-tamper is not "owned" by CRI, and anyone can implement AT > > techniques, and, in any system that is supposed to be secure, AT is > > required. > > > "Denial of Service" is another attack to worry about, and if you have > > physical access to a device, then a hammer is sufficient to conclude > > an effective "denial of service." =A0Removing the batteries, or > > unplugging the system can also be very effective. > > > So, security is a big field, with many things to think (anticipate) > > about. =A0DPA is just one attack, of many. > > > Like I said, if you are worried about DPA, then you should also be > > worried about DoS, AT, and many other forms of attack. =A0By itself, DP= A > > might be the least of your concerns. > > > If you already work in this field, you already know that there are > > existing solutions for all of these attacks. =A0Attackers have a natura= l > > advantage: =A0they can think up new attacks all day long. =A0Defenders > > have it tough: =A0they must defend against ALL present, and future > > attacks, right now. > > > And, there are not only threats to your systems, there are threats to > > your way of doing business: =A0If you are unfortunate enough to have > > implemented a defense that someone else has a patent on, then you will > > face an entirely different threat: =A0someone demanding money! > > > I wish CRI all the best in their endeavors, > > > Austin > > Austin, > > Thanks for your insights. I was rather hoping you would jump in on > this question. > > I'm pretty skeptical of the claimed vulnerabilities. I imagine that > it's possible to extract a key with DPA under properly controlled > conditions, but it seems to me that controlling the conditions for any > random hardware that the black hats want to crack would be fairly > difficult. As I mentioned to my boss when he pointed this article out > to me, the first question that I ask when I read something like this > is "What are they trying to sell?" and you've answered that one. > > In my case, we're protecting IP - we don't want our algorithms out > there. Others may be protecting the processed data, or guarding > against counterfeiting. Each of these requires a different web of > protection, and bitstream encryption is just one strand in the web. > Prudence dictates your web have more than one strand. > > Eric A key point to keep in mind: DPA requires many samples in order to improve the signal to noise ratio. The defender can add noise, make sampling more difficult, or both. JohnArticle: 145187
On 1/28/2010 11:55 PM, emeb wrote: > > A lot of scary hype and generalities, but the underlying message seems > to be that by using Differential Power Analysis it's possible to > decrypt a protected FPGA design. Basic idea is to monitor the power > consumption while loading the encrypted design, then via some kind of > magic infer what the plaintext bitstream is and then reverse engineer > it. > > Sounds like someone at a security research outfit is trying to sell > some consulting hours to me, but what's the general feeling about > this? Is this a real threat, and what are the realistic barriers to > applying this attack? > > Eric If you're that interested, why not give them one of your boards and say you'll consider buying their product if they can tell you the key? Cheers, Syms.Article: 145188
On Jan 29, 12:11=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Jan 29, 7:01=A0pm, austin <aus...@xilinx.com> wrote: > > > > > Antti, > > > "If Xilinx cared about the customers...." > > > Cruel, and inappropriate. > > > Of course we care (deeply) about our customers! > > > "Because Xilinx does not have Tool-A, they have no concern for > > customers..." > > > It would be equally true then to say because the 'other guy' has no > > domain specific platforms, that they have zero regard for their > > customers, and force them to re-invent the wheel before they even > > begin a project ... (which in my humble opinion is all true) > > > So, let us refrain from 'name calling', =A0one could waste a great deal > > of time, > > > Austin > > ah, relax.. > > both X and A care for the shareholders. > > but the topic about the "memory editor" is well, it would be SO EASY > for Xilinx todo, > but it has not been done. some 3rd party could do, i could do it, but > it would be much > more work for me todo it properly as it would be for xilinx, besides > because Xilinx > does not open up the xilinx usb cable protocol i could not support > xilinx cables > from my tool, so it would be pointless todo. I like the way that Austin gets all hot under the collar when you say "extreme" things about Xilinx, which we all know to take with a grain of salt, (even if we pretty much agree with them) but he completely ignores the real issue being discussed. His reply, "we are (trying to) prevent poor coding practices, which lead to errors" seems to be saying that the programmer is not to be trusted with tools that allow him to work the way he wants. Geeze, there are any number of reasons why a designer would want to manipulate the initial values in the BRAMs "on the fly". Obviously that is why Altera provides these tools. Otherwise we are left to think that Altera wants to promote "poor coding practices" and errors. > there are two reasons why Xilinx does not have memory editor > 1) there are some silicon problems, errata, bugs with the silicon > preventing the usefulnes of the tool > 2) Xilinx just doesnt care to offer this tool > > I see no other reasons. you can choose. either silicon problems, or > lazy programmers. > or management issues. i figured out 3rd option. > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > the memory editor > and well Altera has no data2mem possibility at all, what is real > problem. > > Xilinx has what is really needed, and misses on optional "good to > have" thing that is not > that vital. > > Antti Personally, I think both tools are very useful. Once a design is compiled and a bit file produced that works properly, it can be very useful to produce different versions of the bit stream with different data in the BRAMs. But during debug it can be much more expedient to download the BRAM data on the fly as needed. Potentially it could even be useful to download the BRAM contents ov er JTAG in the field, but I see that as a very limited application. But I can assure you that if either company had just one very large customer who requested a tool like this, they would get it. So most likely, each company has produced the tool that their customers have requested. RickArticle: 145189
On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es> wrote: > So, my question is: > > When I implement a block and I would like to control several of his > parameters to test its behaviour, do I have to recompile each time I want > to change one of them? :O > > That has not sense! It is impractical! > > J. I don't think you need to recompile the HDL. You need to produce a new bit stream from the original bitstream. Still, this requires a number of steps, which can be done in one step with a JTAG tool. RickArticle: 145190
On Feb 1, 7:36=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es> > wrote: > > > So, my question is: > > > When I implement a block and I would like to control several of his > > parameters to test its behaviour, do I have to recompile each time I wa= nt > > to change one of them? :O > > > That has not sense! It is impractical! > > > J. > > I don't think you need to recompile the HDL. =A0You need to produce a > new bit stream from the original bitstream. =A0Still, this requires a > number of steps, which can be done in one step with a JTAG tool. > > Rick Hi, If you have a design where you want to modify the BRAM contents, data2mem is the tool to use. It can modify an existing bitfile and creates a new bitfile with the new BRAM contents. After you have created the .bmm file, it's just one call to data2mem to create a new bitfile with modified BRAM contents. It takes a few seconds to finish. If you just want to toggle some registers down in the target, you can use Chipscope VIO which allows you to modify signal values in target using JTAG. I agree that it would be good to have a tool that allow you full control of everything in the device over JTAG but I can also think of 10+ other tools that would be good to have. Xilinx doesn't have an infinite number of resources for doing tools and we have to pick which one we should do. One can argue that a comprehensive JTAG debug tool should be one of them but as today, Xilinx has data2mem and chipscope. It allows customers accomplish what they want although it might not be in easiest way for everyone. G=F6ranArticle: 145191
On Feb 1, 10:26=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote: > On Feb 1, 7:36=A0am, rickman <gnu...@gmail.com> wrote: > > > > > > > On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es> > > wrote: > > > > So, my question is: > > > > When I implement a block and I would like to control several of his > > > parameters to test its behaviour, do I have to recompile each time I = want > > > to change one of them? :O > > > > That has not sense! It is impractical! > > > > J. > > > I don't think you need to recompile the HDL. =A0You need to produce a > > new bit stream from the original bitstream. =A0Still, this requires a > > number of steps, which can be done in one step with a JTAG tool. > > > Rick > > Hi, > > If you have a design where you want to modify the BRAM contents, > data2mem is the tool to use. > It can modify an existing bitfile and creates a new bitfile with the > new BRAM contents. > After you have created the .bmm file, it's just one call to data2mem > to create a new bitfile with modified BRAM contents. > It takes a few seconds to finish. > > If you just want to toggle some registers down in the target, you can > use Chipscope VIO which allows you to modify signal values in target > using JTAG. > > I agree that it would be good to have a tool that allow you full > control of everything in the device over JTAG but I can also think of > 10+ other tools that would be good to have. > Xilinx doesn't have an infinite number of resources for doing tools > and we have to pick which one we should do. > > One can argue that a comprehensive JTAG debug tool should be one of > them but as today, Xilinx has data2mem and chipscope. > It allows customers accomplish what they want although it might not be > in easiest way for everyone. > > G=F6ran G=F6ran, if-when Xilinx admits it has limited resources, then WHY Xilinx does not allow 3rd party developer to help Xilinx customers? just a small decision to make: open up Xilinx USB Cable API, that is all that Xilinx would have todo. Yes, this also takes resources as it may require some maintenance and code cleanup from Xilinx, but if Xilinx would do that cleanup, it may also be of benefit of Xilinx internal developer team, so at the end Xilinx may actually win saving time not spending it. I would love to re-think and re publish some of my old JTAG tools, but without the ability to talk to Xilinx official USB cables it makes little sense. Altera USB cables are EASY to talk, and there exist 3rd party software that uses them. There is very little 3rd party software supporting completly and without problems Xilinx USB cables. AnttiArticle: 145192
On Feb 1, 9:43=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Feb 1, 10:26=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote: > > > > > > > On Feb 1, 7:36=A0am, rickman <gnu...@gmail.com> wrote: > > > > On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es> > > > wrote: > > > > > So, my question is: > > > > > When I implement a block and I would like to control several of his > > > > parameters to test its behaviour, do I have to recompile each time = I want > > > > to change one of them? :O > > > > > That has not sense! It is impractical! > > > > > J. > > > > I don't think you need to recompile the HDL. =A0You need to produce a > > > new bit stream from the original bitstream. =A0Still, this requires a > > > number of steps, which can be done in one step with a JTAG tool. > > > > Rick > > > Hi, > > > If you have a design where you want to modify the BRAM contents, > > data2mem is the tool to use. > > It can modify an existing bitfile and creates a new bitfile with the > > new BRAM contents. > > After you have created the .bmm file, it's just one call to data2mem > > to create a new bitfile with modified BRAM contents. > > It takes a few seconds to finish. > > > If you just want to toggle some registers down in the target, you can > > use Chipscope VIO which allows you to modify signal values in target > > using JTAG. > > > I agree that it would be good to have a tool that allow you full > > control of everything in the device over JTAG but I can also think of > > 10+ other tools that would be good to have. > > Xilinx doesn't have an infinite number of resources for doing tools > > and we have to pick which one we should do. > > > One can argue that a comprehensive JTAG debug tool should be one of > > them but as today, Xilinx has data2mem and chipscope. > > It allows customers accomplish what they want although it might not be > > in easiest way for everyone. > > > G=F6ran > > G=F6ran, > > if-when Xilinx admits it has limited resources, then WHY Xilinx does > not > allow 3rd party developer to help Xilinx customers? > > just a small decision to make: open up Xilinx USB Cable API, that > is all that Xilinx would have todo. Yes, this also takes resources > as it may require some maintenance and code cleanup from Xilinx, > but if Xilinx would do that cleanup, it may also be of benefit of > Xilinx internal developer team, so at the end Xilinx may actually > win saving time not spending it. > > I would love to re-think and re publish some of my old JTAG > tools, but without the ability to talk to Xilinx official USB cables > it makes little sense. > > Altera USB cables are EASY to talk, and there exist 3rd party > software that uses them. There is very little 3rd party software > supporting completly and without problems Xilinx USB cables. > > Antti- Hide quoted text - > > - Show quoted text - Hi Antti, Every company has limited resources so this is not just Xilinx- specific. For this "godly" JTAG debug tool, I doubt that the USB JTAG cable API is the main issue. The tool would need to understand the complete configuration description of every Xilinx architecture and device. The tool also need to support all download cables and not just USB. If this is not about the "godly" JTAG tool but rather that you want to have access to the USB JTAG cable API, I can check if we plan to make it public. I think there is a generic cable API (which should cover all types of download cables, not just USB) but I don't know the status of it. G=F6ranArticle: 145193
On Feb 1, 11:16=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote: > On Feb 1, 9:43=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Feb 1, 10:26=A0am, Goran_Bilski <goran.bil...@xilinx.com> wrote: > > > > On Feb 1, 7:36=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.e= s> > > > > wrote: > > > > > > So, my question is: > > > > > > When I implement a block and I would like to control several of h= is > > > > > parameters to test its behaviour, do I have to recompile each tim= e I want > > > > > to change one of them? :O > > > > > > That has not sense! It is impractical! > > > > > > J. > > > > > I don't think you need to recompile the HDL. =A0You need to produce= a > > > > new bit stream from the original bitstream. =A0Still, this requires= a > > > > number of steps, which can be done in one step with a JTAG tool. > > > > > Rick > > > > Hi, > > > > If you have a design where you want to modify the BRAM contents, > > > data2mem is the tool to use. > > > It can modify an existing bitfile and creates a new bitfile with the > > > new BRAM contents. > > > After you have created the .bmm file, it's just one call to data2mem > > > to create a new bitfile with modified BRAM contents. > > > It takes a few seconds to finish. > > > > If you just want to toggle some registers down in the target, you can > > > use Chipscope VIO which allows you to modify signal values in target > > > using JTAG. > > > > I agree that it would be good to have a tool that allow you full > > > control of everything in the device over JTAG but I can also think of > > > 10+ other tools that would be good to have. > > > Xilinx doesn't have an infinite number of resources for doing tools > > > and we have to pick which one we should do. > > > > One can argue that a comprehensive JTAG debug tool should be one of > > > them but as today, Xilinx has data2mem and chipscope. > > > It allows customers accomplish what they want although it might not b= e > > > in easiest way for everyone. > > > > G=F6ran > > > G=F6ran, > > > if-when Xilinx admits it has limited resources, then WHY Xilinx does > > not > > allow 3rd party developer to help Xilinx customers? > > > just a small decision to make: open up Xilinx USB Cable API, that > > is all that Xilinx would have todo. Yes, this also takes resources > > as it may require some maintenance and code cleanup from Xilinx, > > but if Xilinx would do that cleanup, it may also be of benefit of > > Xilinx internal developer team, so at the end Xilinx may actually > > win saving time not spending it. > > > I would love to re-think and re publish some of my old JTAG > > tools, but without the ability to talk to Xilinx official USB cables > > it makes little sense. > > > Altera USB cables are EASY to talk, and there exist 3rd party > > software that uses them. There is very little 3rd party software > > supporting completly and without problems Xilinx USB cables. > > > Antti- Hide quoted text - > > > - Show quoted text - > > Hi Antti, > > Every company has limited resources so this is not just Xilinx- > specific. > > For this "godly" JTAG debug tool, I doubt that the USB JTAG cable API > is the main issue. > The tool would need to understand the complete configuration > description of every Xilinx architecture and device. > The tool also need to support all download cables and not just USB. > > If this is not about the "godly" JTAG tool but rather that you want to > have access to the USB JTAG cable API, I can check if we plan to make > it public. > I think there is a generic cable API (which should cover all types of > download cables, not just USB) but I don't know the status of it. > > G=F6ran Xilinx has obsoleted the Parallel port cables, (no longer supported!) so the USB cable is the only cable supported by official tools. right publishing the API, would not "do it all" but it would open possibility for more USEABLE and USEFUL tools to be developed and offered for the Xilinx users. AnttiArticle: 145194
Hello, is there a way to constrain minimum hold time requirements with ISE? I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H supplies a 60 MHz clock and specifies 11 ns setup and 0 ns hold. As the FT2232H supplied clock can stop, using a DCM to retime the clock will at least require the DCM to stabilize each time and so to wait when the transmission is initiated. So only with the FT2232H on a global clock, all outputs using the PAD registers and with a XC200A and LVCMOS25/12mA/Fast slew drive TICKOF is 5.24 ns and timing can be met (16.666 -5.24 = 11.42 > 11). However this eats up simultaneous switching margins, and more my test board uses 3.3V and the clock is on a LHCLK, not reaching all outputs. Another way would be to clock out data on the negative edge with input delay on the clock and a slow drive. If I could constrain half a clock period hold time, the 0 ns hold requirement of the FT2232h could be met. Is there a way to do so? Any other ideas? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 145195
Uwe Bonnes wrote: > Is there a way to do so? > Any other ideas? use a faster clock ? > Thanks hope this helps ;-) yg -- http://ygdes.com / http://yasep.orgArticle: 145196
hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data clock out(DC0+,DC0-) and out of range(OUR) are connected physically to Sparta 3a dsp. My question is how do I directly collect these LVDS signals in my sparta 3a dsp core. How do I get back my data in aa format I can work on? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145197
Hi, My query is the next: I'm working with Xilinx Ise Design Suite 11.1. I need some ROMS with differents values of depth, width and initialization files that I want to instantiate in one proyect. I need a generic ROM, so I created one with Core Generator and I got its HDL code using View HDL functional Model. Then I introduced the values of width, depth and initialization file like generics values. In the proyect, I generated the ROMS intantiating this HDL code, each one with differents values. When I sintetize the proyect appears some warnings like those: WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not attach to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. WARNING:Xst:616 - Invalid property "depth 3": Did not attach to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. WARNING:Xst:616 - Invalid property "width 8": Did not attach to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. Is there another way to get a ROM with Core Generator so that it can be instantiated in the proyect and form there I can generate differents ROMs since te core that I created with differents the values of width, depth and initialization file?? Thank you --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145198
On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com> wrote: > Hi, > > My query is the next: > I'm working with Xilinx Ise Design Suite 11.1. > I need some ROMS with differents values of depth, width and initializatio= n > files that I want to instantiate in one proyect. I need a generic ROM, so= I > created one with Core Generator and I got its HDL code =C2=A0using View H= DL > functional Model. > Then I introduced the values of width, depth and initialization file like > generics values. In the proyect, I generated the ROMS intantiating this H= DL > code, each one with differents values. > > When I sintetize the proyect appears some warnings like those: > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not atta= ch > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > WARNING:Xst:616 - Invalid property "width 8": Did not attach to > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > > Is there another way to get a ROM with Core Generator so that it can be > instantiated in the proyect and form there I can generate differents ROMs > since te core that I created with differents the values of width, depth a= nd > =C2=A0 initialization file?? > > Thank you > > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0 > Posted throughhttp://www.FPGARelated.com Take a look at creating ROMs using textio operations, that is, create your own ROM via VHDL. I hope it will solve your problem. --enesArticle: 145199
>> >>>According to ISE definition, input offset is the time of data transition >>>relative to NEXT clock edge. >>>Your setting of 2ns resulted in ISE reporting -3.17ns i.e. ISE now >>>contradicted its own definition and related it to previous clock edge. >>>Whichever way you look at it, you got a transition at(6 - (-3.17)) = >2.83 >>>ns with respect to NEXT clock edge, almost centre aligned. I don't >expect >>>volation of setup or hold as reported. Your own addition of 2 + 3.17ns >>>makes no sense to me. you asked for 2ns and you got 2.83ns >>> >>>kadhiem >>> >>>--------------------------------------- >>>Posted through http://www.FPGARelated.com >>> >> >>I think you are wrong. "transition at 2.83ns with respect to the next clk >>edge, almost center aligned" AT THE PAD means nothing, what we need is >>clocking correct AT THE FIRST Flip Flop. >> >>What ISE report means is that: If data come 3.17ns lag behind clock >rising >>edge, clock can just exactly sample data correctly at the first flip >flop. >>Right? >> >>If that is true, then: if data come 2ns before clock rising edge as the >>offset constraint, after going through the same data path and clock path, >>clock rising edge will present at (2+3.17)ns with respect to the data. >That >>is my question. >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com > >Both xilinx and altera timing tools are practically intersted in figures >for setup/hold timing relations at pads so that timing of io registers is >derived internally according to window shift. As a user, you only need to >look at pads and the tool will tell you if internal io and core registers >are ok. > >kadhiem > > >--------------------------------------- >Posted through http://www.FPGARelated.com > kadhiem, thank for your reply first. And let me explain the question again: What ISE report means is that: If data come 3.17ns lag behind clock rising edge, clock can just exactly sample data correctly at the first flip flop. So, if data come 2ns before clock rising edge, (i.e. come (2+3.17)ns earlier than ISE report), data will arrive the first flip flop (2+3.17)ns earlier than situation of ISE report which means fulfill setup time at FF exactly. And data period is 6ns, so, (2+3.17)ns will not be a stable time of data. I've read a pdf of xilinx which says constraint of "offset in before" only analyze setup time, and hold time is analyzed when "valid" time is set. And i think maybe that is the answer to my question: -3.17ns fulfill setup time, but don't fulfill the hold time. So, i add "valid" time constraint, and -3.17ns is not reported again. Am i right? Thanks! --------------------------------------- Posted through http://www.FPGARelated.com
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