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On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...@gmail.com> wrote: > On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com> wrote: > > > > > Hi, > > > My query is the next: > > I'm working with Xilinx Ise Design Suite 11.1. > > I need some ROMS with differents values of depth, width and initializat= ion > > files that I want to instantiate in one proyect. I need a generic ROM, = so I > > created one with Core Generator and I got its HDL code =C2=A0using View= HDL > > functional Model. > > Then I introduced the values of width, depth and initialization file li= ke > > generics values. In the proyect, I generated the ROMS intantiating this= HDL > > code, each one with differents values. > > > When I sintetize the proyect appears some warnings like those: > > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not at= tach > > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to > > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > > WARNING:Xst:616 - Invalid property "width 8": Did not attach to > > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > > > Is there another way to get a ROM with Core Generator so that it can be > > instantiated in the proyect and form there I can generate differents RO= Ms > > since te core that I created with differents the values of width, depth= and > > =C2=A0 initialization file?? > > > Thank you > > > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0 > > Posted throughhttp://www.FPGARelated.com > > Take a look at creating ROMs using textio operations, that is, create > your own ROM via VHDL. I hope it will solve your problem. > > --enes > via VHDL make that HDLArticle: 145201
I have two designs for an Altera chip that use approximately 6,000 and 24,000 logic elements. I am looking at moving to Xilinx tools, but am not sure how these numbers translate across manufacturers. I have seen Xilinx FPGA with gate counts cited, but I am not sure what those number mean. Can anyone provide some guidance in this?Article: 145202
On 2/1/2010 2:59 PM, Sam wrote: > I have two designs for an Altera chip that use approximately 6,000 and > 24,000 logic elements. I am looking at moving to Xilinx tools, but am > not sure how these numbers translate across manufacturers. I have seen > Xilinx FPGA with gate counts cited, but I am not sure what those > number mean. > > Can anyone provide some guidance in this? 1) Download tools from Xilinx's website with free 60 day license. 2) Feed your design into Xilinx tools. 3) Look at numbers. Ta da! HTH., Syms.Article: 145203
On Feb 1, 7:32=A0am, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: > hi there > > =A0 I have an ADC chip which is working in the LVDS mode. > =A0The data out(D0+,D0-,......D13+ and D13-),along with data clock > out(DC0+,DC0-) > and out of range(OUR) are connected physically to Sparta 3a dsp. > > =A0My question is how do I directly collect these LVDS signals in my spar= ta > 3a dsp core. > > =A0How do I get back my data in aa format I can work on? It is a little scary reading this question. It makes me think you don't understand that an LVDS receiver only has two signals on the pins, but is converted to a single signal by the receiver. Is that what you are missing? If so, you need to make sure your LVDS signals are going to the receivers in matched pairs. If you already understand this, then I am not clear on what you don't understand. In general, to use inputs to an FPGA, you have signal names in your HDL code which are inputs and outputs to the top level module. A separate file, typically created using a special editor in the GUI, specifies the details of how these signals are to be mapped to the I/O pins. Each maker has their own format for this file and typically other details are specified here, such as the I/O type (TTL, CMOS, LVDS, etc...), voltage levels, drive strength, etc... Often this same file also contains the timing constraints to be applied to the design while it is routed by the tool and analyzed to see if it meets timing. Is that what you needed? RickArticle: 145204
>On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...@gmail.com> wrote: >> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com> wrote: >> >> >> >> > Hi, >> >> > My query is the next: >> > I'm working with Xilinx Ise Design Suite 11.1. >> > I need some ROMS with differents values of depth, width and initializat= >ion >> > files that I want to instantiate in one proyect. I need a generic ROM, = >so I >> > created one with Core Generator and I got its HDL code =C2=A0using View= > HDL >> > functional Model. >> > Then I introduced the values of width, depth and initialization file li= >ke >> > generics values. In the proyect, I generated the ROMS intantiating this= > HDL >> > code, each one with differents values. >> >> > When I sintetize the proyect appears some warnings like those: >> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not at= >tach >> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> > WARNING:Xst:616 - Invalid property "width 8": Did not attach to >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> >> > Is there another way to get a ROM with Core Generator so that it can be >> > instantiated in the proyect and form there I can generate differents RO= >Ms >> > since te core that I created with differents the values of width, depth= > and >> > =C2=A0 initialization file?? >> >> > Thank you >> >> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0 >> > Posted throughhttp://www.FPGARelated.com >> >> Take a look at creating ROMs using textio operations, that is, create >> your own ROM via VHDL. I hope it will solve your problem. >> >> --enes > >> via VHDL > >make that HDL > Ok, I can do my own ROM via HDL but I need to use a CORE. What can I do?? I have to use a Core for demands of the proyect. Thank you --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145205
On Mon, 01 Feb 2010 10:02:09 -0600 "bellatoise" <arianaponte@n_o_s_p_a_m.gmail.com> wrote: > >On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...@gmail.com> wrote: > >> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com> wrote: > >> > >> > >> > >> > Hi, > >> > >> > My query is the next: > >> > I'm working with Xilinx Ise Design Suite 11.1. > >> > I need some ROMS with differents values of depth, width and > initializat= > >ion > >> > files that I want to instantiate in one proyect. I need a > >> > generic ROM, > = > >so I > >> > created one with Core Generator and I got its HDL code > >> > =C2=A0using > View= > > HDL > >> > functional Model. > >> > Then I introduced the values of width, depth and initialization > >> > file > li= > >ke > >> > generics values. In the proyect, I generated the ROMS > >> > intantiating > this= > > HDL > >> > code, each one with differents values. > >> > >> > When I sintetize the proyect appears some warnings like those: > >> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did > >> > not > at= > >tach > >> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > >> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to > >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > >> > WARNING:Xst:616 - Invalid property "width 8": Did not attach to > >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > >> > >> > Is there another way to get a ROM with Core Generator so that it > >> > can > be > >> > instantiated in the proyect and form there I can generate > >> > differents > RO= > >Ms > >> > since te core that I created with differents the values of width, > depth= > > and > >> > =C2=A0 initialization file?? > >> > >> > Thank you > >> > >> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 > >> > =C2=A0 Posted throughhttp://www.FPGARelated.com > >> > >> Take a look at creating ROMs using textio operations, that is, > >> create your own ROM via VHDL. I hope it will solve your problem. > >> > >> --enes > > > >> via VHDL > > > >make that HDL > > > > Ok, I can do my own ROM via HDL but I need to use a CORE. What can I > do?? I have to use a Core for demands of the proyect. > Thank you > > > --------------------------------------- > Posted through http://www.FPGARelated.com Ahhh, this is a _homework_ problem. You should have said that earlier. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 145206
> >Ok, I can do my own ROM via HDL but I need to use a CORE. What can I do?? >I have to use a Core for demands of the proyect. >Thank you > It's very difficult to 'genericise' the CoreGen outputs, although certainly possible for some types of cores. You could have a 'generic wrapper' that calls up different CoreGen outputs, for instance in VHDL using conditional generate statements (assuming that the company coding standards let you). Or you could just take the pain... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145207
On 29 Jan., 08:45, Kolja Sulimma <ksuli...@googlemail.com> wrote: > DPA =A0should be relatively easy on FPGAs. (But still hard) > Usually an attacker using DPA has to guess the workings of the > algorithm > in the device. They use lots of statisctics to find clock cycles that > show > a small difference in power consumption when the key has a 1 or 0 at > a certain bit. > > The advantage of an attack an on FPGA is, that the attacker can buy an > identical FPGA and start experimenting with his own keys and own > bitstreams Thinking about doing this for devices with OTP Key engaging a good industry spy may be cheaper and quicker.Article: 145208
On Mon, 01 Feb 2010 11:26:59 -0600 "RCIngham" <robert.ingham@n_o_s_p_a_m.gmail.com> wrote: > > > > >Ok, I can do my own ROM via HDL but I need to use a CORE. What can I > do?? > >I have to use a Core for demands of the proyect. > >Thank you > > > > It's very difficult to 'genericise' the CoreGen outputs, although > certainly possible for some types of cores. > > You could have a 'generic wrapper' that calls up different CoreGen > outputs, for instance in VHDL using conditional generate statements > (assuming that the company coding standards let you). > > Or you could just take the pain... > > > --------------------------------------- > Posted through http://www.FPGARelated.com Actually had to do something like that on a project I'm working on right now. I was building up a variable rate decimator (2:1 steps) by just chaining together 7 FIR halfbands (about the simplest block I'd be willing to call in a CoreGen on), and muxing between their outputs. All the filters had the same set of coefficients, but they all needed to be Gen'd independently to accomodate different input rates. Ultimately the best answer turned out to be writing a Python script that writes out the 7 nearly identical .XCO files, then calling CoreGen from the command line on all of them. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 145209
Goran_Bilski <goran.bilski@xilinx.com> writes: > I think there is a generic cable API (which should cover all types of > download cables, not just USB) but I don't know the status of it. What is the URL of this document? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145210
On Feb 1, 7:48=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > Goran_Bilski <goran.bil...@xilinx.com> writes: > > I think there is a generic cable API (which should cover all types of > > download cables, not just USB) but I don't know the status of it. > > What is the URL of this document? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? C:\ its internal Xilinx document. let's pray and hope it eventually comes public in some form AnttiArticle: 145211
> if-when Xilinx admits it has limited resources, then WHY Xilinx does not > allow 3rd party developer to help Xilinx customers? > > just a small decision to make: open up Xilinx USB Cable API, that is all > that Xilinx would have todo. Yes, this also takes resources as it may > require some maintenance and code cleanup from Xilinx, but if Xilinx > would do that cleanup, it may also be of benefit of Xilinx internal > developer team, so at the end Xilinx may actually win saving time not > spending it. > > I would love to re-think and re publish some of my old JTAG tools, but > without the ability to talk to Xilinx official USB cables it makes > little sense. > > Altera USB cables are EASY to talk, and there exist 3rd party software > that uses them. There is very little 3rd party software supporting > completly and without problems Xilinx USB cables. > > Antti Ideally both Xilinx and Altera should open source their ChipScope and SignalTap tools as well as the USB drivers. The Linux drivers for both companies are pretty terrible, if they were GPLed they could be incorporated into the Linux kernel which would make live a lot easier for both their customers and them. The only XP system that I maintain is an old machine that I use for SignalTap and Chipscope. When I tried to use SignalTap on CentOS5.4 on the same box it was unable to find the device about 95% of the time. Last year I had similar problems at a customer site using Chipscope on CentOS. If ChipScope and SignalTap worked reliably on Linux I'd dump the XP partition in a heartbeat. I don't think the debug tools are the family jewels for either company, buying decisions are made based on the devices. The synthesis and place and route tools have a huge impact on the performance of the parts so those clearly have to be closed source. But ChipScope and SignalTap only effect the performance of the users. If they were open sourced I'd bet their deficiencies would be fixed pretty quickly.Article: 145212
bellatoise wrote:
> Ok, I can do my own ROM via HDL but I need to use a CORE. What can I do??
> I have to use a Core for demands of the proyect.
> Thank you
If I synthesize working HDL code for a specific device, I have a core.
core = synthesis - source.
If I have the source code for some rom, say
http://mysite.verizon.net/miketreseler/sync_rom.vhd
Then I can make rom cores for brands A-X by running synthesis
and then hiding the source code.
-- Mike Treseler
Article: 145213Goran_Bilski wrote: > > If you have a design where you want to modify the BRAM contents, > data2mem is the tool to use. Yes, to some extent. Especially if the whole chunk of memory you are interested in lives in a single BRAM. If it is spread over several BRAMS things become a lot uglier. And as others mentioned it is very useful to bee able to peek inside the BRAM and change contents without a full cycle. When debugging simple soft CPU cores nothing beats Altera's memory editor. As for the cable I think it was really stupid to close the design. Yes, they could sell for $300 a box that costs $20 to make but this extra revenue is probably a lot less than losses from bad publicity. And now ebay is full of reverse engineered USB cables from China anyway. -Alex. --- news://freenews.netfront.net/ - complaints: news@netfront.net ---Article: 145214
On Jan 29, 7:30 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote: >Just to be even handed about > this, the Altera people would benefit from looking at Xilinx's method of > doing timing analysis. Altera introduced a new timing tool a couple of > years ago and it still sucks. Xilinx produces an easy to read timing > report that you can look at in Emacs. It shows the fanout and delays of > each stage of the worst case paths, formatted as one line per level. > Xilinx also figures out derivative clocks automatically, all you have to > do is specify the reference clock speed and the tools automatically > figures out the rates and phase relationships of all of the outputs of > the PLL or DCM. The Altera tools forces you to do that by hand, what's > worse is that you can't even do it using the clock names, you have to > figure out the path to the output port of the PLL. Add the following couple of lines to your .sdc derive_pll_clocks derive_clock_uncertainty They would cover 99% of the cases you described above Timequest timing analyzer still sucks in some important aspects (e.g. support for reference pin in delay specifications inconsistent, output skew constrains don't work at all), but that particular part mostly works > Altera's report format > is utterly unusable, you are forced to look at worst case paths in the > GUI and what it puts out is nearly unreasonable. That's true. Timequest Analizer/Timequest Analizer GUI dichotomy makes absolutely no sense. And report formats are hard to follow in the text editor. > The bottom line is that > I do all of my timing closure using Xilinx tools even if the design is > targeted at an Altera part. Once the Xilinx version meets timing I run it > through Quartus and hope that I only have a couple of paths that need > fixing. Well, that's certainly sounds too extreme.Article: 145215
On Jan 29, 7:11 pm, Antti <antti.luk...@googlemail.com> wrote: > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > the memory editor > and well Altera has no data2mem possibility at all, what is real > problem. > What exactly data2mem can do, but quartus_cdb+quartus_asm can't? Except, of course, that quartus_cdb needs a whole db directory, which, at least for me, doesn't sound like a serious obstacle. Or do you feel that quartus_cdb is too high level?Article: 145216
On Feb 2, 1:41=A0am, Michael S <already5cho...@yahoo.com> wrote: > On Jan 29, 7:11 pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > > the memory editor > > and well Altera has no data2mem possibility at all, what is real > > problem. > > What exactly data2mem can do, but quartus_cdb+quartus_asm can't? > Except, of course, that quartus_cdb needs a whole db directory, which, > at least for me, doesn't sound like a serious obstacle. > Or do you feel that quartus_cdb is too high level? data2mem is standalone tool that doesnt need ANY design files except final BIT file and .text BMM file. any tool flows that use DESIGN intermediate files (Altera and Lattice flow) are not OK. if a company is serious about soft-core processor than that company should offer data2mem type of functionality. too PITA Altera does not listen. AnttiArticle: 145217
On Feb 2, 2:02 am, Antti <antti.luk...@googlemail.com> wrote: > On Feb 2, 1:41 am, Michael S <already5cho...@yahoo.com> wrote: > > > On Jan 29, 7:11 pm, Antti <antti.luk...@googlemail.com> wrote: > > > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > > > the memory editor > > > and well Altera has no data2mem possibility at all, what is real > > > problem. > > > What exactly data2mem can do, but quartus_cdb+quartus_asm can't? > > Except, of course, that quartus_cdb needs a whole db directory, which, > > at least for me, doesn't sound like a serious obstacle. > > Or do you feel that quartus_cdb is too high level? > > data2mem is standalone tool that doesnt need ANY design files > except final BIT file and .text BMM file. > Altera .sof file simply doesn't contain enough of information to make something like data2mem possible. > any tool flows that use DESIGN intermediate files (Altera and Lattice > flow) > are not OK. I know very little about X tools but I am pretty sure that the input to data2mem _is_ a design intermediate file, just in more compact and probably more specialized format than Altera db directory. > > if a company is serious about soft-core processor than that company > should offer data2mem type of functionality. > > too PITA Altera does not listen. > > Antti In Altera approach I don't like that in order to make quartus_cdb +quartus_asm work I need to install a full Quartus. What is even worse, I think quartus_asm requires non-free license. Those are real problems that shows that Altera fails to understand that in most organizations FPGA developement and software developement for FPGA-hosted soft cores is done by different people with different sets of skills and that developers on the software side hate to care about additional set of tools, esp. when these tools require quirky licensing, However I don't care in the slightest whether the input to my tool is a single file or the whole database consisting of multiple files and directories. That is, I don't care as long as I can easily move the database in question from place to place within a computer or between different computers.Article: 145218
On Mon, 1 Feb 2010 06:59:33 -0800 (PST), Sam <kerr.sam@gmail.com> wrote: |I have two designs for an Altera chip that use approximately 6,000 and |24,000 logic elements. I am looking at moving to Xilinx tools, but am |not sure how these numbers translate across manufacturers. I have seen |Xilinx FPGA with gate counts cited, but I am not sure what those |number mean. | |Can anyone provide some guidance in this? | |============== In my opinion about the best way to compare different vendor's FPGAs is not to use stated gate count. Instead look at the features like # of LUTs # of block ram # of multipliers # of DSP blocks It is better to compare the building blocks of the FPGA rather than an estimated gate count. jamesArticle: 145219
On Feb 1, 7:27=A0am, rickman <gnu...@gmail.com> wrote:
> On Feb 1, 7:32=A0am, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote:
>
> > hi there
>
> > =A0 I have an ADC chip which is working in the LVDS mode.
> > =A0The data out(D0+,D0-,......D13+ and D13-),along with data clock
> > out(DC0+,DC0-)
> > and out of range(OUR) are connected physically to Sparta 3a dsp.
>
> > =A0My question is how do I directly collect these LVDS signals in my sp=
arta
> > 3a dsp core.
>
> > =A0How do I get back my data in aa format I can work on?
>
> It is a little scary reading this question. =A0It makes me think you
> don't understand that an LVDS receiver only has two signals on the
> pins, but is converted to a single signal by the receiver. =A0Is that
> what you are missing? =A0If so, you need to make sure your LVDS signals
> are going to the receivers in matched pairs. =A0If you already
> understand this, then I am not clear on what you don't understand.
>
> In general, to use inputs to an FPGA, you have signal names in your
> HDL code which are inputs and outputs to the top level module. =A0A
> separate file, typically created using a special editor in the GUI,
> specifies the details of how these signals are to be mapped to the I/O
> pins. =A0Each maker has their own format for this file and typically
> other details are specified here, such as the I/O type (TTL, CMOS,
> LVDS, etc...), voltage levels, drive strength, etc... =A0 Often this
> same file also contains the timing constraints to be applied to the
> design while it is routed by the tool and analyzed to see if it meets
> timing.
>
> Is that what you needed?
>
> Rick
It actually isn't that trivial to hook up an LVDS part to a Spartan3A,
because there don't seem to be any simple, broadly-applicable examples
floating around. What is out there is a lot of contradictory,
confusing advice, and the docs aren't very helpful at all.
In particular, it's unclear what declarations and attributes go into
the .ucf file and what can be declared on the HDL side. After some
Googling and trial-and-error work, I ended up with a .UCF section like
this:
net "BUS_0_P<15>" LOC =3D "B15" | IOSTANDARD =3D "LVDS_33" | DIFF_TERM
=3D TRUE;
net "BUS_0_N<15>" LOC =3D "B14" | IOSTANDARD =3D "LVDS_33" | DIFF_TERM
=3D TRUE;
(repeat for other bus lines 14...0)
... and the following Verilog interface:
module LTC2217
(
input ADC_0_P_CLK,
input ADC_0_N_CLK,
input signed [15:0] BUS_0_P,
input signed [15:0] BUS_0_N,
(...)
);
//
// LVDS buffers
//
wire [15:0] B0;
wire ADC_0_CLK;
IBUFGDS #(.DIFF_TERM("TRUE"),
.IOSTANDARD("LVDS_33")
) SOURCE_SYNC_CLOCK_IN
(
.I(ADC_0_P_CLK),
.IB(ADC_0_N_CLK),
.O(ADC_0_CLK));
genvar i;
generate
for (i=3D0; i <=3D 15; i =3D i + 1)
begin: loop0
IBUFDS #(.DIFF_TERM("TRUE"),
.IOSTANDARD("LVDS_33")
) ibuf_d0
(
.I(BUS_0_P[i]),
.IB(BUS_0_N[i]),
.O(B0[i]));
end
endgenerate
In this case B0 is the name of the ADC bus that would be declared as a
single-ended input if LVDS weren't being used, and ADC_0_CLK is its
data-ready signal.
I'm not necessarily claiming that this is the "right" way to do it,
but it worked in my case.
-- john, KE5FX
Article: 145220On Feb 1, 9:25=A0pm, james <bu...@bud.u> wrote: > On Mon, 1 Feb 2010 06:59:33 -0800 (PST), Sam <kerr....@gmail.com> > wrote: > > |I have two designs for an Altera chip that use approximately 6,000 and > |24,000 logic elements. I am looking at moving to Xilinx tools, but am > |not sure how these numbers translate across manufacturers. I have seen > |Xilinx FPGA with gate counts cited, but I am not sure what those > |number mean. > | > |Can anyone provide some guidance in this? > | > |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > In my opinion about the best way to compare different vendor's FPGAs > is not to use stated gate count. Instead look at the features like > > # of LUTs > # of block ram > # of multipliers > # of DSP blocks > > It is better to compare the building blocks of the FPGA rather than an > estimated gate count. > > james And make sure you do your own counting of features like LUTs. Xome companies like to count "imaginary" features like "Logic Cells" which don't exist in *anyone's* FPGAs. RickArticle: 145221
On Feb 2, 2:56=A0am, Michael S <already5cho...@yahoo.com> wrote: > On Feb 2, 2:02 am, Antti <antti.luk...@googlemail.com> wrote: > > > > > On Feb 2, 1:41 am, Michael S <already5cho...@yahoo.com> wrote: > > > > On Jan 29, 7:11 pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > > > > the memory editor > > > > and well Altera has no data2mem possibility at all, what is real > > > > problem. > > > > What exactly data2mem can do, but quartus_cdb+quartus_asm can't? > > > Except, of course, that quartus_cdb needs a whole db directory, which= , > > > at least for me, doesn't sound like a serious obstacle. > > > Or do you feel that quartus_cdb is too high level? > > > data2mem is standalone tool that doesnt need ANY design files > > except final BIT file and .text BMM file. > > Altera .sof file simply doesn't contain enough of information to make > something like data2mem possible. > > > any tool flows that use DESIGN intermediate files (Altera =A0and Lattic= e > > flow) > > are not OK. > > I know very little about X tools but I am pretty sure that the input > to data2mem _is_ =A0a design intermediate file, just in more compact and > probably more specialized format than Altera db directory. > > > > > if a company is serious about soft-core processor than that company > > should offer data2mem type of functionality. > > > too PITA Altera does not listen. > > > Antti > > In Altera approach I don't like that in order to make quartus_cdb > +quartus_asm work I need to install a full Quartus. What is even > worse, I think quartus_asm requires non-free license. > Those are real problems that shows that Altera fails to understand > that in most organizations FPGA developement and software developement > for FPGA-hosted soft cores is done by different people with different > sets of skills and that developers on the software side hate to care > about additional set of tools, esp. when these tools require quirky > licensing, > However I don't care in the slightest whether the input to my tool is > a single file or the whole database consisting of multiple files and > directories. That is, =A0I don't care as long as I can easily move the > database in question from place to place within a computer or between > different computers. if you DO NOT KNOW, then DO NOT TALK. data2mem uses FINAL bitstream only no interim files. you can take the BIT file and configure the FPGA then you can take the same BIT file, feed it into data2mem and configure an FPGA this is not possible with Altera or Lattice tools which both require design files (not final configuration file) to work AnttiArticle: 145222
On Feb 2, 2:56=A0am, Michael S <already5cho...@yahoo.com> wrote: > On Feb 2, 2:02 am, Antti <antti.luk...@googlemail.com> wrote: > > > > > On Feb 2, 1:41 am, Michael S <already5cho...@yahoo.com> wrote: > > > > On Jan 29, 7:11 pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > but.. DATA2MEM is MUCH more important (yeah for the customers) then > > > > the memory editor > > > > and well Altera has no data2mem possibility at all, what is real > > > > problem. > > > > What exactly data2mem can do, but quartus_cdb+quartus_asm can't? > > > Except, of course, that quartus_cdb needs a whole db directory, which= , > > > at least for me, doesn't sound like a serious obstacle. > > > Or do you feel that quartus_cdb is too high level? > > > data2mem is standalone tool that doesnt need ANY design files > > except final BIT file and .text BMM file. > > Altera .sof file simply doesn't contain enough of information to make > something like data2mem possible. > > > any tool flows that use DESIGN intermediate files (Altera =A0and Lattic= e > > flow) > > are not OK. > > I know very little about X tools but I am pretty sure that the input > to data2mem _is_ =A0a design intermediate file, just in more compact and > probably more specialized format than Altera db directory. > > > > > if a company is serious about soft-core processor than that company > > should offer data2mem type of functionality. > > > too PITA Altera does not listen. > > > Antti > > In Altera approach I don't like that in order to make quartus_cdb > +quartus_asm work I need to install a full Quartus. What is even > worse, I think quartus_asm requires non-free license. > Those are real problems that shows that Altera fails to understand > that in most organizations FPGA developement and software developement > for FPGA-hosted soft cores is done by different people with different > sets of skills and that developers on the software side hate to care > about additional set of tools, esp. when these tools require quirky > licensing, > However I don't care in the slightest whether the input to my tool is > a single file or the whole database consisting of multiple files and > directories. That is, =A0I don't care as long as I can easily move the > database in question from place to place within a computer or between > different computers. Hi, SOF file or RBT file could be used the same BIT file is used. there is no technical problem with that. the BIT file does also not include the BRAM mapping information in it this is supplied with separate TEXT file that simple tells the instance name to X Y location mapping to the primitives. similar tool for Altera and Lattice WOULD be possible. maybe you do not care, but the need to have FULL QUARTUS installed and and to move ALL DATABASE is something much different than having 1) a final BIT file 2) bram mapping text file 3) small commandline utility to update the BIT file AnttiArticle: 145223
Could some Xilinx guru please help ? I have the following module
synthesized on Xilinix ISE 11.1. I am getting a message at the end of
synthesis that no clock exists for design - could some please kindly
explain what it means ?
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:08:55 02/02/2010
// Design Name:
// Module Name: GetTail
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GetTail(
input [0:0] clock,
input [0:511] inarr,
input [0:31] inpriority,
input [0:31] intail,
input [0:31] innum,
input [0:31] toppriority,
input [0:31] outtail
);
parameter MAX = 512;
parameter DATA_WIDTH = 32;
reg [0 : 31] localtail;
initial
begin
localtail = intail;
end
always @ (posedge clock)
if(inpriority == 0)
begin
if(innum > 0 &&
inarr[localtail] == 0 &&
inarr[localtail + 1] == 1)
begin
localtail = localtail + 1;
end
else if(innum > 0 &&
localtail == MAX - 1 &&
inarr[localtail] == 0)
begin
localtail = 0;
end
end
else if(inpriority > 0)
begin
localtail = toppriority;
end
endmodule
Any hints, suggestions would be of immense help - thanks in advance.
Article: 145224On Feb 2, 7:28=A0am, Daku <dakup...@gmail.com> wrote: > Could some Xilinx guru please help ? I have the following module > synthesized on Xilinix ISE 11.1. I am getting a message at the end of > synthesis that no clock exists for design - could some please kindly > explain what it means ? > > `timescale 1ns / 1ps > /////////////////////////////////////////////////////////////////////////= // /////// > // Company: > // Engineer: > // > // Create Date: =A0 =A000:08:55 02/02/2010 > // Design Name: > // Module Name: =A0 =A0GetTail > // Project Name: > // Target Devices: > // Tool versions: > // Description: > // > // Dependencies: > // > // Revision: > // Revision 0.01 - File Created > // Additional Comments: > // > /////////////////////////////////////////////////////////////////////////= // /////// > module GetTail( > =A0 =A0 input [0:0] clock, > =A0 =A0 input [0:511] inarr, > =A0 =A0 input [0:31] inpriority, > =A0 =A0 input [0:31] intail, > =A0 =A0 input [0:31] innum, > =A0 =A0 input [0:31] toppriority, > =A0 =A0 input [0:31] outtail > =A0 =A0 ); > > parameter MAX =3D 512; > parameter DATA_WIDTH =3D 32; > > reg [0 : 31] localtail; > > initial > =A0begin > =A0 localtail =3D intail; > =A0end > > always @ (posedge clock) > =A0 if(inpriority =3D=3D 0) > =A0 =A0begin > =A0 =A0 =A0 if(innum > 0 =A0&& > =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0 && > =A0 =A0 =A0 =A0 =A0inarr[localtail + 1] =3D=3D 1) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0localtail =3D localtail + 1; > =A0 =A0 =A0 =A0 end > > =A0 =A0 =A0 else if(innum > 0 && > =A0 =A0 =A0 =A0 =A0 =A0 =A0localtail =3D=3D MAX - 1 && > =A0 =A0 =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0) > =A0 =A0 =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 =A0localtail =3D 0; > =A0 =A0 =A0 =A0 =A0end > =A0 end > =A0 else if(inpriority > 0) > =A0 =A0begin > =A0 =A0 localtail =3D toppriority; > =A0 =A0end > > endmodule > > Any hints, suggestions would be of immense help - thanks in advance. any designs with NO OUTPUT ports will be considered EMTPY designs so EVERYTHING is optimized away what leads to error message. Antti
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