Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
hi everyone,
I need to transfer 16 bytes data block (a packet of 16 bytes data) from PC
to DE2 board and then the DE2 board will send the data back to PC.
I’m use the firmware of device controller of isp1362 chip on de2 board to
transfer the data.
below is one part of my codings:
(this is the coding from interrupt service routine,ISR.c)
void Isr_Ep02Done(void)
{
unsigned char bbuf[16];
int i = 0;
Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP02);
Hal4D13_ReadEndpoint(EPINDEX4EP02,&bbuf, 16); //error was found here
if( sendCount < length)
{
Hal4D13_WriteEndpoint(EPINDEX4EP02, data + sendCount, 16);
Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP02);
sendCount += 16;
if(sendCount > length)
{
sendCount = 0;
//memset(data, 0, sizeof(char));
length = 0;
for( i = 0; i < 65; i++)
data[i] = 0;
}
}
}
the error I get from NIOS II IDE : passing arg 2 of 'Hal4D13_ReadEndpoint'
from imcompatible pointer type.
can someone give me idea how to debug this?
ps:#define EPINDEX4EP02 0x3
USHORT Hal4D13_ReadEndpoint(UCHAR bEPIndex, UCHAR * buf, USHORT len);
USHORT Hal4D13_ReadEndpointWOClearBuffer(UCHAR bEPIndex, UCHAR * buf,
USHORT len);
USHORT Hal4D13_WriteEndpoint(UCHAR bEPIndex, UCHAR * buf, USHORT len);
Thanks,
summer
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 145151On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote: > Antti, > > Oh, you are so kind! > > Really, the way to set initial conditions is in your HDL code. > > For BRAM, there is a whole app note on how to use the data2bram utility > to set BRAM contents. > > http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > > I would argue that we are (trying to) prevent poor coding practices, > which lead to errors, and poor HDL code, > > Austin Austin, The ability to change memories or registers has nothing to do with poor coding practices. When you are running a hardware testbench it would be incredibly useful to be able to change the contents of a register in real time rather then having to place and route the design again. Changing a register allows you to be able to select different tests or test conditions. There also ought to be a way to add some signals to ChipScope or SignalTap in a few minutes. The so called quick recompiles aren't quick at all. Speed of adding a few additional signals is an area where both tools are deficient. I use both Xilinx and Altera tools. The place where Xilinx tools are noticeably inferior to Altera's is with ChipScope vs SignalTap. The ChipScope software doesn't even under stand the concept of buses, it requires you to group things together by hand which is a tedious process, SignalTap does this automatically. I wonder if either Xilinx or Altera's tools people bother to look at each others stuff. Chipscope hasn't been improved for years, there is no excuse for it to be as poor as it is, the Xilinx people ought to look at SignalTap and at least match it's features. Just to be even handed about this, the Altera people would benefit from looking at Xilinx's method of doing timing analysis. Altera introduced a new timing tool a couple of years ago and it still sucks. Xilinx produces an easy to read timing report that you can look at in Emacs. It shows the fanout and delays of each stage of the worst case paths, formatted as one line per level. Xilinx also figures out derivative clocks automatically, all you have to do is specify the reference clock speed and the tools automatically figures out the rates and phase relationships of all of the outputs of the PLL or DCM. The Altera tools forces you to do that by hand, what's worse is that you can't even do it using the clock names, you have to figure out the path to the output port of the PLL. Altera's report format is utterly unusable, you are forced to look at worst case paths in the GUI and what it puts out is nearly unreasonable. The bottom line is that I do all of my timing closure using Xilinx tools even if the design is targeted at an Altera part. Once the Xilinx version meets timing I run it through Quartus and hope that I only have a couple of paths that need fixing.Article: 145152
On Jan 29, 7:30=A0pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote: > > Antti, > > > Oh, you are so kind! > > > Really, the way to set initial conditions is in your HDL code. > > > For BRAM, there is a whole app note on how to use the data2bram utility > > to set BRAM contents. > > >http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > > > I would argue that we are (trying to) prevent poor coding practices, > > which lead to errors, and poor HDL code, > > > Austin > > Austin, > > The ability to change memories or registers has nothing to do with poor > coding practices. When you are running a hardware testbench it would be > incredibly useful to be able to change the contents of a register in real > time rather then having to place and route the design again. Changing a > register allows you to be able to select different tests or test > conditions. There also ought to be a way to add some signals to ChipScope > or SignalTap in a few minutes. The so called quick recompiles aren't > quick at all. Speed of adding a few additional signals is an area where > both tools are deficient. > > I use both Xilinx and Altera tools. The place where Xilinx tools are > noticeably inferior to Altera's is with ChipScope vs SignalTap. The > ChipScope software doesn't even under stand the concept of buses, it > requires you to group things together by hand which is a tedious process, > SignalTap does this automatically. > > I wonder if either Xilinx or Altera's tools people bother to look at each > others stuff. Chipscope hasn't been improved for years, there is no > excuse for it to be as poor as it is, the Xilinx people ought to look at > SignalTap and at least match it's features. Just to be even handed about > this, the Altera people would benefit from looking at Xilinx's method of > doing timing analysis. Altera introduced a new timing tool a couple of > years ago and it still sucks. Xilinx produces an easy to read timing > report that you can look at in Emacs. It shows the fanout and delays of > each stage of the worst case paths, formatted as one line per level. > Xilinx also figures out derivative clocks automatically, all you have to > do is specify the reference clock speed and the tools automatically > figures out the rates and phase relationships of all of the outputs of > the PLL or DCM. The Altera tools forces you to do that by hand, what's > worse is that you can't even do it using the clock names, you have to > figure out the path to the output port of the PLL. Altera's report format > is utterly unusable, you are forced to look at worst case paths in the > GUI and what it puts out is nearly unreasonable. The bottom line is that > I do all of my timing closure using Xilinx tools even if the design is > targeted at an Altera part. Once the Xilinx version meets timing I run it > through Quartus and hope that I only have a couple of paths that need > fixing. thanks General! yes, both REGISTER (LUT and distributed RAM) as BRAM can be changed via JTAG and ability todo so would be of benefit for Xilinx Customers. As of chipscope hm, it isnt that bad, but it could be better. As of of using X tools, eh I use X tools to make Actel designs..:) I setup Xilinx project, create BRAM modules that look like actel RAM's and then run that on some Xilinx board with Chipscope added to the design. and finally will then replace some modules to target Actel AnttiArticle: 145153
Hi I want to synthesize a completely empty design, no clocks no combo and no sequential logic for a xilinx FPGA using ISE. THe problem is if I try to implement module dummy_fpga (); endmodule The tool synthesizes it but fails to translate it. I wanted to create an empty design with no inputs and no outputs and then use bit gen to float all unused IOs. This was I could measure the quiescent current of the xilinx FPGA. Any suggestions? ThanksArticle: 145154
On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > Hi > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. > THe problem is > if I try to implement =A0module dummy_fpga (); endmodule > The tool synthesizes it but fails to translate it. > I wanted to create an empty design with no inputs and no outputs and > then use bit gen to float all unused IOs. This was I could measure the > quiescent current of the xilinx FPGA. > Any suggestions? > Thanks you do have to have one output or the flow will fail well, design with no IO's could actually be useful, if all data transfer goes over BSCAN, but the tools require one top level port to be present AnttiArticle: 145155
On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > Hi > > I want to synthesize a completely empty design, no clocks no combo and > > no sequential logic for a xilinx FPGA using ISE. > > THe problem is > > if I try to implement =A0module dummy_fpga (); endmodule > > The tool synthesizes it but fails to translate it. > > I wanted to create an empty design with no inputs and no outputs and > > then use bit gen to float all unused IOs. This was I could measure the > > quiescent current of the xilinx FPGA. > > Any suggestions? > > Thanks > > you do have to have one output or the flow will fail > > well, design with no IO's could actually be useful, if all data > transfer goes over BSCAN, but the tools require one top level port to > be present > > Antti It would seem to me that pulling the PROG_B pin low would put the device into as quiescent state as you can get. But as for a post- programmed state I don't think driving at least one I/O would change the quiescent current significantly vs "no design". Regards, GaborArticle: 145156
On Jan 29, 10:21=A0am, Gabor <ga...@alacron.com> wrote: > On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > > Hi > > > I want to synthesize a completely empty design, no clocks no combo an= d > > > no sequential logic for a xilinx FPGA using ISE. > > > THe problem is > > > if I try to implement =A0module dummy_fpga (); endmodule > > > The tool synthesizes it but fails to translate it. > > > I wanted to create an empty design with no inputs and no outputs and > > > then use bit gen to float all unused IOs. This was I could measure th= e > > > quiescent current of the xilinx FPGA. > > > Any suggestions? > > > Thanks > > > you do have to have one output or the flow will fail > > > well, design with no IO's could actually be useful, if all data > > transfer goes over BSCAN, but the tools require one top level port to > > be present > > > Antti > > It would seem to me that pulling the PROG_B pin low would put the > device into as quiescent state as you can get. =A0But as for a post- > programmed state I don't think driving at least one I/O would change > the quiescent current significantly vs "no design". > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - That won't work as when PROG_B is pulled low this starts house cleaning activities and the current will spike (from quiescient) One input and Output with no toggling activities =3D Quiescient power. Ed McGettigan -- Xilinx Inc.Article: 145157
On Jan 29, 8:38=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jan 29, 10:21=A0am, Gabor <ga...@alacron.com> wrote: > > > > > > > On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > > > Hi > > > > I want to synthesize a completely empty design, no clocks no combo = and > > > > no sequential logic for a xilinx FPGA using ISE. > > > > THe problem is > > > > if I try to implement =A0module dummy_fpga (); endmodule > > > > The tool synthesizes it but fails to translate it. > > > > I wanted to create an empty design with no inputs and no outputs an= d > > > > then use bit gen to float all unused IOs. This was I could measure = the > > > > quiescent current of the xilinx FPGA. > > > > Any suggestions? > > > > Thanks > > > > you do have to have one output or the flow will fail > > > > well, design with no IO's could actually be useful, if all data > > > transfer goes over BSCAN, but the tools require one top level port to > > > be present > > > > Antti > > > It would seem to me that pulling the PROG_B pin low would put the > > device into as quiescent state as you can get. =A0But as for a post- > > programmed state I don't think driving at least one I/O would change > > the quiescent current significantly vs "no design". > > > Regards, > > Gabor- Hide quoted text - > > > - Show quoted text - > > That won't work as when PROG_B is pulled low this starts house > cleaning activities and the current will spike (from quiescient) > > One input and Output with no toggling activities =3D Quiescient power. > > Ed McGettigan > -- > Xilinx Inc. why the input??Article: 145158
On Jan 29, 9:16=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > With knowledge of the crypto algorithm - which they have in case of > the FPGA > - they can now simulate what the power consumption pattern for a 1 in > the > position X of the key would be compared to a 0 at that position. > > This is still hard work but in many cases a lot faster than a brute > force attack. Based on your explanation it seems fairly trivial: * hook a fast V/I meter to the power supplies of an FPGA * via JTAG load various known keys into the FPGA * via the configuration interface load various known bitstreams into the FPGA * Average over many trials, look for differences in V/I with key changes. This whole process can be automated. The loading process is quick, and assuming a small FPGA probably completes in a few seconds. Using a fast CPU the required analysis is equally quick. So, with some common lab equipment and a few days unattended processing time it's a cinch. As you note, if you can break one FPGA in a family, you've probably broken them all, so once you've got the initial analysis worked out you can probably crack any device with similar architecture from a few averaged samples of the configuration process. Given that we've solved that problem, what measures have the FPGA vendors taken to prevent any schmoe with time on his hands from going into the reverse engineering business? Seems like their security measures are fundamentally broken unless there is something else going on we don't know about. EricArticle: 145159
On Jan 29, 1:42=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Jan 29, 8:38=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Jan 29, 10:21=A0am, Gabor <ga...@alacron.com> wrote: > > > > On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > > > > Hi > > > > > I want to synthesize a completely empty design, no clocks no comb= o and > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > THe problem is > > > > > if I try to implement =A0module dummy_fpga (); endmodule > > > > > The tool synthesizes it but fails to translate it. > > > > > I wanted to create an empty design with no inputs and no outputs = and > > > > > then use bit gen to float all unused IOs. This was I could measur= e the > > > > > quiescent current of the xilinx FPGA. > > > > > Any suggestions? > > > > > Thanks > > > > > you do have to have one output or the flow will fail > > > > > well, design with no IO's could actually be useful, if all data > > > > transfer goes over BSCAN, but the tools require one top level port = to > > > > be present > > > > > Antti > > > > It would seem to me that pulling the PROG_B pin low would put the > > > device into as quiescent state as you can get. =A0But as for a post- > > > programmed state I don't think driving at least one I/O would change > > > the quiescent current significantly vs "no design". > > > > Regards, > > > Gabor- Hide quoted text - > > > > - Show quoted text - > > > That won't work as when PROG_B is pulled low this starts house > > cleaning activities and the current will spike (from quiescient) > > > One input and Output with no toggling activities =3D Quiescient power. > > > Ed McGettigan > > -- > > Xilinx Inc. > > why the input?? If your output can not be traced back to an input, it will be optimized away. You could drive the output with a constant value, so the actual input pin is not needed, but the output has to be driven by something. But as you have discovered, this is a tool issue, not a fundamental issue with the design process. So the tools might just require an input, but I doubt it. RickArticle: 145160
One output, driven from a constant, should be all you need. Just make sure your one output is not driving a load in your test/ measurement setup. And make sure your IO pins are not pulled down (internal pullups are enabled on unused pins) AndyArticle: 145161
On Jan 28, 11:59=A0am, Morppheu <jdemam...@gmail.com> wrote: > On Jan 13, 1:35=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I'm not sure where this thread started, I don't see a message before > > Nico's post Jan 11. =A0Did you post your code? > > > Your design is using about 10% of the LUTs as routing, which does tend > > to happen when your LUT usage rises using up much of the routing > > resources. =A0The main offender that I can see is the use of almost 50% > > of the LUTs as DP RAM. =A0I am guessing that these are being used for > > FIFO buffers. =A0Can you reduce the number of LUTs used for buffering o= r > > are they all required? > > > As to the clocking issue, I don't know what the problem is exactly. > > Why can't you use the E1 clock? =A0What pin is the E1 clock connected t= o > > on the S3 part? =A0I would hope it is connected to a DCM or at least a > > clock input. > > > It is hard to suggest much more without more insight into what your > > design is doing. > > > Rick > > > On Jan 12, 9:00=A0am, Morppheu <jdemam...@gmail.com> wrote:> > Why use = the internal clock? Isn't the MT9076 free running when it > > > > doesn't see a line-sync? > > > > Yes, the MT goes free running when its not sinced. > > > But the MT9076 is a module on my hardware. I can mount the backplane > > > with or without the MT9076 chip. > > > That is the point, what to do when I have the E1 module installed. Ho= w > > > to interface with it. > > > My FPGA is an Spartan 3e S100 (almost 100% full): > > > > Logic Utilization: > > > =A0 Total Number Slice Registers: =A0 =A0 =A0 737 out of =A0 1,920 = =A0 38% > > > =A0 =A0 Number used as Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 731 > > > =A0 =A0 Number used as Latches: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A06 > > > =A0 Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 956 out of =A0 1,= 920 =A0 49% > > > Logic Distribution: > > > =A0 Number of occupied Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0959 out of > > > 960 =A0 99% > > > =A0 =A0 Number of Slices containing only related logic: =A0 =A0 959 o= ut of > > > 959 =A0100% > > > =A0 =A0 Number of Slices containing unrelated logic: =A0 =A0 =A0 =A0 = =A00 out of > > > 959 =A0 =A00% > > > =A0 =A0 =A0 *See NOTES below for an explanation of the effects of unr= elated > > > logic > > > Total Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A01,910 out of =A0 1,9= 20 =A0 99% > > > =A0 Number used as logic: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0956 > > > =A0 Number used as a route-thru: =A0 =A0 =A0 =A0 181 > > > =A0 Number used for Dual Port RAMs: =A0 =A0 =A0768 > > > =A0 =A0 (Two LUTs used per Dual Port RAM) > > > =A0 Number used as Shift registers: =A0 =A0 =A0 =A05 > > > =A0 Number of bonded IOBs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 93 out of =A0 = =A0 108 =A0 86% > > > =A0 =A0 IOB Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A019 > > > =A0 Number of Block RAMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A04 out of =A0= =A0 =A0 4 =A0100% > > > =A0 Number of GCLKs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 9 out of= =A0 =A0 =A024 =A0 37% > > > =A0 Number of DCMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A02 out = of =A0 =A0 =A0 2 =A0100% > > > > Another thing. How to reduce the area usage?? > > > > Thanks! > > Hey guys! > Thanks for your reply. =3D) > I will explain my problem. > I have a internal clock of 16.384MHz (50ppm) and a E1 interface > (MT9076B). > The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame > sync signal, active low). > When the E1 is installed (MT9076 chip is soldered at motherboard), I > use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e > S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I > use to send the E1 data to MT9076, aligned with F0 signal. > What I want to do is use only the internal 2.048MHz (generate from > 16.384MHz clock, with DCM) and interface with E1 through a FIFO. > Here is the problem. Internal and external clock are different, so the > FIFO will go underflow or overflow... > What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 > goes free running I will have problem anyway. > > Waiting suggestions.. =3D) > > Thanks! I guess I don't understand how things are connected. You seem to have three clocks in the system and I don't know when (or why) you want to use what clock. I understand that the E1 clock at 2.048 MHz is used to clock data from the interface. I think you want to sync the internal 16.384 MHz clock to the E1 so you can process data faster than the 2.048 MHz clock allows. But what is the clock from the MT9076 chip used for? If the MT clock is used to clock data when the E1 clock is not present, you will need to mux the two clocks (E1 and MT) before using them to sync to the internal clock. Does that do the job you are looking for? RickArticle: 145162
Differential Power Attack has been known (and used) for many years now, (it is not new at all) DPA was originally used to hack credit cards in Europe, and there are many other recorded (successful) attacks, as well. CRI is making a lot of noise about their alleged crack of one Virtex II Pro, 3DES key (168 bits), on one platform designed to facilitate just such attacks. Is this claim confirmed? By whom? If I loaded the "secret" key, and I know the value, and then I claim I "discovered" its value ... seems that the real "key" here is to authentication: who do you believe, and how can you be sure? The 'motivation' for this seems unusually coincidental, as well... They also own a lot of IP, for the express purpose of countering DPA .... and making money. They are looking for business. If you want to protect yourself from DPA (and you think their methods might work), and you are very rich, give them a call. Seems they need money. Don't we all! See 'motivation', above. The job of preventing ALL attacks, is known as anti tamper: detect an attack, and remove all information of value (prevent the attack). Anti-tamper is not "owned" by CRI, and anyone can implement AT techniques, and, in any system that is supposed to be secure, AT is required. "Denial of Service" is another attack to worry about, and if you have physical access to a device, then a hammer is sufficient to conclude an effective "denial of service." Removing the batteries, or unplugging the system can also be very effective. So, security is a big field, with many things to think (anticipate) about. DPA is just one attack, of many. Like I said, if you are worried about DPA, then you should also be worried about DoS, AT, and many other forms of attack. By itself, DPA might be the least of your concerns. If you already work in this field, you already know that there are existing solutions for all of these attacks. Attackers have a natural advantage: they can think up new attacks all day long. Defenders have it tough: they must defend against ALL present, and future attacks, right now. And, there are not only threats to your systems, there are threats to your way of doing business: If you are unfortunate enough to have implemented a defense that someone else has a patent on, then you will face an entirely different threat: someone demanding money! I wish CRI all the best in their endeavors, AustinArticle: 145163
On Jan 29, 10:42=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Jan 29, 8:38=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Jan 29, 10:21=A0am, Gabor <ga...@alacron.com> wrote: > > > > On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > > > > Hi > > > > > I want to synthesize a completely empty design, no clocks no comb= o and > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > THe problem is > > > > > if I try to implement =A0module dummy_fpga (); endmodule > > > > > The tool synthesizes it but fails to translate it. > > > > > I wanted to create an empty design with no inputs and no outputs = and > > > > > then use bit gen to float all unused IOs. This was I could measur= e the > > > > > quiescent current of the xilinx FPGA. > > > > > Any suggestions? > > > > > Thanks > > > > > you do have to have one output or the flow will fail > > > > > well, design with no IO's could actually be useful, if all data > > > > transfer goes over BSCAN, but the tools require one top level port = to > > > > be present > > > > > Antti > > > > It would seem to me that pulling the PROG_B pin low would put the > > > device into as quiescent state as you can get. =A0But as for a post- > > > programmed state I don't think driving at least one I/O would change > > > the quiescent current significantly vs "no design". > > > > Regards, > > > Gabor- Hide quoted text - > > > > - Show quoted text - > > > That won't work as when PROG_B is pulled low this starts house > > cleaning activities and the current will spike (from quiescient) > > > One input and Output with no toggling activities =3D Quiescient power. > > > Ed McGettigan > > -- > > Xilinx Inc. > > why the input??- Hide quoted text - > > - Show quoted text - Why not? I find it simpler that way since design of A=3DB always works. Ed McGettigan -- XilinxArticle: 145164
EE EE <eengr.usa@gmail.com> wrote: > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. In the old days there was LCAEdit that would allow one to edit the design at the LUT/switch level. I think if you open LTAEdit you can just say SAVE without adding anything and you get an empty design. I thought a similar tool still existed. Otherwise, you need more control over the output than synthesis tools will give you. -- glenArticle: 145165
On Jan 29, 2:57=A0pm, austin <aus...@xilinx.com> wrote: > Differential Power Attack has been known (and used) for many years > now, (it is not new at all) > > DPA was originally used to hack credit cards in Europe, and there are > many other recorded (successful) attacks, as well. > > CRI is making a lot of noise about their alleged crack of one Virtex > II Pro, 3DES key (168 bits), on one platform designed to facilitate > just such attacks. =A0Is this claim confirmed? =A0By whom? =A0If I loaded > the "secret" key, and I know the value, and then I claim I > "discovered" its value ... seems that the real "key" here is to > authentication: =A0who do you believe, and how can you be sure? =A0The > 'motivation' for this seems unusually coincidental, as well... > > They also own a lot of IP, for the express purpose of countering > DPA .... and making money. =A0They are looking for business. =A0If you > want to protect yourself from DPA (and you think their methods might > work), and you are very rich, give them a call. =A0Seems they need > money. =A0Don't we all! =A0See 'motivation', above. > > The job of preventing ALL attacks, is known as anti tamper: =A0detect an > attack, and remove all information of value (prevent the attack). > > Anti-tamper is not "owned" by CRI, and anyone can implement AT > techniques, and, in any system that is supposed to be secure, AT is > required. > > "Denial of Service" is another attack to worry about, and if you have > physical access to a device, then a hammer is sufficient to conclude > an effective "denial of service." =A0Removing the batteries, or > unplugging the system can also be very effective. > > So, security is a big field, with many things to think (anticipate) > about. =A0DPA is just one attack, of many. > > Like I said, if you are worried about DPA, then you should also be > worried about DoS, AT, and many other forms of attack. =A0By itself, DPA > might be the least of your concerns. > > If you already work in this field, you already know that there are > existing solutions for all of these attacks. =A0Attackers have a natural > advantage: =A0they can think up new attacks all day long. =A0Defenders > have it tough: =A0they must defend against ALL present, and future > attacks, right now. > > And, there are not only threats to your systems, there are threats to > your way of doing business: =A0If you are unfortunate enough to have > implemented a defense that someone else has a patent on, then you will > face an entirely different threat: =A0someone demanding money! > > I wish CRI all the best in their endeavors, > > Austin Austin, Thanks for your insights. I was rather hoping you would jump in on this question. I'm pretty skeptical of the claimed vulnerabilities. I imagine that it's possible to extract a key with DPA under properly controlled conditions, but it seems to me that controlling the conditions for any random hardware that the black hats want to crack would be fairly difficult. As I mentioned to my boss when he pointed this article out to me, the first question that I ask when I read something like this is "What are they trying to sell?" and you've answered that one. In my case, we're protecting IP - we don't want our algorithms out there. Others may be protecting the processed data, or guarding against counterfeiting. Each of these requires a different web of protection, and bitstream encryption is just one strand in the web. Prudence dictates your web have more than one strand. EricArticle: 145166
On Jan 30, 6:47=A0am, EE EE <eengr....@gmail.com> wrote: > Hi > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. > THe problem is > if I try to implement =A0module dummy_fpga (); endmodule > The tool synthesizes it but fails to translate it. > I wanted to create an empty design with no inputs and no outputs and > then use bit gen to float all unused IOs. This was I could measure the > quiescent current of the xilinx FPGA. > Any suggestions? > Thanks As others have said, o=3Di is a tool-happy minimum. You might want to be more intelligent with test patterns tho, and try some pins that allow Hi or Low by IO bank. I have seen one programmable device, where the state of buried nodes was measurable on Icc, so design your test to catch the unexpected.... -jgArticle: 145167
On Jan 30, 2:05=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jan 29, 10:42=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Jan 29, 8:38=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Jan 29, 10:21=A0am, Gabor <ga...@alacron.com> wrote: > > > > > On Jan 29, 12:50=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > > On Jan 29, 7:47=A0pm, EE EE <eengr....@gmail.com> wrote: > > > > > > > Hi > > > > > > I want to synthesize a completely empty design, no clocks no co= mbo and > > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > > THe problem is > > > > > > if I try to implement =A0module dummy_fpga (); endmodule > > > > > > The tool synthesizes it but fails to translate it. > > > > > > I wanted to create an empty design with no inputs and no output= s and > > > > > > then use bit gen to float all unused IOs. This was I could meas= ure the > > > > > > quiescent current of the xilinx FPGA. > > > > > > Any suggestions? > > > > > > Thanks > > > > > > you do have to have one output or the flow will fail > > > > > > well, design with no IO's could actually be useful, if all data > > > > > transfer goes over BSCAN, but the tools require one top level por= t to > > > > > be present > > > > > > Antti > > > > > It would seem to me that pulling the PROG_B pin low would put the > > > > device into as quiescent state as you can get. =A0But as for a post= - > > > > programmed state I don't think driving at least one I/O would chang= e > > > > the quiescent current significantly vs "no design". > > > > > Regards, > > > > Gabor- Hide quoted text - > > > > > - Show quoted text - > > > > That won't work as when PROG_B is pulled low this starts house > > > cleaning activities and the current will spike (from quiescient) > > > > One input and Output with no toggling activities =3D Quiescient power= . > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > why the input??- Hide quoted text - > > > - Show quoted text - > > Why not? =A0I find it simpler that way since design of A=3DB always works= . > > Ed McGettigan > -- > Xilinx TOO COMPLICATED! LED <=3D '1'; is simpler as only one output pin is needed, it is the dummy design i use.Article: 145168
On Jan 30, 4:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Jan 30, 6:47=A0am, EE EE <eengr....@gmail.com> wrote: > > > Hi > > I want to synthesize a completely empty design, no clocks no combo and > > no sequential logic for a xilinx FPGA using ISE. > > THe problem is > > if I try to implement =A0module dummy_fpga (); endmodule > > The tool synthesizes it but fails to translate it. > > I wanted to create an empty design with no inputs and no outputs and > > then use bit gen to float all unused IOs. This was I could measure the > > quiescent current of the xilinx FPGA. > > Any suggestions? > > Thanks > > As others have said, o=3Di is a tool-happy minimum. > > You might want to be more intelligent with test patterns tho, and try > some pins that allow Hi or Low by IO bank. > > I have seen one programmable device, where the state of buried nodes > was measurable on Icc, so design your test to catch the unexpected.... > -jg o=3Di; is not needed o=3D'1'; is sufficient AnttiArticle: 145169
On Jan 30, 7:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > o=3Di; > > is not needed > > o=3D'1'; > > is sufficient but Sufficient to test only the o=3D1 case, by making the OP under user control, you can test both H and L outputs with one compile ;) -jgArticle: 145170
On Jan 30, 10:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Jan 30, 7:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > o=3Di; > > > is not needed > > > o=3D'1'; > > > is sufficient > > but Sufficient to test only the o=3D1 case, > by making the OP under user control, you can test > both H and L outputs with one compile ;) > -jg Jim, it was not about TESTING the output, it was about creating an EMPTY design. there is no need to test anything with empty design :) AnttiArticle: 145171
On Jan 30, 9:59=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Jan 30, 10:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > On Jan 30, 7:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > o=3Di; > > > > is not needed > > > > o=3D'1'; > > > > is sufficient > > > but Sufficient to test only the o=3D1 case, > > by making the OP under user control, you can test > > both H and L outputs with one compile ;) > > -jg > > Jim, it was not about TESTING the output, it was about creating an > EMPTY design. > there is no need to test anything with empty design :) > > Antti The OP wanted to "measure the quiescent current of the xilinx FPGA", and that can vary with H & L, so the best test coverage is to check both. He probably should also plot Icc vs Vin on a pin, so he can factor in non-cmos or level shifting effects, if needed. -jgArticle: 145172
On Jan 30, 11:18=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Jan 30, 9:59=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Jan 30, 10:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > On Jan 30, 7:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > o=3Di; > > > > > is not needed > > > > > o=3D'1'; > > > > > is sufficient > > > > but Sufficient to test only the o=3D1 case, > > > by making the OP under user control, you can test > > > both H and L outputs with one compile ;) > > > -jg > > > Jim, it was not about TESTING the output, it was about creating an > > EMPTY design. > > there is no need to test anything with empty design :) > > > Antti > > The OP wanted to "measure the quiescent current of the xilinx FPGA", > and that can vary with H & L, > so the best test coverage is to check both. > > He probably should also plot Icc vs Vin on a pin, so he can factor in > non-cmos or level shifting effects, if needed. > > -jg nono, he did not want measure the current in dependancy of the output being driven high or low, in the matter of fact he would have preffered the output to not be driven at all, so actually he should have made a desing that is as small as possible, and has one output that is always tristated. AnttiArticle: 145173
Hi Guys, Thank you all for the information you have given me. Cheers SudhirArticle: 145174
Hello, i want to split a number for example 1234 in 4 numbers 1,2,3,4 witch is the best way to do it? i was thinking of using this code tmp := number; o4 := number mod 10; tmp := tmp-o4; o3 := number mod 100; tmp := tmp-o3; o3 := o3/10; o2 := number mod 1000; tmp := tmp-o2; o2 := o2/100; o1 := number /1000; but i get an error: ERROR:HDLParsers:808 - "D:/Work/fpga/projects/stopWatch/nr.vhd" Line 53. * can not have such operands in this context. 10x in advance --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z