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Martin Thompson wrote:
> Personally, I'm impressed that I can write a simple description of my
> logic and get a complicated near-optimal synthesis result out in a
> large number of cases - I wonder if I'm alone? :)
I agree.
If it sims and meets timing I'm usually done.
But then, I don't need that last LUT and that last nS.
-- Mike Treseler
Article: 145051"stephen.craven@gmail.com" <stephen.craven@gmail.com> writes: >All, >Could someone point me to a board or boards that combine a modern FPGA >with multiple ethernet PHYs? The only multiple-ethernet board that I >have discovered is based on a V2P. >Thank you in advance. >Stephen I'm interested in the same subject, I'd like dual gige PHYs and either PCIX or PCIE 4 lane to be able to get a fdx gige capture to the host. I assume the board you are referring to is the Digilent NetFPGA which would do me other than the PCI host bus (which won't do full speed gig). Everything else that I've found so far is expensive. For instance a pair of gige PHYs (no fpga) is around $600 US, so I am much heartened by John's comment Enterpoint is coming out with a gige PHY daughter board, I have a pair of their 10/100s PHYS already which are the only reasonably priced ones I found (other than fpga4fun's dual channel, magnetics only, 10 only, no PHY on the dragon which is the cheapest way I've found of experimenting with ethernet :-)). There is a good list of fpga boards which specify bus and ethernet options if available at: http://www.fpga-faq.com/FPGA_Boards.shtml For me for now I have a Draqon PCI board (~ $300 US) from fpga4fun and as noted two of John's PHYs to see if I can actually do what I want before investing in something gig capable. It may be worth looking at the fpga4fun pcie board (which has a virtex5 in it but no PHYS) if you are cost sensitive like me. If you have money, then the list above does have boards though :-). I'd be interested in any boards that you find as well. Peter Van EppArticle: 145052
A colleague and I were hoping to set up unattended ILA data collection over long periods and changing conditions. I assumed that the ChipScope TCL support would provide a way to do that, but when I look more closely at the ChipScope Engine JTAG Tcl Interface, I find that most of its API provides only very low-level functionality. The API in question supports interrogating a device as to its number of ILA cores, but beyond that, all of the transactions would have to happen through JTAG data/instruction shift commands. I had hoped that the ICON or ILA documentation might at least describe the pertinent registers in those cores, but I seem unable even to find that, and all of my googling has been fruitless. Can it really be that nobody else has worked out unattended data collection with ChipScope? Please dispel that notion for me. Any pointers or suggestions would be appreciated.Article: 145053
On Jan 22, 2:59=A0pm, Neil Steiner <neil.stei...@east.isi.edu> wrote: > A colleague and I were hoping to set up unattended ILA data collection > over long periods and changing conditions. =A0I assumed that the ChipScop= e > TCL support would provide a way to do that, but when I look more closely > at the ChipScope Engine JTAG Tcl Interface, I find that most of its API > provides only very low-level functionality. > > The API in question supports interrogating a device as to its number of > ILA cores, but beyond that, all of the transactions would have to happen > through JTAG data/instruction shift commands. =A0I had hoped that the ICO= N > or ILA documentation might at least describe the pertinent registers in > those cores, but I seem unable even to find that, and all of my googling > has been fruitless. > > Can it really be that nobody else has worked out unattended data > collection with ChipScope? =A0Please dispel that notion for me. =A0Any > pointers or suggestions would be appreciated. I've been using Chipscope for 5 years now and the lack of high-level scripting is one of my major complaints (the other being that the UI bogs down when you create complex projects). It's fairly disappointing that it's so difficult to build complex testing environments with Chipscope - it seems like something that wouldn't be too hard to support. I ended up creating custom logic blocks to handle this which I interface via a SPI port to an off-chip ARM processor, then to a PC via USB. Not nearly as elegant as it could be if Chipscope had a somewhat higher-level API. EricArticle: 145054
On Jan 22, 9:44=A0am, "realwood" <realwood1...@163.com> wrote: > Hi, everybody: > =A0 =A0 I'm confused with offset constraint and its report recently. Can = anyone > help me? Thanks very much! > > =A0 =A0 "din" is a input data whose bus width is 32bit. =A0I set a offset > constraint : > > Net "din<31>" offset =3D IN 2ns before clk_in. Period of clk_in was > constrained to 6ns. And i got a result in P&R report: > > =A0 =A0 Constraint =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Request =A0= =A0 =A0 Actual > > din<31>offset... =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 2ns =A0 =A0 =A0 = =A0 =A0-3.17ns > > All constraints are met. > > =A0 =A0 According to my comprehension, din<31> can lag 3.17ns mostly behi= nd > rising edge of clk_in on the PAD. And after data path delay and clk path > delay, din<31> can be sampled at the first FF correcttly and exactly. Am = i > right? > > =A0 =A0 But if din<31> arrive 2ns before clk_in rising edge just as offse= t > constraint said, after delay of data path and clk path, clk rising edge > will present at nearly (2+3.17)ns with respect to din<31>, that is unstab= le > period of din<31>. > > =A0 =A0 How to explain this? > > =A0 =A0 Thanks, guys! =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You an explain this by looking at the other half of the equation. Your hold time will be very large, meaning that you're not clocking in the data on the cycle you intended to, unless the input signal also meets the hold time requirement.Article: 145055
On Jan 22, 5:18=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Jan 22, 9:44=A0am, Din=E7ay Ak=E7=F6ren <din...@gmail.com> wrote: > > > I have S3E starter kit. I accidentally connect a wrong power adaptor > > and two power regulators on the board was burnt. I cannot replace them > > because pads of the one of the regulators are under the package. So I > > decided to make or purchase a power supply card and connect it to > > starter kit. I have checked farnell.com and Linear Technology website > > but cannot find anything useful. Are there any power supply cards for > > FPGA's? Or any idea how I can re-operate my S3E board? > > Where would you connect a "power supply card" if there was one? PCB has test pins for all voltage levels. So I have an access to regulated voltage nets on PCB. I will use jumpers. > > Repairing a board with burnt components can be difficult, often > requiring an intense effort to pick out the burnt pieces of FR4 that > can be unintentionally conductive. =A0Even components with a pad > underneath can be removed with a narrow focus heat gun, for instance. > Even if you reflow nearby components, usually they're still in good > shape afterward. =A0Adding "dams" to block the airflow around more > sensitive parts nearby can help when reworking in this manner. Removing them is easy. Hard part is replacing them. > > Do you know if your failed regulators have failed open? =A0If you try to > wire in another regulator such as a linear.com uModule, you need to > make sure the parts still on board can play nice with the new supply. What do you mean by "failed open"? I think you mean passive components on the board should play nice. If they cause problems, I can remove them too since they will be useless if the regulator is removed.Article: 145056
Din?ay Ak??ren <dincay@gmail.com> wrote: (snip) > What do you mean by "failed open"? > I think you mean passive components on the board should play nice. If > they cause problems, I can remove them too since they will be useless > if the regulator is removed. The two common failure modes for electrical components, especially semiconductors, are to fail open (open circuit) or fail short (short circuit). The latter case is bad news for your FPGA. -- glenArticle: 145057
> Are there such thing as FPGA farm (for cryptographical purposes), Sure it is there. That farm is called NSA and employs farmers called MiBs (men in black). The farm is even remotely accessable via satelite called Echelon. That Echelon contains AI chip called Clipper. The legend goes that MiBs are using Clipper to feed the FPGA to read all our emails. -- StoneThrower www.dgmicrosys.comArticle: 145058
On Jan 21, 6:39=A0pm, "stephen.cra...@gmail.com" <stephen.cra...@gmail.com> wrote: > All, > > Could someone point me to a board or boards that combine a modern FPGA > with multiple ethernet PHYs? =A0The only multiple-ethernet board that I > have discovered is based on a V2P. > > Thank you in advance. > > Stephen Both the ML505/6/7 and the ML605 boards have a Marvel 88E1111 PHY/RJ45 and a SFP cage that can support 1000BASE-X or BASE-T Ethernet modules. This gives you two ethernet ports without an expansion card. Ed McGettigan -- Xilinx Inc.Article: 145059
In article <b48f5c25-73e0-4b57-8e71-d562a6b427cf@r19g2000yqb.googlegroups.com>, Dennis Yurichev <dennis.yurichev@gmail.com> wrote: >Hi. > >Are there such thing as FPGA farm (for cryptographical purposes), >containing a lot of expensive FPGAs, and accessed remotely for some >payment? There's www.copacobana.org which is 120 x Virtex4 SX35 in a 2U box; you can rent time on them by contacting cpaar@crypto.rub.de though I'm not sure how big the farm actually is. There's http://www.enterpoint.co.uk/merrick/supercomputers.html which seems to be trying to set up a business model based on renting time on their Merrick-1 boards, each of which contains a 10x10 array of XC3SD3400A. But I get the impression that this tends to be an area that small businesses see as a gap in the market, and then turn as they try to exploit the gap into single-purpose consultancies providing FPGA boards to the oil-services or government markets rather than trying to sell LUT*Hz as a commodity. About the only shrink-wrap FPGA-array application is breaking DES, and that's not terribly easy to monetize because you tend to have a degree of official suspicion of your customers. I get the impression that big grids of FPGAs are normally sold at enormous mark-up and in association with enormously expensive properitary software as ASIC emulators TomArticle: 145060
On Jan 23, 4:55=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Din?ay Ak??ren <din...@gmail.com> wrote: > > (snip) > > > What do you mean by "failed open"? > > I think you mean passive components on the board should play nice. If > > they cause problems, I can remove them too since they will be useless > > if the regulator is removed. > > The two common failure modes for electrical components, especially > semiconductors, are to fail open (open circuit) or fail short > (short circuit). =A0The latter case is bad news for your FPGA. > > -- glen It must be failed short, because regulators draw very high currents. I wonder why there is no protection circuits. A simple zener would prevent this accident.Article: 145061
Having been away from active FPGA development for a couple of years, I was surprised to discover the sorry state of Xilinx's documentation. Perhaps it has always been this way... Xilinx Application Notes -- I have found two application notes on the Chinese Xilinx site that do not appear on the main Xilinx web site (XAPPs 730 and 934). Has Xilinx pulled them? Webpack Supported Devices -- A simple Google search for "Xilinx webpack", performed to find the list of supported devices, returns out- of-date information that is not appropriately marked. Namely the second hit (http://www.xilinx.com/ise/logic_design_prod/ webpack_faq.htm) is an FAQ for the 8.2 version of the tools. Documentation Search Engine -- Though the main Xilinx site is up, I cannot get their documentation search engine (http://www.xilinx.com/ support/documentation/index.htm) to respond.Article: 145062
When a preformed post route simulation it gave me this warnings. I am having trouble in understanding them and why these warning come up. WARNING:Timing:3224 - The clock clkf_4 associated with OFFSET = IN 800 ns BEFORE COMP "clkf_4"; does not clock any registered input components. WARNING:Timing:3225 - Timing constraint OFFSET = IN 800 ns BEFORE COMP "clkf_4"; ignored during timing analysis Thank you for the help in advance --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145063
Hello All, In my project some RF input from outside circuitry has to be converted into digital form in ADC and then, after processing in FPGA, it will be converted back into analog RF signal which is to be displayed on an oscilloscope. Hence, I am interested - how to connect BNC connectors to ADC and DAC present on Xilinx Spartan-3E 1600E Microblaze Development Board? Thank you.Article: 145064
On Sat, 23 Jan 2010 17:26:13 -0600, "akshayvreddy" <akshayvreddy@n_o_s_p_a_m.gmail.com> wrote: >When a preformed post route simulation it gave me this warnings. I am >having trouble in understanding them and why these warning come up. > >WARNING:Timing:3224 - The clock clkf_4 associated with OFFSET = IN 800 ns >BEFORE COMP "clkf_4"; does not clock any > registered input components. >WARNING:Timing:3225 - Timing constraint OFFSET = IN 800 ns BEFORE COMP >"clkf_4"; ignored during timing analysis > >Thank you for the help in advance These outputs are from fpga tools (map and/or par) not from post-route simulation. Post route simulation means getting the doing a gate level simulation by annotating the gate level verilog output of PAR with the SDF generated at the same time. The first warning is telling you that the clock constraint you generated in the UCF file has a problem ie the name doesn't match any clocks or it's not connected to any nets. You probably misspelled it. The second one is telling you pretty much the same thing ie because the said clock doesn't clock any flops, the timing constraint is being ignored during PAR. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 145065
On Jan 24, 10:08=A0am, Alex <vict...@gmail.com> wrote: > Hello All, > > In my project some RF input from outside circuitry has to be converted > into digital form in ADC and then, after processing in FPGA, it will > be converted back into analog RF signal which is to be displayed on an > oscilloscope. > > Hence, I am interested - how to connect BNC connectors to ADC and DAC > present on Xilinx Spartan-3E 1600E Microblaze Development Board? > > Thank you. You can use Digilent BNC connector. Xilinx Spartan-3E 1600E Microblaze Development Board has appropriate 6 pin connectors. http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,401,541&Prod=3DP= MOD-CON2Article: 145066
On 24 =D1=8F=D0=BD=D0=B2, 11:58, Din=C3=A7ay Ak=C3=A7=C3=B6ren <din...@gmai= l.com> wrote: > On Jan 24, 10:08=C2=A0am, Alex <vict...@gmail.com> wrote: > > > Hello All, > > > In my project some RF input from outside circuitry has to be converted > > into digital form in ADC and then, after processing in FPGA, it will > > be converted back into analog RF signal which is to be displayed on an > > oscilloscope. > > > Hence, I am interested - how to connect BNC connectors to ADC and DAC > > present on Xilinx Spartan-3E 1600E Microblaze Development Board? > > > Thank you. > > You can use Digilent BNC connector. Xilinx Spartan-3E 1600E Microblaze > Development Board has appropriate 6 pin connectors.http://www.digilentinc= .com/Products/Detail.cfm?NavPath=3D2,401,541&Prod... Thank you for helpful reply!Article: 145067
Anyway I have noticed that the both - Digilent Pmod BNC connector and J5 header (which is used for DAC on Xilinx 1600E Microblaze development kit) are actually male pin connectors - so how to connect them?! I am puzzled.Article: 145068
Thanks very much for your reply! It tell me "all constraint are met", doesn't timing report analyze setup time and hold time at the same time? That is to say, if hold time equation doesn't meet, timing report will tell us offset constraint is "not met", right? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145069
On Jan 24, 5:28=A0am, Alex <vict...@gmail.com> wrote: > Anyway I have noticed that the both - Digilent Pmod BNC connector and > J5 header (which is used for DAC on Xilinx 1600E Microblaze > development kit) are actually male pin connectors - so how to connect > them?! I am puzzled. They come with a cable that has the female connectors at both ends. Regards, John McCaskill www.FasterTechnology.comArticle: 145070
On 24 =D1=8F=D0=BD=D0=B2, 16:18, John McCaskill <jhmccask...@gmail.com> wro= te: > On Jan 24, 5:28=C2=A0am, Alex <vict...@gmail.com> wrote: > > > Anyway I have noticed that the both - Digilent Pmod BNC connector and > > J5 header (which is used for DAC on Xilinx 1600E Microblaze > > development kit) are actually male pin connectors - so how to connect > > them?! I am puzzled. > > They come with a cable that has the female connectors at both ends. > > Regards, > > John McCaskillwww.FasterTechnology.com agh.. silly me (thanks anyway!)Article: 145071
>Thanks very much for your reply! > >It tell me "all constraint are met", doesn't timing report analyze setup >time and hold time at the same time? > >That is to say, if hold time equation doesn't meet, timing report will tell >us offset constraint is "not met", right? > >--------------------------------------- >Posted through http://www.FPGARelated.com > According to ISE definition, input offset is the time of data transition relative to NEXT clock edge. Your setting of 2ns resulted in ISE reporting -3.17ns i.e. ISE now contradicted its own definition and related it to previous clock edge. Whichever way you look at it, you got a transition at(6 - (-3.17)) = 2.83 ns with respect to NEXT clock edge, almost centre aligned. I don't expect volation of setup or hold as reported. Your own addition of 2 + 3.17ns makes no sense to me. you asked for 2ns and you got 2.83ns kadhiem --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145072
Hello, I need to implement a project as a part of my Masters curriculum using fpga devices that would generate delays, that is generate higher output frequencies than the system clock using propagation delays. I'm using ISE tool for the same. I'm new to this technology and would really appreciate if i could get some help on this. Thanks in advance. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145073
On Jan 25, 6:25=A0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote: > Hello, > > I need to implement a project as a part of my Masters curriculum using fp= ga > devices that would generate delays, that is generate higher output > frequencies than the system clock using propagation delays. I'm using ISE > tool for the same. I'm new to this technology and would really appreciate > if i could get some help on this. Thanks in advance. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com This is a somewhat confused question ? If you want to generate delays, you do not need to 'over-clock' - just choose a FPGA with inbuilt delay blocks, and they will have a step size, much smaller than any clock precision. ie the FPGA vendors have solved this problem already. -jgArticle: 145074
John_H <newsgroup@johnhandwork.com> writes: > On Jan 22, 5:21 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > Your definition of "better" fits pretty well but there's a little more > to it. When there's little consideration made for how the hardware > behaves with the Verilog tossed towards it, even very readable code > can be a problem. Memory inferences want a properly clocked and > enabled assignment for a single memory write and proper references for > the memory reads; registers on the read address and/or read values are > critical for proper implementation in a given target hardware. Flip- > flops like single edges and usually either asynchronous set/reset > controls or synchronous versions, not a mix (though a mix can be > supported by pushing the synchronous controls behind LUTs into the > logic). > > It's people who have never designed to the hardware level either with > old TTL chips or coded with a dog-eared, printed copy of an FPGA > architecture chapter that can produce something that looks okay from a > software viewpoint - even readable - but will cause problems in clean > synthesis. > Agreed - that's a description I can go with... you have to give the synth a fighting chance. "Poor code" can also include describing behaviour that really doesn't match what you have available. A bit like using floating-point code on a fixed-point processor and not understanding the FP library shenanegins that's going to have to support you. Heh - when I look back to my early days VHDLing I use to forget it was going to end up as hardware - and I used to solder 4000 series CMOS in my bedroom as a teenager :) So, yes, code like that > Clever synthesis tricks can be read, maintained, and debugged with > ease when done well. Clever tricks not done well can be "poor" code, > indeed. > Agreed! > >> Personally, I'm impressed that I can write a simple description of my >> logic and get a complicated near-optimal synthesis result out in a >> large number of cases - I wonder if I'm alone? :) > > A "simple description" in my book is one that's clean relative to the > hardware. When I see code that's trying to use dual-clocked > registers, case statements with (unintended) unpopulated states, > unintended combinatorial latches, abuses of asynchronous data > transfers or ugly workarounds to match pipelining, things get tough > for compilers. But they usually still produce results. > Yes, I had not interpreted your "poor code" to cover that sort of thing at all, but I can entirely see your point there. > Clean, readable code designed to favor using a heavily loaded signal > as close to the register as possible too often ends up with several > levels of LUTs in the critical path despite synthesis timing > constraints designed to keep those paths short. Synthesizers decide > to do things different than the implied coding intent because they're > smarter. Really? Too often I've had to manually piece-up a logic > cone so the critical paths do what they should have from the beginning. Maybe I've got luckier there then :) Apart from that it sounds like we don't differ as wildly as I implied, sorry! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
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Compare FPGA features and resources
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