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> =A0 if ((paddr(8 downto 2) =3D "1000000") and > =A0 =A0 =A0 ((psel and penable) =3D '1') and > =A0 =A0 =A0 ((pwrite and not(wrfifo_full)) =3D '1')) then Thanks a lot, that does the trick!Article: 149451
On Oct 24, 11:35=A0pm, rickman <gnu...@gmail.com> wrote: > On Oct 24, 1:37=A0pm, Santosh <santos...@gmail.com> wrote: > > > <> > > > > Do you know the terms SPI or EIA-232? =A0Or ain't you got to that poi= nt > > > in your class yet? > > > > Rick > > > I know SPI, but ain't done it. But I haven't heard of EIA-232 yet, is > > it like the RS-232 : P > > So what class is this for? By class you mean academic? I m just FPGA enthusiast .Article: 149452
On Oct 26, 9:22=A0am, Santosh <santos...@gmail.com> wrote: > On Oct 24, 11:35=A0pm, rickman <gnu...@gmail.com> wrote: > > > On Oct 24, 1:37=A0pm, Santosh <santos...@gmail.com> wrote: > > > > <> > > > > > Do you know the terms SPI or EIA-232? =A0Or ain't you got to that p= oint > > > > in your class yet? > > > > > Rick > > > > I know SPI, but ain't done it. But I haven't heard of EIA-232 yet, is > > > it like the RS-232 : P > > > So what class is this for? > > By class you mean academic? > I m just FPGA enthusiast . Good luck...Article: 149453
For this to be useful, you would have to also overload AND for combinations of sl and bool (on both sides too) to return bool. Then you would have a problem with "if abool and (asl and bsl) then" because the return type of the second "and" (inside the paretheses) is ambiguous (because the first "and" could accept either bool,bool or bool,sl operands). I wrote and use functions is1() and is0() to convert sl to boolean, while handling weak values and warning on other metavalues (while returning false). AndyArticle: 149454
I need to add an output pin to my design (virtex6), driven constantly high. I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set. If I look at the properties of the OBUF I see that there is nothing in the OSTANDARD parameter. It should be LVCMOS25. How do I change it? It doesn't seem to be editable in the properties dialog, and I don't see it in the component edit view. I've already got the change in my RTL for when I run the design next, I just want to edit my existing design for now. thanks, --steveArticle: 149455
Steve You need to switch the FPGA Editor into editing mode. Click on "edirmode" to toggle into editing mode and open the the I/O cell with "editblock" command. You should set the background set darker indicating the correct mode and you will be able to set the properties. John Adair Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development Board. On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote: > I need to add an output pin to my design (virtex6), driven constantly hig= h. > I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between > them. =A0I have one DRC warning, that the ISTANDARD of the OBUF isn't set= . =A0If > I look at the properties of the OBUF I see that there is nothing in the > OSTANDARD parameter. =A0It should be LVCMOS25. =A0How do I change it? =A0= It > doesn't seem to be editable in the properties dialog, and I don't see it = in > the component edit view. > > I've already got the change in my RTL for when I run the design next, I j= ust > want to edit my existing design for now. > > thanks, > --steveArticle: 149456
Do the p and n signals appear in your Entity declaration? Also watch out if the instantiations are not at your very top level. I hae seen issues in various versions of ISE if you are not at the top level. There shouldn't be a problem with LVPECL input on S3E providing you have locked the p and n parts to the correct pin locations. John Adair Enterpoint Ltd.- Home of Drigmorn3. The Spartan-6 Industrial Control Development Board. On 25 Oct, 15:11, Giorgos_P <giorgos.puik...@gmail.com> wrote: > Hello, > > I want to use 24 pairs of LVPECL_25 differential inputs in my design, > at a S3E500 FPGA device. During mapping, ISE gives the following > warnings and removes these inputs: > > =A0 =A0 =A0MapLib:701 - Signal pecl_input_p<23> connected to top level po= rt > pecl_input_p<23> has been removed. > =A0 =A0 =A0MapLib:701 - Signal pecl_input_n<23> connected to top level po= rt > pecl_input_n<23> has been removed. > =A0 =A0 =A0... > =A0 =A0 =A0MapLib:701 - Signal pecl_input_p<23> connected to top level po= rt > pecl_input_p<0> has been removed. > =A0 =A0 =A0MapLib:701 - Signal pecl_input_n<23> connected to top level po= rt > pecl_input_n<0> has been removed. > > The input buffers are instantiated in VHDL like this: > > =A0 =A0 =A0Gen1: for i in 23 downto 0 generate > =A0 =A0 =A0 =A0 IBUFDS_inst : IBUFDS =A0generic map (IOSTANDARD =3D> "LVP= ECL_25") > =A0 =A0 =A0 =A0 port map ( > =A0 =A0 =A0 =A0 =A0 =A0O =3D> cmp_in(i), =A0 =A0 =A0 =A0 =A0 =A0-- Diff_p= output (connect > directly to top-level port) > =A0 =A0 =A0 =A0 =A0 =A0I =3D> pecl_input_p(i), =A0 =A0 =A0-- Diff_n outpu= t (connect > directly to top-level port) > =A0 =A0 =A0 =A0 =A0 =A0IB =3D> pecl_input_n(i) =A0 =A0 =A0-- Buffer input > =A0 =A0 =A0 =A0 ); > =A0 =A0 =A0end generate Gen1 ; > > and in the constraint file it is specified that: > > =A0 =A0 =A0NET "pecl_input_p<0>" =A0LOC =3D "p57" | IOSTANDARD =3D LVPECL= _25 ; > =A0 =A0 =A0NET "pecl_input_n<0>" =A0LOC =3D "p58" | IOSTANDARD =3D LVPECL= _25 ; > =A0 =A0 =A0... > > The "cmp_in" output of the buffer is used and has load connected to > it, that is not removed from optimization steps. The problem seems to > be buffer-related, when I remove the buffer the inputs are not removed > by ISE. I also tried instantiating the buffer with following way, > getting the same results: > > =A0 =A0Gen1: for i in 23 downto 0 generate > =A0 =A0 =A0buffer_array : IBUFDS_LVPECL_25 port map > (I=3D>input_p(i),IB=3D>input_n(i) , O=3D>input_int(i)); > =A0 =A0end generate Gen1 ; > > Any ideas? > > Thank you in advance for your time, > GeorgeArticle: 149457
Hi John, I've already done that, I had to do it to add the ologic, tieoff, and obuf to the design, to create the routing, etc. When open the IO cell for editing in FPGA editor I see checkboxes for PULLTYPE, DIFF_TERM, and IBUF_LOW_PWR. I don't see anything related to IOSTANDARD in the IO cell view. If I right click the OBUF and look at properties, I see the IOSTANDARD on the configuration tab, but apparently not editable. Although I will say that FPGA editor in Linux goes have some GUI/mouse/focus issues, so maybe I should be able to type into the parameter fields of the properties dialog box, and linux/X is preventing it. thanks, --steve "John Adair" <g1@enterpoint.co.uk> wrote in message news:c201a335-d459-4eed-8113-a8e3c59ef99b@u10g2000yqk.googlegroups.com... Steve You need to switch the FPGA Editor into editing mode. Click on "edirmode" to toggle into editing mode and open the the I/O cell with "editblock" command. You should set the background set darker indicating the correct mode and you will be able to set the properties. John Adair Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development Board. On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote: > I need to add an output pin to my design (virtex6), driven constantly > high. > I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between > them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set. If > I look at the properties of the OBUF I see that there is nothing in the > OSTANDARD parameter. It should be LVCMOS25. How do I change it? It > doesn't seem to be editable in the properties dialog, and I don't see it > in > the component edit view. > > I've already got the change in my RTL for when I run the design next, I > just > want to edit my existing design for now. > > thanks, > --steveArticle: 149458
Apparently it was a message in the PlanAhead Tcl Console window and it looks as follows: INFO: [HD-Ucf 0] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file /MikhailArticle: 149459
On Oct 26, 10:58=A0am, "Steve Ravet" <steve.ra...@arm.com> wrote: > Hi John, I've already done that, I had to do it to add the ologic, tieoff= , > and obuf to the design, to create the routing, etc. =A0When open the IO c= ell > for editing in FPGA editor I see checkboxes for PULLTYPE, DIFF_TERM, and > IBUF_LOW_PWR. =A0I don't see anything related to IOSTANDARD in the IO cel= l > view. > > If I right click the OBUF and look at properties, I see the IOSTANDARD on > the configuration tab, but apparently not editable. =A0Although I will sa= y > that FPGA editor in Linux goes have some GUI/mouse/focus issues, so maybe= I > should be able to type into the parameter fields of the properties dialog > box, and linux/X is preventing it. > > thanks, > --steve > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:c201a335-d459-4eed-8113-a8e3c59ef99b@u10g2000yqk.googlegroups.com... > Steve > > You need to switch the FPGA Editor into editing mode. Click on > "edirmode" to toggle into editing mode and open the the I/O cell with > "editblock" command. You should set the background set darker > indicating the correct mode and you will be able to set the > properties. > > John Adair > Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development > Board. > > On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote: > > > > > I need to add an output pin to my design (virtex6), driven constantly > > high. > > I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes betwe= en > > them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set.= If > > I look at the properties of the OBUF I see that there is nothing in the > > OSTANDARD parameter. It should be LVCMOS25. How do I change it? It > > doesn't seem to be editable in the properties dialog, and I don't see i= t > > in > > the component edit view. > > > I've already got the change in my RTL for when I run the design next, I > > just > > want to edit my existing design for now. > > > thanks, > > --steve- Hide quoted text - > > - Show quoted text - After you open the OBUF cell using the "Edit Block" button. Click the "F=3D" icon to add the function/attribute editor and then type in your desired IO standard into OSTANDARD field. Ed McGettigan -- Xilinx Inc.Article: 149460
So, if anyone is curious, this command is supposed to be typed in the PlanAhead tcl console. It works quite nicely and generates a file with invalid constraints from all the constraints files it considers to be relevant. write_ucf -h produces some basic help information. /MikhailArticle: 149461
Hi all,
I am wondering if there is a way to simulate a Xilinx FIFO that is
generated with the FIFO Generator v6.1 as follows:
COMPONENT fifo_generator_v6_1
GENERIC (
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
...
)
PORT(
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
...
)
ATTRIBUTE box_type : STRING;
ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box";
ATTRIBUTE GENERATOR_DEFAULT : STRING;
ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a
map_qrvirtex4_to=virtex4 map_qvirtex4_to=virtex4";
Of course when I just simulate my design this is a blackbox. But to see
that I got everything right, I would need to be able to simulate this
core. Is there a simple way to do that?
In the meantime, I used async_fifo_v5_1.vhd to do some testing which has
a similar interface and worked fine. Anyway, I was wondering if there is
something similiar with the fifo_generator_v6_1.
Many thanks!
Article: 149462On Tue, 26 Oct 2010 08:23:12 -0700 (PDT), Andy <jonesandy@comcast.net> wrote: > >For this to be useful, you would have to also overload AND for >combinations of sl and bool (on both sides too) to return bool. It's still somewhat useful without those combinations - and avoids the ambiguity problems you note. >I wrote and use functions is1() and is0() to convert sl to boolean, >while handling weak values and warning on other metavalues (while >returning false). Another way of skinning the cat... - BrianArticle: 149463
On 27 Okt., 00:54, Richard <Rich...@yahoo.com> wrote: > Hi all, > > I am wondering if there is a way to simulate a Xilinx FIFO that is > generated with the FIFO Generator v6.1 as follows: > > COMPONENT fifo_generator_v6_1 > =A0 =A0GENERIC ( > =A0 =A0 =A0C_COMMON_CLOCK =A0 =A0 =A0 =A0 =A0 : integer =A0:=3D 0; > =A0 =A0 =A0C_COUNT_TYPE =A0 =A0 =A0 =A0 =A0 =A0 : integer =A0:=3D 0; > > =A0 =A0 ... > > =A0 ) > > =A0 =A0PORT( > =A0 =A0 =A0CLK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0std_lo= gic :=3D '0'; > =A0 =A0 =A0BACKUP =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0std_logi= c :=3D '0'; > > =A0 ... > > ) > > ATTRIBUTE box_type : STRING; > ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box"; > > ATTRIBUTE GENERATOR_DEFAULT : STRING; > ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS > "generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a > map_qrvirtex4_to=3Dvirtex4 map_qvirtex4_to=3Dvirtex4"; > > Of course when I just simulate my design this is a blackbox. But to see > that I got everything right, I would need to be able to simulate this > core. Is there a simple way to do that? > > In the meantime, I used async_fifo_v5_1.vhd to do some testing which has > a similar interface and worked fine. Anyway, I was wondering if there is > something similiar with the fifo_generator_v6_1. > > Many thanks! Hi Richard, corgen creates a set of files for each generated core. One is the ngc netlist. another one or two are instantiation templates (VHDL, verilog or both) and then there are also wrapper HDL files for simulation, that instantiate the xilinxcorelib modules for simulation with correctly set generics. Normally ISE Project Navigator should handle al this automatically when you change from implementatioon to simulation, Of course you have to add the .xco file, which should happen automatically when you create a new coregen module from ISE. If you happen to have problems finding the simulation wrapper, it may be that your prefered HDL language settings are wrong in the PNs Preferences. Have a nice simulation EilertArticle: 149464
On Oct 24, 2:50=A0pm, Santosh <santos...@gmail.com> wrote: > > What sort of external interfaces does your AtMega system have? =A0Since > > I assume that you don't need the data to update really fast for this > > sort > > of application, I would choose the interface with the fewest wires > > if there are more than one to choose from. =A0I think something like I2= C > > would be perfect for this application - just two signal wires and a > > protocol that's easy to use. =A0SPI or MicroWire are even easier > > from a protocol standpoint and have only a couple more wires. > > Any of these protocols can be run slow enough that you can > > oversample the signals with an internal clock in the FPGA. > > Then you don't need to be as concerned about signal integrity > > on your "clock" lines, which would be sampled, too. =A0Otherwise > > no matter how slow the interface (including 100 MHz I2C) > > if you try to use the clock line directly as a clock you can > > have headaches. > > > Regards, > > Gabor > > Hey, > =A0 =A0 =A0 I may be wrong but doesn't the AtMega output data on its cloc= k > speed, which is run by external X-tal and FPGA runs at 50 Mhz. And due > to non-matching clocks, ain't there any conflicts. And I didn't get > the term oversampling, : P > > San. You can generate a clock with atmega. It doesn't need to be fast nor have %50 duty cycle in your application since the speed you need is very low. As rickman said, look for SPI protocol. It is very easy to implement, both in fpga and atmega. There is a good tutorial in fpga4fun.com about SPI.Article: 149465
On Oct 27, 2:35=A0am, backhus <goous...@googlemail.com> wrote: > On 27 Okt., 00:54, Richard <Rich...@yahoo.com> wrote: > > > > > Hi all, > > > I am wondering if there is a way to simulate a Xilinx FIFO that is > > generated with the FIFO Generator v6.1 as follows: > > > COMPONENT fifo_generator_v6_1 > > =A0 =A0GENERIC ( > > =A0 =A0 =A0C_COMMON_CLOCK =A0 =A0 =A0 =A0 =A0 : integer =A0:=3D 0; > > =A0 =A0 =A0C_COUNT_TYPE =A0 =A0 =A0 =A0 =A0 =A0 : integer =A0:=3D 0; > > > =A0 =A0 ... > > > =A0 ) > > > =A0 =A0PORT( > > =A0 =A0 =A0CLK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0std_= logic :=3D '0'; > > =A0 =A0 =A0BACKUP =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0std_lo= gic :=3D '0'; > > > =A0 ... > > > ) > > > ATTRIBUTE box_type : STRING; > > ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box"; > > > ATTRIBUTE GENERATOR_DEFAULT : STRING; > > ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS > > "generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a > > map_qrvirtex4_to=3Dvirtex4 map_qvirtex4_to=3Dvirtex4"; > > > Of course when I just simulate my design this is a blackbox. But to see > > that I got everything right, I would need to be able to simulate this > > core. Is there a simple way to do that? > > > In the meantime, I used async_fifo_v5_1.vhd to do some testing which ha= s > > a similar interface and worked fine. Anyway, I was wondering if there i= s > > something similiar with the fifo_generator_v6_1. > > > Many thanks! > > Hi Richard, > corgen creates a set of files for each generated core. > One is the ngc netlist. > another one or two are instantiation templates (VHDL, verilog or both) > and then there are also wrapper HDL files for simulation, that > instantiate the xilinxcorelib modules for simulation with correctly > set generics. > > Normally ISE Project Navigator should handle al this automatically > when you change from implementatioon to simulation, > Of course you have to add the .xco file, which should happen > automatically when you create a new coregen module from ISE. > > If you happen to have problems finding the simulation wrapper, it may > be that your prefered HDL language settings are wrong in the PNs > Preferences. > > Have a nice simulation > =A0 Eilert Some other notes: If you use the "Project --> New Source..." method of adding a Coregen module to the design, you don't really get to see the Coregen project settings. Using the ISE GUI, the only way to get to those is either "Tools --> CoreGen" or by selecting the "manage cores" property for an .xco file already in your design. When generating FIFO cores, always select the structural models for simulation. The behavioral models are not only not cycle-accurate, but they are also broken for some configurations. For example in the FWFT dual-clock FIFO's I found that the behavioral model did not properly set the programmable almost full or empty flags. Regards, GaborArticle: 149466
On Oct 26, 6:53=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 26 Oct 2010 08:23:12 -0700 (PDT), Andy <jonesa...@comcast.net> wr= ote: > > >For this to be useful, you would have to also overload AND for > >combinations of sl and bool (on both sides too) to return bool. > > It's still somewhat useful without those combinations - and avoids the am= biguity > problems you note. Without those combinations, here are a few exampes of what would work and what would not: if asl and bsl then -- would work if (asl and bsl) and abool then -- would work if asl and abool then -- would NOT work The resulting confusion would be worse than that of the original situation. AndyArticle: 149467
"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:dd44fdde-353d-42f1-ba12-cbd1f5bb154d@30g2000yqm.googlegroups.com... After you open the OBUF cell using the "Edit Block" button. Click the "F=" icon to add the function/attribute editor and then type in your desired IO standard into OSTANDARD field. Ed McGettigan -- Xilinx Inc. Thanks Ed, just what I was looking for. --steveArticle: 149468
I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied high (LX760). What I've done so far: Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from O to the pad. Added a new OLOGIC X0Y318 and created a path from D1 to OQ. Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command but it failed. The specific commands were: select pin VTREF_TIEOFF.HARD1 select pin VTREF_ologic.D1 add The failure message is: ERROR:FPGAEditor:313 - Failed to route net "$NET_1". ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? thanks, --steveArticle: 149469
A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply enabling a pullup. /Mikhail "Steve Ravet" <steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >I thought this would be easy but I'm having a problem routing one of the >wires. I need to create a new output from my fpga, tied high (LX760). >What I've done so far: > > Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). > Edited the OBUF OUTMUX and OINMUX to create a path from O to the pad. > > Added a new OLOGIC X0Y318 and created a path from D1 to OQ. > > Selected OBUF.O and OLOGIC.OQ and created a routed net between them with > the add command. > > Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to > create a routed net between them with the add command but it failed. The > specific commands were: > > select pin VTREF_TIEOFF.HARD1 > select pin VTREF_ologic.D1 > add > > The failure message is: > > ERROR:FPGAEditor:313 - Failed to route net "$NET_1". > ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net > "$NET_1". > > I've done this kind of thing before, I'm not sure why it isn't working. > Any suggestions? > > thanks, > --steve > > > >Article: 149470
That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx support, they were able to duplicate the problem. He tried manually routing it as well and was unable to. For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. thanks, --steve "MM" <mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net... >A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >enabling a pullup. > > /Mikhail > > > > "Steve Ravet" <steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied >>high (LX760). What I've done so far: >> >> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from >> O to the pad. >> >> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >> >> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >> >> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command >> but it failed. The specific commands were: >> >> select pin VTREF_TIEOFF.HARD1 >> select pin VTREF_ologic.D1 >> add >> >> The failure message is: >> >> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >> >> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >> >> thanks, >> --steve >> >> >> >> > >Article: 149471
Hi, i am using spartan 3 xc3s4000 in my design and 2 national phys are integrated with it. The problem is that when i transmit from phy 1 to phy 2 ,i receive the packet and i can view it on wireshark. When i transmit it from phy2 to phy1 , wireshark display "receive ok" in statistics menu but it doesn't display any packet. and it doesn't report fcs error either. btw i am using xilinx 12.1 for synthesis. So,i switched to chipscope pro to debug my design,and i can see the transmitting nibbles , which are correct. But i don't know why isn't the pc showing any packet. Also, both are phys are just using 2 instances of same module. So, if the logic works at one end, technically it should work at the other end as well. can anyone give me any pointers as to what should i do now? how to debug it? Because i have been stuck for 2 days now and my vision has narrowed down a lot and i am out of ideas now. Kindly! Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149472
Steve : FPGA Editor is a great tool to debug and to find synthesis and or implementations tools bugs but never use it as design tool. If you need a new output go back to your HDL add a new output and then go to your UCF to setup the properties to the added output. Never break the implementation tool chain other than to do some simple test. Walter El 2010-10-27 13:53, Steve Ravet escribió: > That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx support, > they were able to duplicate the problem. He tried manually routing it as well and was unable to. > > For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. > > thanks, > --steve > > "MM"<mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net... >> A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >> enabling a pullup. >> >> /Mikhail >> >> >> >> "Steve Ravet"<steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>> I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied >>> high (LX760). What I've done so far: >>> >>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from >>> O to the pad. >>> >>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >>> >>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >>> >>> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command >>> but it failed. The specific commands were: >>> >>> select pin VTREF_TIEOFF.HARD1 >>> select pin VTREF_ologic.D1 >>> add >>> >>> The failure message is: >>> >>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >>> >>> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >>> >>> thanks, >>> --steve >>> --- news://freenews.netfront.net/ - complaints: news@netfront.net ---Article: 149473
On 10/27/2010 10:00 AM, salimbaba wrote: > Hi, > i am using spartan 3 xc3s4000 in my design and 2 national phys are > integrated with it. The problem is that when i transmit from phy 1 to phy 2 > ,i receive the packet and i can view it on wireshark. When i transmit it > from phy2 to phy1 , wireshark display "receive ok" in statistics menu but > it doesn't display any packet. and it doesn't report fcs error either. > > btw i am using xilinx 12.1 for synthesis. > > So,i switched to chipscope pro to debug my design,and i can see the > transmitting nibbles , which are correct. But i don't know why isn't the pc > showing any packet. > > Also, both are phys are just using 2 instances of same module. So, if the > logic works at one end, technically it should work at the other end as > well. > > can anyone give me any pointers as to what should i do now? how to debug > it? > Because i have been stuck for 2 days now and my vision has narrowed down a > lot and i am out of ideas now. Kindly! I'm not a super cool FPGA guy, but I can throw out a couple of suggestions: 1a: You have a plain old wiring error to one of the phys. Are transmit and receive wired separately? If so, check the transmit wiring on phy2. 1b: Check trace impedance and any necessary delay matching, of course. 1c: And power supply decoupling, no floating pins, etc. 2: What flavor of Ethernet? How challenged is the chip for speed? If it's right on the edge it may not like your choice of pins for one of the phy's. A long time ago when I was involved in a PCI project the only really successful PCI IP available for the FPGA we were using came laid out and was locked down to specific pins. Yes, PCI isn't Ethernet, and I don't know if it's an issue -- but it's something to check. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 149474
Walter, thanks for the advice. I have already made the change in the RTL but need to press on with this image, and find as many bugs as possible, before spending a week respinning the design. The word back from xilinx support is to not use the TIEOFF, but to instead connect the OBUF.O input to the net GLOBAL_LOGIC1. Did that and it works great. I'd still like to know what the problem was routing the TIEOFF though... --steve "Walter" <wsfpga@adinet.com.uy> wrote in message news:ia9m0j$a9e$1@adenine.netfront.net... > Steve : > > FPGA Editor is a great tool to debug and to find synthesis and or implementations tools bugs but never use it as design tool. > > If you need a new output go back to your HDL add a new output and then go to your UCF to setup the properties to the added output. > > Never break the implementation tool chain other than to do some simple test. > > Walter > > El 2010-10-27 13:53, Steve Ravet escribió: >> That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx >> support, >> they were able to duplicate the problem. He tried manually routing it as well and was unable to. >> >> For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. >> >> thanks, >> --steve >> >> "MM"<mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net... >>> A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >>> enabling a pullup. >>> >>> /Mikhail >>> >>> >>> >>> "Steve Ravet"<steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>>> I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, >>>> tied >>>> high (LX760). What I've done so far: >>>> >>>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path >>>> from >>>> O to the pad. >>>> >>>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >>>> >>>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >>>> >>>> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add >>>> command >>>> but it failed. The specific commands were: >>>> >>>> select pin VTREF_TIEOFF.HARD1 >>>> select pin VTREF_ologic.D1 >>>> add >>>> >>>> The failure message is: >>>> >>>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >>>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >>>> >>>> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >>>> >>>> thanks, >>>> --steve >>>> > > > --- news://freenews.netfront.net/ - complaints: news@netfront.net ---
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