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Hey all, I am trying to build a software defined radio for educational purposes. I need some help in understanding how to pick a A/D and D/A board that would interface correctly to my SP605 board. Are there any design considerations that I have to make (aside from sampling rate, number of effective bits, snr) to make sure that it interfaces correctly to my board? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149601
On Nov 10, 9:37=A0am, "pacman101" <acosta.janp@n_o_s_p_a_m.gmail.com> wrote: > Hey all, > > I am trying to build a software defined radio for educational purposes. > > I need some help in understanding how to pick a A/D and D/A board that > would interface correctly to my SP605 board. > > Are there any design considerations that I have to make (aside from > sampling rate, number of effective bits, snr) to make sure that it > interfaces correctly to my board? =A0 Clocking is very important in an SDR. Phase noise adds noise to your signal and sets a floor for the sensitivity of the receiver. Select a board that uses a clock source with low phase noise. The other parameters you mention, SNR, ENOB, Fs, are all factors that only matter once you have decided on what signals the radio will receive. ENOB will affect SNR, but is not equivalent to SNR. Noise can be averaged out in the filtering so that SNR can improve as the signal is processed. Fs depends on the band width of the received signal and how you plan to handle the analog to digital conversion. For example you can sample so the signals are below the Nyquist frequency or you can under-sample to perform a down conversion. RickArticle: 149602
On Nov 10, 6:37=A0am, "jypa09" <jyothirmai.aksha@n_o_s_p_a_m.gmail.com> wrote: > Hello > > I'm Implementing controller using xilinx ISE 8.2 =A0on FPGA board Virtex-= II > and anlyzing signals inside FPGA using chiscope analyzer. > > I instantiated cores using chipscope core inserter.My implementation was > successful. > > Though the bit file was generated =A0but when it comes to analyze it in > chipscope ,,,I could get this problem > > Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.. > When I implemented the design..I could get the only warning ..i,e > WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignore= d > during timing analysis. > > and the rest like generating programming file everything is going well > but when it come sto analyze it in chipscope after configuring it with bi= t > file...I could get the error like > > Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.. > > I have tried to manage it by reading so many forums...like nearly I chang= ed > all possible changes but still I could get this... > Its a big design so I assigned pin only =A0for clock signal with help of > manual.. > and the signal I selected for a clock to Chipscope is driven by > a BUFG or BUFGMUX component... > mhz_in signal is not being driven by the board. > clock source (on-board) was driven by the pin I assigned > to it in .ucf file...but still I could get this problem.. > > Can anybody help me ...Please.. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You have two different messages telling you that the clock is not connected to the ILA. #1: "slow or stopped clock" - This message indicates that the Chipscope application timed out waiting for the ILA to report ready - all it needs is a clock for it to respond. #2: "timing path ignored" - In this case it's trying to tell you that it didn't find a clock on the specified path. I realize that you think you have connected a clock. However, ISE is not convinced. RKArticle: 149603
Dear all,
In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:
-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:
process_out : process (in_a, in_b)
variable var : std_logic_vector (KA-KB-1 downto 0) := (others =>
'0');
begin
I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:
Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.
But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.
I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.
How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?
Thanks a lot in advance,
JaaC
Article: 149604Hi all, I need help. How to send single instruction/command thru JTAG interface with altera tools. I have to send FACTORY instruction and I know binry code for this instruction but I don't know how to send it. Or in other words I have to reenable jtag interface blocked because of anti tamper feature ( in my design ) Please help. BR AdamArticle: 149605
On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > Dear all, > > In my current project I have an entity for which I which arhitecture > to use on a VHDL file where I instantiate the entity, like following > configuration code: > > -- Embedded configuration > -- Select control architecture to use > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > Within the VHDL file where Ctrl2D is defined, I have different > configurations, namely rtl_tiny and rtl_small. Within each of those, > are processes which have variables whose length depend on some > constants (KA, KB), like: > > process_out : process (in_a, in_b) > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (other= s =3D> > '0'); > =A0 begin > > I should select which architecture to use in the configuration > (rtl_tiny or rtl_small) depending on a given a given set of values KA > and KB. For a set of values KA and KB that works fine with rtl_small > and having rtl_small selected in the configuration, XST, when parsing, > gives me warnign and error messages: > > Entity <Ctrl2D> compiled. > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > range: -33 downto 0 > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > concat operation is different than size of the target. > Entity <Ctrl2D> (Architecture <rtl_small>) compiled. > > But those lines (157 and 214) are within the architecture rtl_tiny, > not rtl_small. > > I was confident that by selecting the right architecture in the > configuration I was completely bypassing everything related to non- > desired architectures, but it seems like I was wrong. > > How can I direct XST to ignore the code of the non-interesting > architectures, and parse and synthesize only the one that I selected > in the configuration? > > Thanks a lot in advance, > > JaaC Unlike simulation tools, synthesis tools combine the analysis and elaboration phases into one. This is probably leading to your problem. Leaving something out in a configuration is not quite like conditionally compiling it. Everything gets analyzed (if it is in a file that is being analyzed), whether it is chosen at elaboration or not. Some simulators have options for compiling (analyzing) only certain types of units (packages, package bodies, entities, architectures, etc.) and ignoring others in the same file. I have not seen that in a synthesis tool. Other than fixing the problem with the mismatched size (if even possible), I would suggest moving the two architectures into separate files, and only including the appropriate file in the project. AndyArticle: 149606
On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote: > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > <jaime.arangu...@gmail.com> wrote: > > Dear all, > > > In my current project I have an entity for which I which arhitecture > > to use on a VHDL file where I instantiate the entity, like following > > configuration code: > > > -- Embedded configuration > > -- Select control architecture to use > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > Within the VHDL file where Ctrl2D is defined, I have different > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > are processes which have variables whose length depend on some > > constants (KA, KB), like: > > > process_out : process (in_a, in_b) > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (oth= ers =3D> > > '0'); > > =A0 begin > > > I should select which architecture to use in the configuration > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > and KB. For a set of values KA and KB that works fine with rtl_small > > and having rtl_small selected in the configuration, XST, when parsing, > > gives me warnign and error messages: > > > Entity <Ctrl2D> compiled. > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > range: -33 downto 0 > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > concat operation is different than size of the target. > > Entity <Ctrl2D> (Architecture <rtl_small>) compiled. > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > not rtl_small. > > > I was confident that by selecting the right architecture in the > > configuration I was completely bypassing everything related to non- > > desired architectures, but it seems like I was wrong. > > > How can I direct XST to ignore the code of the non-interesting > > architectures, and parse and synthesize only the one that I selected > > in the configuration? > > > Thanks a lot in advance, > > > JaaC > > Unlike simulation tools, synthesis tools combine the analysis and > elaboration phases into one. This is probably leading to your problem. > Leaving something out in a configuration is not quite like > conditionally compiling it. Everything gets analyzed (if it is in a > file that is being analyzed), whether it is chosen at elaboration or > not. Some simulators have options for compiling (analyzing) only > certain types of units (packages, package bodies, entities, > architectures, etc.) and ignoring others in the same file. I have not > seen that in a synthesis tool. > > Other than fixing the problem with the mismatched size (if even > possible), I would suggest moving the two architectures into separate > files, and only including the appropriate file in the project. > > Andy Hi Andy, Thanks for your reply, I found the solution however: adding pragmas: architecture struct of Stack2D is signal dat_2ext : buf2dwrd; signal rd_2ext : std_logic; signal dat_2slv : buf2dwrd; signal wr_2slv : std_logic; -- pragma synthesis on for all : Ctrl2D use entity work.Ctrl2D(rtl_small); -- pragma synthesis off begin The commented pragmas did the job. Regards.Article: 149607
On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote: > > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > <jaime.arangu...@gmail.com> wrote: > > > Dear all, > > > > In my current project I have an entity for which I which arhitecture > > > to use on a VHDL file where I instantiate the entity, like following > > > configuration code: > > > > -- Embedded configuration > > > -- Select control architecture to use > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > > are processes which have variables whose length depend on some > > > constants (KA, KB), like: > > > > process_out : process (in_a, in_b) > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (o= thers =3D> > > > '0'); > > > =A0 begin > > > > I should select which architecture to use in the configuration > > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > > and KB. For a set of values KA and KB that works fine with rtl_small > > > and having rtl_small selected in the configuration, XST, when parsing= , > > > gives me warnign and error messages: > > > > Entity <Ctrl2D> compiled. > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > range: -33 downto 0 > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > concat operation is different than size of the target. > > > Entity <Ctrl2D> (Architecture <rtl_small>) compiled. > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > not rtl_small. > > > > I was confident that by selecting the right architecture in the > > > configuration I was completely bypassing everything related to non- > > > desired architectures, but it seems like I was wrong. > > > > How can I direct XST to ignore the code of the non-interesting > > > architectures, and parse and synthesize only the one that I selected > > > in the configuration? > > > > Thanks a lot in advance, > > > > JaaC > > > Unlike simulation tools, synthesis tools combine the analysis and > > elaboration phases into one. This is probably leading to your problem. > > Leaving something out in a configuration is not quite like > > conditionally compiling it. Everything gets analyzed (if it is in a > > file that is being analyzed), whether it is chosen at elaboration or > > not. Some simulators have options for compiling (analyzing) only > > certain types of units (packages, package bodies, entities, > > architectures, etc.) and ignoring others in the same file. I have not > > seen that in a synthesis tool. > > > Other than fixing the problem with the mismatched size (if even > > possible), I would suggest moving the two architectures into separate > > files, and only including the appropriate file in the project. > > > Andy > > Hi Andy, > > Thanks for your reply, I found the solution however: adding pragmas: > > architecture struct of Stack2D is > > =A0 signal dat_2ext : buf2dwrd; > =A0 signal rd_2ext =A0: std_logic; > =A0 signal dat_2slv : buf2dwrd; > =A0 signal wr_2slv =A0: std_logic; > > =A0 -- pragma synthesis on > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > =A0 -- pragma synthesis off > > begin > > The commented pragmas did the job. > > Regards. Dear all, By the way, is there a way to make a conditional selection of architecture to use, something in the lines of: for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) else use entity work.Ctrl2D(architecture_b); ??? Or is there an alternative approach? Thanks lot in advance. JaaCArticle: 149608
On 11/10/2010 10:54 AM, Jaime Andrés Aranguren Cardona wrote:
>> architecture struct of Stack2D is
>>
>> signal dat_2ext : buf2dwrd;
>> signal rd_2ext : std_logic;
>> signal dat_2slv : buf2dwrd;
>> signal wr_2slv : std_logic;
>>
>> -- pragma synthesis on
>> for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
>> -- pragma synthesis off
>>
>> begin
>>
>> The commented pragmas did the job.
Maybe.
Were both architectures in the synthesis file list?
If so which one was first?
I use a similar trick to insert debug code into synthesis sources:
-- synthesis translate off
spy: process (strobe_s) is
begin -- process watch
if falling_edge(strobe_s) then
report("data = ", work.my_pkg.std2hexstr(my_ctr));
end if;
end process spy;
-- synthesis translate on
> By the way, is there a way to make a conditional selection of
> architecture to use, something in the lines of:
>
> for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a) else
> use entity work.Ctrl2D(architecture_b); ???
Not that I know of for synthesis, where I must declare
one top entity and file list. There is no notion
of vhdl libraries or configurations.
> Or is there an alternative approach?
I could generate one direct instance or another
based on a packaged constant value, but I find this confusing.
If the architecture differences are much less the spare fpga resources,
I might combine both modes and select using a mode
register or a jumper.
-- Mike Treseler
Article: 149609
On 11/8/2010 7:21 AM, LC wrote:
> # ** Error: (vsim-3170) Could not find
> 'D:\..myworkingpath...\simulation\modelsim\rtl_work.tb_port'.
Post the script or command line you used to run modelsim.
Did you create a modelsim work directory
named work under the source directory?
vlib work
vmap work work
Did you recompile the changes?
vcom mycode.vhd
vcom mytb.vhd
Did you try an elaboration test like this:
vsim -c mytb -do run
Good Luck.
-- Mike Treseler
Article: 149610Hi Everybody, can you please explain me how to design a vestigial side-band filter for analog TV applications using digital techniques? Thanks in advance, MaxArticle: 149611
"Safe mode" will add overhead logic into the current/next state decoding paths, which could negatively impact overall timing depending on encoding method, # states, and recovery scheme built in by synthesis tool (or user, if done manually). So one advantage of registering states and doing binary conversion is that user can re- locate any necessary detection/recovery logic from current/next state decoding and into the binary conversion path. Assuming that an illegal state event would be a rare and catastrophic (fsm would be dead), recovery would occur two cycles later, perhaps with the use of a sync "recovery" reset that configures all one-hot flops to desired recovery state. (that is unless any illegal state cannot be tolerated for more than one cycle, in which case the recovery logic must be built in to the original fsm code). In summary, registering state bits and doing binary conversion allows benefit of shrinking one-hot state to reasonable vector for status reporting, less intrusive chipscope monitoring, and decoupling recovery logic from actual fsm next state decode. JohnArticle: 149612
Hi, I'm developing a certain controller using Spartan3 FPGA. Since I have to communicate with another circuit that is using 5V signaling (similar to TTL, but HV level is above 3.5V) I was wondering if someone could recommend a good solution in a form of a "level shifter" circuit (I searched the internet and found a few ICs that could do the job. However, I could use a good recomendation though :) ). Tnx in advance.. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149613
On Thu, 11 Nov 2010 08:45:56 -0000, "Michael Kellett" <nospam@nospam.com> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:iq5jd6t8vpelg53n1e1e5hdkqs7f0deu90@4ax.com... >> >> http://www.theregister.co.uk/2010/11/09/marvell_armada_xp_arm_chip/ >> >> All that beautiful room for vias. >> >> John >> > >Very nice (the pattern - I don't have any use for the chip !). I wish more >semi compnaies would think a bit more about the cost of using BGAs before >connecting evey possible ball. > >Michael Kellett > The Altera chip we're going to use [1] is a solid rectangle of balls. Yuk. John [1] We're migrating away from Xilinx. Great silicon, insanely broken software.Article: 149614
On Nov 10, 12:54=A0pm, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona > > > > > > <jaime.arangu...@gmail.com> wrote: > > On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote: > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > <jaime.arangu...@gmail.com> wrote: > > > > Dear all, > > > > > In my current project I have an entity for which I which arhitectur= e > > > > to use on a VHDL file where I instantiate the entity, like followin= g > > > > configuration code: > > > > > -- Embedded configuration > > > > -- Select control architecture to use > > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > > configurations, namely rtl_tiny and rtl_small. Within each of those= , > > > > are processes which have variables whose length depend on some > > > > constants (KA, KB), like: > > > > > process_out : process (in_a, in_b) > > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D = (others =3D> > > > > '0'); > > > > =A0 begin > > > > > I should select which architecture to use in the configuration > > > > (rtl_tiny or rtl_small) depending on a given a given set of values = KA > > > > and KB. For a set of values KA and KB that works fine with rtl_smal= l > > > > and having rtl_small selected in the configuration, XST, when parsi= ng, > > > > gives me warnign and error messages: > > > > > Entity <Ctrl2D> compiled. > > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > > range: -33 downto 0 > > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > > concat operation is different than size of the target. > > > > Entity <Ctrl2D> (Architecture <rtl_small>) compiled. > > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > > not rtl_small. > > > > > I was confident that by selecting the right architecture in the > > > > configuration I was completely bypassing everything related to non- > > > > desired architectures, but it seems like I was wrong. > > > > > How can I direct XST to ignore the code of the non-interesting > > > > architectures, and parse and synthesize only the one that I selecte= d > > > > in the configuration? > > > > > Thanks a lot in advance, > > > > > JaaC > > > > Unlike simulation tools, synthesis tools combine the analysis and > > > elaboration phases into one. This is probably leading to your problem= . > > > Leaving something out in a configuration is not quite like > > > conditionally compiling it. Everything gets analyzed (if it is in a > > > file that is being analyzed), whether it is chosen at elaboration or > > > not. Some simulators have options for compiling (analyzing) only > > > certain types of units (packages, package bodies, entities, > > > architectures, etc.) and ignoring others in the same file. I have not > > > seen that in a synthesis tool. > > > > Other than fixing the problem with the mismatched size (if even > > > possible), I would suggest moving the two architectures into separate > > > files, and only including the appropriate file in the project. > > > > Andy > > > Hi Andy, > > > Thanks for your reply, I found the solution however: adding pragmas: > > > architecture struct of Stack2D is > > > =A0 signal dat_2ext : buf2dwrd; > > =A0 signal rd_2ext =A0: std_logic; > > =A0 signal dat_2slv : buf2dwrd; > > =A0 signal wr_2slv =A0: std_logic; > > > =A0 -- pragma synthesis on > > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > =A0 -- pragma synthesis off > > > begin > > > The commented pragmas did the job. > > > Regards. > > Dear all, > > By the way, is there a way to make a conditional selection of > architecture to use, something in the lines of: > > for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) =A0els= e > use entity work.Ctrl2D(architecture_b); =A0 ??? > > Or is there an alternative approach? > > Thanks lot in advance. > > JaaC- Hide quoted text - > > - Show quoted text - The only way to do that is with an if-generate on the instantiation, not the configuration. In fact, since the '93 standard, you can directly instantiate an entity and its architecture: if a =3D 0 generate u1: entity work.entity_name(architecture_name)... end generate; if a /=3D 0 generate u1: entity work.entity_name(alternative_architecture_name) ... end generate; You don't even need to mess with a configuration! AndyArticle: 149615
On Nov 10, 9:25=A0am, G=F3rski Adam <gorskiamalpa@wpkropkapl> wrote: > Hi all, > > I need help. > How to send single instruction/command thru JTAG interface with altera > tools. I have to send FACTORY instruction and I know binry code for this > instruction but I don't know how to send it. > > Or in other words I have to reenable jtag interface blocked because of > anti tamper feature ( in my design ) > Please help. > > BR > > Adam It ain't gonna happen with Altera-provided tools. I would look for a general purpose JTAG tool, one with application- level support. Something like this: <http://www.amontec.com/> RKArticle: 149616
W dniu 11/11/2010 18:10, d_s_klein pisze: > On Nov 10, 9:25 am, Górski Adam<gorskiamalpa@wpkropkapl> wrote: >> Hi all, >> >> I need help. >> How to send single instruction/command thru JTAG interface with altera >> tools. I have to send FACTORY instruction and I know binry code for this >> instruction but I don't know how to send it. >> >> Or in other words I have to reenable jtag interface blocked because of >> anti tamper feature ( in my design ) >> Please help. >> >> BR >> >> Adam > > It ain't gonna happen with Altera-provided tools. > > I would look for a general purpose JTAG tool, one with application- > level support. Something like this:<http://www.amontec.com/> > > RK I solved my problem with Altera support. Funny is that when flash contains valid image - jtag is almost disabled in ep3cls family. Only few commands are working. AdamArticle: 149617
In article <i81od65b1at3tbplttg152gs89noermf7b@4ax.com>, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes: >The Altera chip we're going to use [1] is a solid rectangle of balls. >Yuk. >[1] We're migrating away from Xilinx. Great silicon, insanely broken >software. Were you doing anything "strange" with the Xilinx software? For example, running on Linux rather than Windows, or trying to use make rather than pushing buttons on their GUI? Is Altera's software any better? (Are you jumping out of the frying pan into the fire?) -- These are my opinions, not necessarily my employer's. I hate spam.Article: 149618
On Nov 11, 9:45=A0am, "noob13" <matija.draganovic@n_o_s_p_a_m.hotmail.com> wrote: > Hi, > > I'm developing a certain controller using Spartan3 FPGA. Since I have to > communicate with another circuit that is using 5V signaling (similar to > TTL, but HV level is above 3.5V) I was wondering if someone could recomme= nd > a good solution in a form of a "level shifter" circuit (I searched the > internet and found a few ICs that could do the job. However, I could use = a > good recomendation though :) ). > > Tnx in advance.. A tried and true method is a "quick switch" circuit. This is a pass transistor type gate that automatically limits the max voltage conveyed from either side to the other to within approximately a volt of Vdd if I remember correctly. They even have a version of the chip that integrates a diode in the Vdd path so it can be powered by 5 volts and the max level is just within the power rail of 3.3 volt logic. If you need a logic high to be 3.5 volts, you would need to add a pull up resistor to that side of the interface. A part number I have used in my designs is SN74CBTD3384CPW, a 10 element part with a separate enable for each 5 elements. I like the PW (TSSOP) packages as they are very small, but not BGA. They seem easy to get. There should be parts without the diode if you want to try to run without the pullups and can provide just the right Vdd voltage so the FPGA doesn't fry and your 3.5 volt thresholds are met... I'm not sure what the I/O max is on the spartans, so this may not be possible on paper. Otherwise there are parts that actually drive the correct signal voltage and have two power pins, one for each side. I don't have a part number handy, but I should have an advertisement for these parts available when I get back to the office. I'm not certain they are bidirectional, but I believe they are and it doesn't make much sense for them not to be... except if they drive both directions, they would need direction and enable controls. RickArticle: 149619
On Nov 11, 4:18=A0pm, rickman <gnu...@gmail.com> wrote: > On Nov 11, 9:45=A0am, "noob13" > > <matija.draganovic@n_o_s_p_a_m.hotmail.com> wrote: > > Hi, > > > I'm developing a certain controller using Spartan3 FPGA. Since I have t= o > > communicate with another circuit that is using 5V signaling (similar to > > TTL, but HV level is above 3.5V) I was wondering if someone could recom= mend > > a good solution in a form of a "level shifter" circuit (I searched the > > internet and found a few ICs that could do the job. However, I could us= e a > > good recomendation though :) ). > > > Tnx in advance.. > > A tried and true method is a "quick switch" circuit. =A0This is a pass > transistor type gate that automatically limits the max voltage > conveyed from either side to the other to within approximately a volt > of Vdd if I remember correctly. =A0They even have a version of the chip > that integrates a diode in the Vdd path so it can be powered by 5 > volts and the max level is just within the power rail of 3.3 volt > logic. =A0If you need a logic high to be 3.5 volts, you would need to > add a pull up resistor to that side of the interface. > > A part number I have used in my designs is SN74CBTD3384CPW, a 10 > element part with a separate enable for each 5 elements. =A0I like the > PW (TSSOP) packages as they are very small, but not BGA. =A0They seem > easy to get. =A0There should be parts without the diode if you want to > try to run without the pullups and can provide just the right Vdd > voltage so the FPGA doesn't fry and your 3.5 volt thresholds are > met... =A0I'm not sure what the I/O max is on the spartans, so this may > not be possible on paper. > > Otherwise there are parts that actually drive the correct signal > voltage and have two power pins, one for each side. =A0I don't have a > part number handy, but I should have an advertisement for these parts > available when I get back to the office. =A0I'm not certain they are > bidirectional, but I believe they are and it doesn't make much sense > for them not to be... except if they drive both directions, they would > need direction and enable controls. > > Rick Some things to watch out for when using the quick switch: TI has some 3.3V parts that have charge pumps built in. These parts will conduct above 3.3V so they're not good for voltage level translation. The FET's in the switch have a soft shut-off as the channel voltage nears Vcc. When translating between 5V TTL and 3.3V CMOS this is O.K. but going from 3.3V CMOS to 5V CMOS it means that the final bit of rise time to reach the high voltage threshold is controlled by your pullup resistors. You need to decide whether this is OK or if you need to use an active drive part to meet your timing needs. Otherwise the quick switch will tend to have better timing than the active drive approach as well as not needing direction enables. In fact if you are not doing a hot plug design you can tie the enable active. Regards, GaborArticle: 149620
On Nov 11, 7:58=A0am, jc <jcappe...@optimal-design.com> wrote: > In summary, registering state bits and doing binary conversion allows Maybe I'm missing something here, and just need a clearer explanation... What is the output of the binary conversion when the input is an illegal state value? (Example: Three bit one hot that ends up at "111") How do you specify the binary conversion function when the input is an enumerate type? The t_my_type'pos(xyz) won't do it. In the previous example it would return a number from 0 to 2. Even allowing that the implementation of the function would compute two bits and therefore be capable of returning 0 to 3, it does not cover the case that I mentioned "111". The fact that there are three bits implementing the one hot encoding means that there are 8 possibilities, most of which can not be specified in any fashion. KevinArticle: 149621
On Thu, 11 Nov 2010 07:03:29 -0800, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Thu, 11 Nov 2010 08:45:56 -0000, "Michael Kellett" ><nospam@nospam.com> wrote: > >> >>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >>news:iq5jd6t8vpelg53n1e1e5hdkqs7f0deu90@4ax.com... >>> >>> http://www.theregister.co.uk/2010/11/09/marvell_armada_xp_arm_chip/ >>> >>> All that beautiful room for vias. >>> >>> John >>> >> >>Very nice (the pattern - I don't have any use for the chip !). I wish more >>semi compnaies would think a bit more about the cost of using BGAs before >>connecting evey possible ball. >> >>Michael Kellett >> > >The Altera chip we're going to use [1] is a solid rectangle of balls. >Yuk. They're not all that bad. Most of the center are power/ground so easier to wire. The problem is that without the doughnut hole there is no convenient place to put decoupling and terminators (on the back). The coarse pitched parts (1mm and .8mm) aren't hard to fan out, either. We're stuck with them because of our SMT process anyway. My problem is that no one makes low-pincount parts with a coarse pitch. They insist on .5 or even .4mm! >John > >[1] We're migrating away from Xilinx. Great silicon, insanely broken >software. I didn't have a lot of problems with Xilinx, other than it constantly wanted to rebuild my libraries in a new location. I like Altera's software much better, though.Article: 149622
On Nov 11, 4:45=A0pm, "noob13" <matija.draganovic@n_o_s_p_a_m.hotmail.com> wrote: > Hi, > > I'm developing a certain controller using Spartan3 FPGA. Since I have to > communicate with another circuit that is using 5V signaling (similar to > TTL, but HV level is above 3.5V) I was wondering if someone could recomme= nd > a good solution in a form of a "level shifter" circuit (I searched the > internet and found a few ICs that could do the job. However, I could use = a > good recomendation though :) ). > > Tnx in advance.. I use SN74LVC8T245, which can be used to interface any voltage bus (either 3.3V <-> 5V or 3.3V <-> 1.8V possible afaik). There are two separate power pins for buffer sides: VccA and VccB. However, You will need to switch direction pin for full IO. Also I had other part ADM3304 afaik, can't remember exactly, but I am sure it was ADMxxxx.Article: 149623
Hi all,
I am working on a design, where there are n modules. Each module is
connected with next module in sequential fashion.
like, data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
-> decoder2 -> decoder1
The output of decoder1 should be same as data generator. I have tested each
module in FPGA and also the following configurations
data generator -> encoder 1 -> encoder 2-> decoder2 ->decoder1
----------Works fine
data generator -> encoder 2 -> modulator -> demodulator -> decoder2
----------Works fine
But, when I integrate the all the modules, the design is not working as
expected. I need to reset the board for 5,6 times for the output to come
correctly. The timing analyzer reported no error.
BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
hardware boards 1. Spartan-6 sp601 kit 2. Spartan-3 based baord
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 149624
On Nov 12, 7:54 am, "sridar" <srisridar@n_o_s_p_a_m.gmail.com> wrote:
> Hi all,
>
> I am working on a design, where there are n modules. Each module is
> connected with next module in sequential fashion.
>
> like, data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
> -> decoder2 -> decoder1
>
> The output of decoder1 should be same as data generator. I have tested each
> module in FPGA and also the following configurations
>
> data generator -> encoder 1 -> encoder 2-> decoder2 ->decoder1
> ----------Works fine
>
> data generator -> encoder 2 -> modulator -> demodulator -> decoder2
> ----------Works fine
>
> But, when I integrate the all the modules, the design is not working as
> expected. I need to reset the board for 5,6 times for the output to come
> correctly. The timing analyzer reported no error.
>
> BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
> hardware boards 1. Spartan-6 sp601 kit 2. Spartan-3 based baord
First question, did you simulate the design? I find it much easier to
view internals in simulation than on a chip.
Second, try monitoring each of the points in the upstream side with a
separate downstream chain...
gen->encode1-+->encode2-+->mod->demod->decode2->decode1->monitor
| |
| +->decode2->decode1->monitor
|
+->decode1->monitor
This may at least point to what is failing.
It is possible you have some issues with your clocking. Perhaps you
can describe how you perform that. I would expect the encode and
modulate processes create multiple samples for each sample input. Are
you using a high speed clock and enabling each section as
appropriate?
Rick
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