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>However, the new problem is that I cannot feed in a data message, followed >by the known good CRC, and get 0! This used to work before I added the >above logic. You aren't supposed to get 0. You get some magic constant. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 145351
"Mike Treseler" <mtreseler@gmail.com> wrote in message news:7t3rmlFhriU1@mid.individual.net... > Eric Chomko wrote: >> Has anyone created a copy machine of an old system using an FPGA? I >> was wondering if it would be possible to take an entire SWTPC 6800 and >> compile the schematics and have it run on an FPGA board.? Wouldn't >> even have to be the latest Xylinx product, I suspect. > > No fpga, but same idea: > http://www.grc.com/pdp-8/pdp-8.htm Looking at the PDP8 picture brings back bad memories of me helping to clear out the computer lab at my old University which was full of PDP8 and PDP11, it all went into the skip......;-( Hans www.ht-lab.com > > > -- Mike TreselerArticle: 145352
On 5 Feb, 18:19, Eric Chomko <pne.cho...@comcast.net> wrote: > Has anyone created a copy machine of an old system using an FPGA? I > was wondering if it would be possible to take an entire SWTPC 6800 and > compile the schematics and have it run on an FPGA board.? Wouldn't > even have to be the latest Xylinx product, I suspect. Like Alex Freed this person made an Apple 2 on FPGA http://www.cs.columbia.edu/~sedwards/apple2fpga/ An amazing project however one looks at it. The power consumption figures are interesting. JamesArticle: 145353
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote: (snip regarding signals crossing gaps between supply planes) >> I believe, for the most part, it doesn't do that. The capacitance >> of even a single plane is high enough at the higher frequencies >> that for the most part the return current doesn't have to take >> the long way around. > What do you base this on? And what do you mean by the "capacitance of > even a single plane"??? What is the sound of one hand clapping? > Isn't capacitance measured between two conductors? Consider two concentric spheres as a capacitor, and you can easily calculate the capacitance. Now take the limit as the radius of the outer sphere goes to infinity. The capacitance does not go to zero. Interestingly, in the CGS (gaussian) unit system the unit of capacitance is the centimeter. I believe that without any factors (2, pi, etc.) it is the capacitance of a sphere to infinity. Otherwise, in terms of ground bounce the question is how much does the voltage change on the pin as a function of AC current. Q=CV I=dQ/dt=C dV/dt > Above you said, > "The two ground planes should be well bonded with vias, so there isn't > a problem when a signal goes through a via and passes from being > referred to one ground plane to the other." How is bonding the planes > with vias useful if the current has to go all the way to a via and > back in order to follow the trace??? You have to be careful using DC thinking for AC problems. How does (AC) current get through a capacitor? As someone else said, for a fair frequency range the signal capacitively couples to another plane that does cross the boundary, then back to the first plane. The conductor is to remind the electromagnetic wave which direction it is supposed to go. (snip, someone wrote) >> >> I reject the notion of placing a power plane and a ground plane close >> >> together in the middle of the board to get the benefit of the >> >> inter-plane capacitance for bypassing reasons. Don't get me wrong, it >> >> won't hurt, but IMO the amount of capacitance gained is tiny, and even >> >> though it is a very high Q capacitor, getting the power to the die is >> >> stymied by the inductance of the vias and BGA balls that are part of the >> >> PDS. >> I think I agree with this. The way to actually see this is to >> calculate the radial propagation of the signal into the plane >> from the via. The impedance (both inductance and capacitance) >> will change with radial distance and frequency. > That is why Lee Ritchey's course was such an eye opener for me. There > are any number of ways you can "calculate" and theorize what happens > in power planes. But unless you verify it by testing in hardware, you > are just whistling in the dark. I completely agree. Well, actually computers are probably about fast enough to do the whole calculation for at least one board trace using the actual geometry. With linearity you can compute each one and add them together. > Lee has done that. One test he made > that really impressed me was to show that a decoupling cap does not > need to be close to a pin to work well. If the power and ground plane > are closely spaced, the impedance is very low. If you understand > transmission lines, you will know that the current into (or out of) a > driver into the transmission line is constant until the signal reaches > the other end and depending on what load it finds, either continues > until the reflection returns to the driver (as in a series terminated > line with high impedance load) or keeps flowing as when it reaches the > decoupling cap. Well, it has the impedance of the transmission line itself. That depends on the inductance and capacitance of the conductors making up the transmission line. You can consider a linear transmission line as a sequence of series inductors and parallel capacitors of constant value per unit length. Consider the impedance of a finite length open ended transmission line as a function of frequency. For some frequencies the impedance will be very low, for others it will be very high. This property is used for impedance matching and filtering in RF circuits. > So if the cap is further away, the transmission line > supplies the current for decoupling until the wave front reaches the > cap. The point is that the planes have to be closely coupled for > there to be a high enough capacitance (also known as a low enough > impedance) to provide the current until the pulse reaches the cap. Now, consider the case of a signal going into or out of a supply plane. Now instead of the constant inductance and capacitance per unit length you have concentric rings. The inductance decreases and the capacitance increase with radial distance. In transmission line terms, it is a line with the impedance decreasing with R. Impedance decreases pretty fast, too. A quick web search finds a paper that looks interesting on just this problem. http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf The paper has much more detail than even I know, and includes comparisons of calculations and actual boards. > Lee actually built a board and has measurement data to show this. So > analyze away if you want, but how can you dispute measurements? I don't dispute them. Since you don't want to build boards by trial and error, and any measurements will only apply to the board that they were measured on, you also want to have some understanding of the measurements. That seems to be what the paper above does. >> >> If your power plane is in the middle of the board, the signal path >> >> of these vias are longer. You don't care about the supply stiffness on >> >> your plane, it's on the die that counts. >> Well, I think it is both. For a single supply via, yes. But if you >> add them all up, then the ground plane has to supply (or sink) the >> total of all the vias, and some of that comes from the interplane >> capacitance. The via inductance will be most important at the >> highest frequencies. The ground plane at slightly lower, but >> still significant frequencies. At some point there is a tradeoff >> between the two, and you have to figure out what that means in terms >> of plane positioning. > What exactly is any of this based on? Well, you can calculate and/or measure the impedance of the via. It should be pretty close to proportional to length, and decrease with radius. Again, I am not at all against measurment. So you have the series impedance of the via, and that parallel impedance of the ground plane. The via, being mostly inductance, will increase with frequency. (snip, someone else wrote) >> > I'm a bit unclear on what you are saying. You are suggesting that the >> > impedance of the vias is enough that you should put the planes as >> > close as possible to the component surface, but then you recommend >> > putting the decoupling caps on the back side much further away from >> > the component with longer vias. >> To see this, you have to think of it in frequency (Fourier) space. >> The switching currents have frequency components over a wide >> range, with a peak somewhere near 1/(transition time) but >> significant over a range of lower frequencies. The highest ones >> are supplied by the internal capacitors. The next lower ones >> by the ground plane itself, near the via. Lower still by the >> ground plane farther away, where interplane capacitance is important. >> Then there are the onboard bypass capacitors, the power supply >> bypass capacitors, the power supply filter capacitors, etc. (snip) > The high frequency components are the only ones I care about for > ground bounce. The problem is caused by series inductance. The lower > the frequency, the lower the impact. But still, ground bounce is > largely a package problem which you can do nothing about on the board > other than make it worse. I think I don't disagree. Still, you can't ignore the high frequencies that aren't quite as high as the peak. That is why you need ever bigger bypass capacitors farther out, in addition to the small and close ones. > Another really amazing thing I got from Lee's course is that there are > any number of engineers who get it wrong. I'm not talking about > typical board designers, I am talking about engineers designing chips > and packages. He has any number of examples where he was called in to > fix a problem and he told them to throw it out and start over doing it > right. In one case, they wanted to use some chip that Lee found had > too much lead impedance and would ground bounce all the noise margin > out of the logic levels. So they had to scrap the idea of using the > chip. There are always tradeoffs. ICs in packages with too much lead inductance to ever be used don't sound so useful, though. Maybe they work in some conditions, though. Does anyone remember the 74S124? -- glenArticle: 145354
On Feb 6, 1:19=A0am, Eric Chomko <pne.cho...@comcast.net> wrote: > Has anyone created a copy machine of an old system using an FPGA? It's the answer to a different question of course, but a National Semiconducter subsidiary once tried to emulate an IBM 3033 at full speed using Fairchild 100k parts. ... the reason for failure is interesting ... James Dow AllenArticle: 145355
Eric Chomko <pne.chomko@comcast.net> wrote: >Has anyone created a copy machine of an old system using an FPGA? I >was wondering if it would be possible to take an entire SWTPC 6800 and >compile the schematics and have it run on an FPGA board.? Wouldn't >even have to be the latest Xylinx product, I suspect. Many people already did that. http://www.hat.hi-ho.ne.jp/tujikawa/esepld/esemsx2/ -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 145356
On 2/6/2010 8:13 AM, rickman wrote: > To be honest, I don't know > why they would put caps inside the package > > Rick The caps are on the package because the inductance of the connecting vias and package balls means that, no matter how good the bypassing is on the PCB, the die on the package will have bypassing problems with it's supply. This is why I believe the high Q bypassing from a power plane and a ground plane doesn't help, and the layers can be arranged differently to achieve better results by optimising other areas. Syms.Article: 145357
>
>>However, the new problem is that I cannot feed in a data message,
followed
>>by the known good CRC, and get 0! This used to work before I added the
>>above logic.
>
>You aren't supposed to get 0. You get some magic constant.
>
You are absolutely right. You also need to feed in the 'what used to be the
matching CRC' in reverse BYTE order (on top of reversing the bits).
Now I'd like to understand why it doesn't give 0. This is what is mentioned
in the 'painless guide to CRC error detection algorithm', line 575.
http://www.ross.net/crc/download/crc_v3.txt
''At the other end, the receiver can do one of two things:
a. Separate the message and checksum. Calculate the checksum for
the message (after appending W zeros) and compare the two
checksums.
b. Checksum the whole lot (without appending zeros) and see if it
comes out as zero!''
I thought this was a nice approach since the receiver in the FPGA only
needs to ever compare the CRC output with 0, instead of capturing the known
CRC (32 flops) and doing a full 32 bit compare. Although now with a magic
constant it's pretty much the same.
Diego
---------------------------------------
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Article: 145358On Fri, 05 Feb 2010 16:33:24 -0800, Mike Treseler wrote: >http://www.grc.com/pdp-8/pdp-8.htm Wow, thanks for that wonderful link, and thanks to the wonderful but certifiably deranged people who put together all those resources. I cut my teeth on PDP8s in various forms; FOCAL was my first programming language; a PDP8/a (yes, I know, not a real classic but a nice Classic nonetheless) was the first computer whose guts I got to mess with. That one was mostly 74-TTL, with quite a lot of small bipolar PROMs for its state machines. (For the youngsters: "small" here means 256 byte or thereabouts. Byte, not kilobyte, please note.) And I totally agree with all the hagiography on that site celebrating the 8's superb economy of design, in the days when that desperately mattered. It spilt over into programming too. OS/8 required you to write device drivers in only 256 12-bit words; I managed to do one of those myself. DEC got the entire FORTRAN runtime library into only 4K of (self-modifying!!) code. Sorry, I'm rambling. I'm still on a nostalgia high after a visit to the fabulous collection of old computer equipment in the Deutsches Museum in Munich a couple of weeks ago. Strangely, though, they had no DEC equipment at all! -- Jonathan BromleyArticle: 145359
rickman <gnuarm@gmail.com> wrote: ... > Maybe I am missing something, but your original post said "XC200A and > LVCMOS25/12mA/Fast slew drive TICKOF is 5.24 ns and timing can be met > (16.666 -5.24 = 11.42 > 11)" The 5.24 ns value matches the data sheet > value for LVCMOS25 on both the clock input and the driver output with > 12 mA fast slew and not using the DCM. Using the 8 mA drive you list > above adds 0.38 ns giving 5.62 ns. Subtracting from 16.666 gives > 11.046 which is close to the result above, but not a perfect match. I > don't know if there is still a mismatch between your constraints and > the data I am using or maybe the timing file is more up to date than > the data sheet. Either way, I guess I am asking if the description of > your I/Os is as above, both the clock input and the driver output at > LVCMOS25 and the output at 8 mA FAST and the DCM is not being used. Often the timing in the datasheet is not as actual as the timing used in ISE. Soslight differences may arise. > If you want to get a little more margin in your timing, which is where > I think you are taking this, you can utilize the DCM and improve your > margin by almost 2 ns! As the USB clock may stop, additional considerations need to be done when using DCM. I will consider, but my original question was about constraining minimum hold times. I still don't see a way to do so. Bye > Rick -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 145360
On 2/6/10 3:29 AM, James Dow Allen wrote: > On Feb 6, 1:19 am, Eric Chomko<pne.cho...@comcast.net> wrote: >> Has anyone created a copy machine of an old system using an FPGA? > > It's the answer to a different question of course, > but a National Semiconducter subsidiary once tried to > emulate an IBM 3033 at full speed using Fairchild 100k parts. > ... the reason for failure is interesting ... > > James Dow Allen I would be interested in what the reason for failure was. I assume it wasn't the obvious chip-chip delays using commodity ICs.Article: 145361
On Feb 6, 8:01=A0am, Symon <symon_bre...@hotmail.com> wrote: > On 2/6/2010 8:13 AM, rickman wrote: > > > =A0 To be honest, I don't know > > why they would put caps inside the package > > > Rick > > The caps are on the package because the inductance of the connecting > vias and package balls means that, no matter how good the bypassing is > on the PCB, the die on the package will have bypassing problems with > it's supply. This is why I believe the high Q bypassing from a power > plane and a ground plane doesn't help, and the layers can be arranged > differently to achieve better results by optimising other areas. I understand what you are saying, but it does not address the problem that the capacitors you say are used inside the chip package no longer decouple effectively above 100 MHz or so. Certainly the noise transients from signal switching in an FPGA extend well above 100 MHz. If the inductance of the package leads do not allow effective connection to power/ground planes, the part will always have noise problems. One of the ways around the inductance of the package leads is to use more than one lead. I believe many packages have as many as 40 or more ground leads. So the effective impedance is then 40 times lower than what is calculated for one pin. Has that been considered in your analysis? Just as decoupling caps can be effective well above their self resonant frequency where they are effectively inductors (because the power delivery system impedance is still very low with many in parallel), the inductors we call power pins can still be an effective power conduit as long as the total impedance is low enough. I keep asking you if you have done any real analysis or measurements of what you are stating? I am no guru, but I was *very* impressed by what Lee Ritchey said just because he has full support for just about everything he stated in his course (except maybe that the food was good at the Chinese restaurant). RickArticle: 145362
On Feb 6, 6:00=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > In comp.arch.fpga rickman <gnu...@gmail.com> wrote: > (snip regarding signals crossing gaps between supply planes) > > >> I believe, for the most part, it doesn't do that. =A0The capacitance > >> of even a single plane is high enough at the higher frequencies > >> that for the most part the return current doesn't have to take > >> the long way around. > > What do you base this on? =A0And what do you mean by the "capacitance o= f > > even a single plane"??? =A0What is the sound of one hand clapping? > > Isn't capacitance measured between two conductors? =A0 > > Consider two concentric spheres as a capacitor, and you can easily > calculate the capacitance. =A0Now take the limit as the radius of > the outer sphere goes to infinity. =A0The capacitance does not go > to zero. =A0 Interestingly, in the CGS (gaussian) unit system the > unit of capacitance is the centimeter. =A0I believe that without > any factors (2, pi, etc.) it is the capacitance of a sphere to > infinity. =A0 > > Otherwise, in terms of ground bounce the question is how much > does the voltage change on the pin as a function of AC current. > > Q=3DCV =A0I=3DdQ/dt=3DC dV/dt =A0 Ok, you have equations. I still don't believe that a ground plain all by itself is an effective capacitor for power delivery decoupling. Showing equations is way down the list of evidence, far below applying equations, which is below running simulations which is far below taking measurements. There are many, many ways to misapply equations, so I am much more convinced by a real world measurement. > > Above you said, > > "The two ground planes should be well bonded with vias, so there isn't > > a problem when a signal goes through a via and passes from being > > referred to one ground plane to the other." =A0How is bonding the plane= s > > with vias useful if the current has to go all the way to a via and > > back in order to follow the trace??? > > You have to be careful using DC thinking for AC problems. =A0 > How does (AC) current get through a capacitor? =A0As someone else > said, for a fair frequency range the signal capacitively couples > to another plane that does cross the boundary, then back to > the first plane. =A0The conductor is to remind the electromagnetic > wave which direction it is supposed to go. =A0 My bad here. I am the one saying that the planes will capacitively couple and allow the return current to cross slots in one plane by jumping to the other. I got your post mixed up with Symon's post where he recommends multiple ground planes stitched together with vias rather than capacitively coupled power/ground planes. > (snip, someone wrote) > > >> >> I reject the notion of placing a power plane and a ground plane clo= se > >> >> together in the middle of the board to get the benefit of the > >> >> inter-plane capacitance for bypassing reasons. Don't get me wrong, = it > >> >> won't hurt, but IMO the amount of capacitance gained is tiny, and e= ven > >> >> though it is a very high Q capacitor, getting the power to the die = is > >> >> stymied by the inductance of the vias and BGA balls that are part o= f the > >> >> PDS. > >> I think I agree with this. =A0The way to actually see this is to > >> calculate the radial propagation of the signal into the plane > >> from the via. =A0The impedance (both inductance and capacitance) > >> will change with radial distance and frequency. > > That is why Lee Ritchey's course was such an eye opener for me. =A0Ther= e > > are any number of ways you can "calculate" and theorize what happens > > in power planes. =A0But unless you verify it by testing in hardware, yo= u > > are just whistling in the dark. =A0 > > I completely agree. =A0Well, actually computers are probably about > fast enough to do the whole calculation for at least one board trace > using the actual geometry. =A0With linearity you can compute each one > and add them together. =A0 > > > Lee has done that. =A0One test he made > > that really impressed me was to show that a decoupling cap does not > > need to be close to a pin to work well. =A0If the power and ground plan= e > > are closely spaced, the impedance is very low. =A0If you understand > > transmission lines, you will know that the current into (or out of) a > > driver into the transmission line is constant until the signal reaches > > the other end and depending on what load it finds, either continues > > until the reflection returns to the driver (as in a series terminated > > line with high impedance load) or keeps flowing as when it reaches the > > decoupling cap. =A0 > > Well, it has the impedance of the transmission line itself. > That depends on the inductance and capacitance of the conductors > making up the transmission line. =A0You can consider a linear > transmission line as a sequence of series inductors and parallel > capacitors of constant value per unit length. =A0Consider the > impedance of a finite length open ended transmission line as > a function of frequency. =A0For some frequencies the impedance will > be very low, for others it will be very high. =A0This property > is used for impedance matching and filtering in RF circuits. I am aware of what a transmission line is. That is my point. The transmission line of closely spaced planes is a very low impedance which supplies current for the full time it takes the impulse to reach the cap. So the spacing of the caps is not at all critical contrary to what many will tell you. > > So if the cap is further away, the transmission line > > supplies the current for decoupling until the wave front reaches the > > cap. =A0The point is that the planes have to be closely coupled for > > there to be a high enough capacitance (also known as a low enough > > impedance) to provide the current until the pulse reaches the cap. > > Now, consider the case of a signal going into or out of a supply > plane. =A0Now instead of the constant inductance and capacitance > per unit length you have concentric rings. =A0The inductance decreases > and the capacitance increase with radial distance. =A0In transmission > line terms, it is a line with the impedance decreasing with R. > Impedance decreases pretty fast, too. =A0 > > A quick web search finds a paper that looks interesting on just > this problem. =A0 > > http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf > > The paper has much more detail than even I know, and includes > comparisons of calculations and actual boards. What paper? I get a 404 error, page not found. Still, I don't see the problem you seem to be describing. So the impedance drops with increasing distance, low impedance in the power supply is a good thing, no? Why would it dropping be a bad thing? Lee actually has impedance vs. frequency measurements of power/ground planes and it is pretty interesting. They don't do much below 100 MHz or so, but beyond that the impedance is an up/down trace (all adequately low) until it finally starts to climb above several GHz. IIRC he explained the the sawtooth as having to do with the board dimensions. I guess it has something to do with standing waves, but it was some four years ago and I don't recall for sure. I do remember that he showed some interesting interactions between the plane capacitance and the inductance of the small sized and valued decoupling caps. They have a resonance around 100-200 MHz I think, which drives the impedance way up at that value. His solution was to add other value caps which effectively move that resonance and also damp it out to where it is acceptable. I think he showed a board where he used a total of three different values of ceramic caps, but only a small number of each, to get a very quiet board with a very constant power delivery system impedance. When I took the course, I understood how to figure it all out, but I have not had a design with difficult power decoupling needs, so I have forgotten some of it. Good thing I still have the book... somewhere... > > Lee actually built a board and has measurement data to show this. =A0So > > analyze away if you want, but how can you dispute measurements? > > I don't dispute them. =A0Since you don't want to build boards by > trial and error, and any measurements will only apply to the board > that they were measured on, you also want to have some understanding > of the measurements. =A0That seems to be what the paper above does. So the physics of each board is different??? The board Lee constructed was a test board. I don't recall what he used for a source of the transient, but he had spots for capacitors at a minimum of three distances connected to the power/ground planes with optimally short runs to the vias. He populated the caps one at a time and measured the effectiveness finding that it dropped off barely at all at an inch, IIRC and only moderately at a couple or three inches. The point is that it is not really needed to put the cap right on top of the power pin. A good power/ground plane pair is much more important. > >> >> If your power plane is in the middle of the board, the signal path > >> >> of these vias are longer. You don't care about the supply stiffness= on > >> >> your plane, it's on the die that counts. > >> Well, I think it is both. =A0For a single supply via, yes. =A0But if y= ou > >> add them all up, then the ground plane has to supply (or sink) the > >> total of all the vias, and some of that comes from the interplane > >> capacitance. =A0The via inductance will be most important at the > >> highest frequencies. =A0The ground plane at slightly lower, but > >> still significant frequencies. =A0At some point there is a tradeoff > >> between the two, and you have to figure out what that means in terms > >> of plane positioning. > > What exactly is any of this based on? > > Well, you can calculate and/or measure the impedance of the via. > It should be pretty close to proportional to length, and decrease > with radius. =A0Again, I am not at all against measurment. > > So you have the series impedance of the via, and that parallel > impedance of the ground plane. =A0The via, being mostly inductance, > will increase with frequency. =A0 My point is that this is all theory. Unless you take some measurements to verify what you are saying, you can't say it is an accurate description of a real board and chip. Also consider that one via is not a power supply. Vias are used in parallel giving an effectively low impedance. RickArticle: 145363
James Dow Allen <jdallen2000@yahoo.com> writes: > It's the answer to a different question of course, > but a National Semiconducter subsidiary once tried to > emulate an IBM 3033 at full speed using Fairchild 100k parts. > ... the reason for failure is interesting ... in the early 80s los gatos did custom hardware for chip logic simulation (LSM ... "losgatos state machine" ... then "logic simulation machine" for publication) ... dozen plus rack boxes ... ran 50,000 times faster faster than logic simulation in software on 3033 this mentions putting 4.5 meter dish in back parking lot of los gatos lab (and on east coast in field near yorkton research). http://www.garlic.com/~lynn/2010c.html#57 watches a dish also went into austin ... and austin credits the link and access to hardware logic simulation (relatively high bandwidth for the period ... for transmission of chip design files) with helping bring in the RIOS chipset 12 months early ... recent reference to six chipset RIOS (aka POWER, used in rs/6000). http://www.garlic.com/~lynn/2010c.html#20 Processes' memory later hardware logic simulators assumed synchronous clock ... but the LSM had clock support ... allowed simulation of digital chips with analog circuits ... (the then) new generation of thin-film disk heads and chips with non-globally synchronous circuit. however, the 3033 in bldg. 15 (disk product test lab) was used for air bearing software simulation (shape for floating disk heads) ... misc. past posts getting to play disk engineer in bldgs. 14&15 http://www.garlic.com/~lynn/subtopic.html#disk misc. past posts mentioning LSM http://www.garlic.com/~lynn/2002d.html#3 Chip Emulators - was How does a chip get designed? http://www.garlic.com/~lynn/2002g.html#55 Multics hardware (was Re: "Soul of a New Machine" Computer?) http://www.garlic.com/~lynn/2002g.html#77 Pipelining in the past http://www.garlic.com/~lynn/2002g.html#82 Future architecture http://www.garlic.com/~lynn/2002j.html#26 LSM, YSE, & EVE http://www.garlic.com/~lynn/2003.html#31 asynchronous CPUs http://www.garlic.com/~lynn/2003k.html#3 Ping: Anne & Lynn Wheeler http://www.garlic.com/~lynn/2003k.html#14 Ping: Anne & Lynn Wheeler http://www.garlic.com/~lynn/2003o.html#38 When nerds were nerds http://www.garlic.com/~lynn/2004j.html#16 US fiscal policy (Was: Bob Bemer, Computer Pioneer,Father of ASCII,Invento http://www.garlic.com/~lynn/2004o.html#25 CKD Disks? http://www.garlic.com/~lynn/2004o.html#65 360 longevity, was RISCs too close to hardware? http://www.garlic.com/~lynn/2005c.html#6 [Lit.] Buffer overruns http://www.garlic.com/~lynn/2005d.html#33 Thou shalt have no other gods before the ANSI C standard http://www.garlic.com/~lynn/2006q.html#42 Was FORTRAN buggy? http://www.garlic.com/~lynn/2006r.html#11 Was FORTRAN buggy? http://www.garlic.com/~lynn/2007f.html#73 Is computer history taught now? http://www.garlic.com/~lynn/2007h.html#61 Fast and Safe C Strings: User friendly C macros to Declare and use C Strings http://www.garlic.com/~lynn/2007l.html#53 Drums: Memory or Peripheral? http://www.garlic.com/~lynn/2007m.html#58 Is Parallel Programming Just Too Hard? http://www.garlic.com/~lynn/2007m.html#61 Is Parallel Programming Just Too Hard? http://www.garlic.com/~lynn/2007n.html#22 What if phone company had developed Internet? http://www.garlic.com/~lynn/2007o.html#67 1401 simulator for OS/360 http://www.garlic.com/~lynn/2007o.html#68 CA to IBM TCP Conversion http://www.garlic.com/~lynn/2008c.html#68 Toyota Beats GM in Global Production http://www.garlic.com/~lynn/2009k.html#75 Disksize history question http://www.garlic.com/~lynn/2009m.html#63 What happened to computer architecture (and comp.arch?) -- 42yrs virtualization experience (since Jan68), online at home since Mar1970Article: 145364
On Feb 5, 1:51=A0pm, "(see below)" <yaldni...@blueyonder.co.uk> wrote: > On 05/02/2010 18:19, in article > badc12c3-cb2b-4ce9-9543-237d60fc2...@o8g2000vbm.googlegroups.com, "Eric > > Chomko" <pne.cho...@comcast.net> wrote: > > Has anyone created a copy machine of an old system using an FPGA? I > > was wondering if it would be possible to take an entire SWTPC 6800 and > > compile the schematics and have it run on an FPGA board.? Wouldn't > > even have to be the latest Xylinx product, I suspect. > > I think such a project would valuable, and perhaps even more valuable if = it > aimed to recreate a machine of the "heroic" era -- a 7094, an Atlas, or a > KDF9, say. Perhaps even a Stretch. > > KDF9 had about 20K transistors, a few K logic transformers, and a compara= ble > number of diodes; less than 50K devices in total. I imagine this would be > easily accommodated on a modern FPGA. The big question would be whether t= o > go for functional equivalence, or whether to try to replicate the origina= l > internal structures. > > Documentation would be the main challenge for the latter. > > -- > Bill Findlay > <surname><forename> chez blueyonder.co.uk Heck, on an iCore 2 you might be able to run that under Spice! You could probably even provide a graphical display of any front panel lights! RickArticle: 145365
On Feb 6, 9:34=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > my original question was about constraining > minimum hold times. I still don't see a way to do so. Sorry, I thought that was explained. I can't say categorically, but I don't think there is a way. Bsides, your approach of using a global clock input and a register in the IOB means the delay is not controllable by layout. It is what the data sheet says it is and they typically don't spec minimum delays. Inside the chip there is no reason to use minimum delays if you are using the clock routing resources. Any other clock routing is at your own risk and I have never seen tools to support that. RickArticle: 145366
I try to keep a reasonably updated list of such projects at http://www.merlintec.com:8080/hardware/31 -- JecelArticle: 145367
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote: (snip) > My bad here. I am the one saying that the planes will capacitively > couple and allow the return current to cross slots in one plane by > jumping to the other. I got your post mixed up with Symon's post > where he recommends multiple ground planes stitched together with vias > rather than capacitively coupled power/ground planes. Well, you want it to stay low impedance all the way down to DC. >> (snip, I wrote) >> I completely agree. ?Well, actually computers are probably about >> fast enough to do the whole calculation for at least one board trace >> using the actual geometry. ?With linearity you can compute each one >> and add them together. ? >> > Lee has done that. ?One test he made >> > that really impressed me was to show that a decoupling cap does not >> > need to be close to a pin to work well. ?If the power and ground plane >> > are closely spaced, the impedance is very low. ?If you understand >> > transmission lines, you will know that the current into (or out of) a >> > driver into the transmission line is constant until the signal reaches >> > the other end and depending on what load it finds, either continues >> > until the reflection returns to the driver (as in a series terminated >> > line with high impedance load) or keeps flowing as when it reaches the >> > decoupling cap. ? >> Well, it has the impedance of the transmission line itself. >> That depends on the inductance and capacitance of the conductors >> making up the transmission line. ?You can consider a linear >> transmission line as a sequence of series inductors and parallel >> capacitors of constant value per unit length. ?Consider the >> impedance of a finite length open ended transmission line as >> a function of frequency. ?For some frequencies the impedance will >> be very low, for others it will be very high. ?This property >> is used for impedance matching and filtering in RF circuits. > I am aware of what a transmission line is. That is my point. The > transmission line of closely spaced planes is a very low impedance > which supplies current for the full time it takes the impulse to reach > the cap. So the spacing of the caps is not at all critical contrary > to what many will tell you. I believe, though, that radial transmission lines aren't discussed much in classes. I hadn't thought of them much until I was replying to your post. A google search for them brought up the paper that I tried to reference. I did the search on a different computer and copied the link by hand. I will try again. (Interesting all the ads that come for towing companies and transmission repair.) (snip) >> Now, consider the case of a signal going into or out of a supply >> plane. ?Now instead of the constant inductance and capacitance >> per unit length you have concentric rings. ?The inductance decreases >> and the capacitance increase with radial distance. ?In transmission >> line terms, it is a line with the impedance decreasing with R. >> Impedance decreases pretty fast, too. ? >> A quick web search finds a paper that looks interesting on just >> this problem. ? >> http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf >> The paper has much more detail than even I know, and includes >> comparisons of calculations and actual boards. > What paper? I get a 404 error, page not found. Still, I don't see > the problem you seem to be describing. So the impedance drops with > increasing distance, low impedance in the power supply is a good > thing, no? Why would it dropping be a bad thing? OK, try again. http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf he seems to even include the reflections of other vias, which seems more than is needed to me, but... It looks like the other papers on on slot antenna design, so he is considering PC board design in slot antenna terms. > Lee actually has impedance vs. frequency measurements of power/ground > planes and it is pretty interesting. They don't do much below 100 MHz > or so, but beyond that the impedance is an up/down trace (all > adequately low) until it finally starts to climb above several GHz. > IIRC he explained the the sawtooth as having to do with the board > dimensions. I guess it has something to do with standing waves, but > it was some four years ago and I don't recall for sure. With some bad luck you might get a resonance (standing wave) where the impedance didn't stay low. > I do remember that he showed some interesting interactions between the > plane capacitance and the inductance of the small sized and valued > decoupling caps. They have a resonance around 100-200 MHz I think, > which drives the impedance way up at that value. His solution was to > add other value caps which effectively move that resonance and also > damp it out to where it is acceptable. I think he showed a board > where he used a total of three different values of ceramic caps, but > only a small number of each, to get a very quiet board with a very > constant power delivery system impedance. When I took the course, I > understood how to figure it all out, but I have not had a design with > difficult power decoupling needs, so I have forgotten some of it. > Good thing I still have the book... somewhere... In the old days, it might be that the tolerance kept the resonances from being too close. The uniformity is so good now that they will all have resonance too close together. (snip) > So the physics of each board is different??? The board Lee > constructed was a test board. I don't recall what he used for a > source of the transient, but he had spots for capacitors at a minimum > of three distances connected to the power/ground planes with optimally > short runs to the vias. He populated the caps one at a time and > measured the effectiveness finding that it dropped off barely at all > at an inch, IIRC and only moderately at a couple or three inches. The > point is that it is not really needed to put the cap right on top of > the power pin. A good power/ground plane pair is much more > important. (snip) > My point is that this is all theory. Unless you take some > measurements to verify what you are saying, you can't say it is an > accurate description of a real board and chip. Also consider that one > via is not a power supply. Vias are used in parallel giving an > effectively low impedance. Hopefully the link is right now. He does both theory and measurement. -- glenArticle: 145368
Symon <symon_brewer@hotmail.com> wrote: > On 2/6/2010 8:13 AM, rickman wrote: >> To be honest, I don't know >> why they would put caps inside the package > The caps are on the package because the inductance of the connecting > vias and package balls means that, no matter how good the bypassing is > on the PCB, the die on the package will have bypassing problems with > it's supply. This is why I believe the high Q bypassing from a power > plane and a ground plane doesn't help, and the layers can be arranged > differently to achieve better results by optimising other areas. I think what he means is that the resonance will still be too low even inside the package. -- glenArticle: 145369
In comp.arch.fpga Anne & Lynn Wheeler <lynn@garlic.com> wrote: (snip) > in the early 80s los gatos did custom hardware for chip logic simulation > (LSM ... "losgatos state machine" ... then "logic simulation machine" > for publication) ... dozen plus rack boxes ... ran 50,000 times faster > faster than logic simulation in software on 3033 I remember when I first started working with computers I had a book from our library about ECAP, IBM's Electronic Circuit Analysis Program. I never saw or used the actual program, and haven't heard about it since. I wonder where it went... -- glenArticle: 145370
On 2/6/2010 7:04 PM, glen herrmannsfeldt wrote: > Symon<symon_brewer@hotmail.com> wrote: >> On 2/6/2010 8:13 AM, rickman wrote: >>> To be honest, I don't know >>> why they would put caps inside the package > >> The caps are on the package because the inductance of the connecting >> vias and package balls means that, no matter how good the bypassing is >> on the PCB, the die on the package will have bypassing problems with >> it's supply. This is why I believe the high Q bypassing from a power >> plane and a ground plane doesn't help, and the layers can be arranged >> differently to achieve better results by optimising other areas. > > I think what he means is that the resonance will still be too > low even inside the package. > > -- glen What resonance?Article: 145371
On 2/6/2010 5:38 PM, rickman wrote: > > I keep asking you if you have done any real analysis or measurements > of what you are stating? > Well, this was the first time you asked IIRC, but thank you for doing so. The answer is "For sure". I've used Hyperlynx and Spice on my boards. I guess you have also, or else you would not be able to post your opinions without worrying you might giving someone a bum steer. > I am no guru, Really? > > but I was *very* impressed by > what Lee Ritchey said just because he has full support for just about > everything he stated in his course (except maybe that the food was > good at the Chinese restaurant). > > Rick You seem to be _very_ impressed. Almost as impressed as Steve Wier. http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4Article: 145372
On 2/6/2010 6:15 PM, rickman wrote: >> will increase with frequency. > > My point is that this is all theory. Unless you take some > measurements to verify what you are saying, you can't say it is an > accurate description of a real board and chip. Also consider that one > via is not a power supply. Vias are used in parallel giving an > effectively low impedance. > > Rick Rick, Do you measure every resistor you put on a board. Ohm's law is a theory, after all. Syms xxArticle: 145373
Symon <symon_brewer@hotmail.com> wrote: (snip on bypass capacitors) > What resonance? The limit to the useful frequency range of a capacitor is when it reaches resonance with the series (lead, package, etc.) inductance. Graph impedance vs. frequency, when the reactive component crosses zero that it resonance. -- glenArticle: 145374
On 2/7/2010 1:03 AM, glen herrmannsfeldt wrote: > Symon<symon_brewer@hotmail.com> wrote: > > (snip on bypass capacitors) > >> What resonance? > > The limit to the useful frequency range of a capacitor is > when it reaches resonance with the series (lead, package, etc.) > inductance. Graph impedance vs. frequency, when the reactive > component crosses zero that it resonance. > > -- glen Hi Glen, Are you sure? Even beyond that frequency the cap is still doing something, isn't it? Syms.
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