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On Mar 3, 12:22=A0am, Symon <symon_bre...@hotmail.com> wrote: > This lot seems to be revealing a bit more about their stuff. > > http://www.mercurynews.com/breaking-news/ci_14493616 > A better overview is here http://www.eetasia.com/ART_8800599499_499495_NT_b33fb563_2.HTM Some of what Tabula say, reads more like a patent dance, than any technical explanation. So, it is locally 1.6GHz, with time-sliced threads. It might save Logic and routing, but it will have no config-memory saving, and it ADDS the complexity of rapid config multiplex. (not to mention power impacts) We already have Achronix climing 1.5GHz PLDs since 2008, and XMOS have 400-500Mhz hard-time-sliced cores shipping also. Tabula have some rather quaint terminology, as they try to spin what they do, but designers have always tried to do more serially & pipeline, to save resource, if they can. It seems their SW will do the 'thread slice & dice' for you, and that may be the critical point. If that works, and you can debug it, it could be useful. If it fails, it will fail in a tangle. -jgArticle: 146001
I've finally decided to buy a better simulator (I've been making do with Modelsim XE so far). Any thoughts as to the relative merits of Modelsim PE and Active-HDL (PE) for FPGA simulation? Thanks PeteArticle: 146002
On Mar 3, 8:02=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > I've finally decided to buy a better simulator > (I've been making do with Modelsim XE so far). > > Any thoughts as to the relative merits of Modelsim PE and > Active-HDL (PE) for FPGA simulation? I can't say anything about the question you asked, but I can say that I bought the entry level design package for Lattice since they don't have a free version that can actually be used for work like Xilinx and Altera do. I ordered the package that included ModelSim and that was good for me since that is the only simulator I have used. But between the time I sent in the order and the time when I licensed the tool, they changed their agreements and started providing ActiveHDL! I complained loudly but they would not provide a license for the tool I had and would only send me the software for the new tool. So I gave it a try and have hardly looked back. My point is that it is very easy to switch and I am totally happy with ActiveHDL. I can't think of anything about that I don't like other than possibly the way it wants to create its own structure for your files, but I finally figured out how to keep it from copying the source files to it's own directory. I still don't know what the difference between a design and a "workspace" is, but the Lattice version only allows one design to a workspace. I don't seem to be limited by that. RickArticle: 146003
I'm going to be travelling soon, and will continue to do FPGA design from the road. I'll need to get a new laptop for this. Any thoughts? I think something based on the Core i7-620M might be fast enough and low power, but they seem rare. Looks like I'll probably end up with something with a Core i7-720QM or a Core i7-820QM. Anybody here have any experience with on of these machines? Is there another processor I should be looking at? The obvious OS with a new machine would be Windows 7, 64-bit, but I'm not sure my software will run on that. I'm running ISE Foundation 10.1 (and don't plan on upgrading quite yet). I also use Modelsim XE, but will be upgrading to Modelsim PE or Aldec. It's not clear what software runs on what OS. It seems that I might be safer with 32-bit XP for the Modelsim and the Xilinx software. Windows 7 Professional seems to have a downgrade option to XP. Does that mean I choose to install one or the other OS, or can I install both and switch between them? 7 Pro seems to have some sort of XP mode. Will that work for these tools? Is there a performance penalty over a real XP installation? Can I emulate XP 32-bit under W7 64-bit? Thanks for your thoughts and suggestions. PeteArticle: 146004
We bought Active-HDL since they are offering Mixed Language (VHDL & Verilog) simulation at an excellent price point. Also, the Active-HDL gui is much nicer to use (especially the waveform viewer) than Modelsim. Most likely since it is not TCL/TK based like Modelsim (as far as I know). I would vote for Active-HDL even if it was the same price as Modelsim.Article: 146005
On Mar 2, 5:38=A0pm, Charles Richmond <friz...@tx.rr.com> wrote: > Joe Pfeiffer wrote: > > "(see below)" <yaldni...@blueyonder.co.uk> writes: > > >> On 24/02/2010 23:55, in article > >> 1bmxyy42ag....@snowball.wb.pfeifferfamily.net, "Joe Pfeiffer" > >> <pfeif...@cs.nmsu.edu> wrote: > > >>> When I was an undergrad I spent some time programming FORTRAN on a > >>> Harris /6 (I think it was a /6 -- there's something nagging at the ba= ck > >>> of my mind that says it may have been a /7). =A0Anyway, reading the m= anual > >>> I discovered that return addresses were stacked, and immediately jump= ed to > >>> the conclusion that it could do recursion. =A0It turned out that loca= l > >>> variables were static... =A0which meant I spent a *long* time figurin= g out > >>> why my program was producing completely nonsensical results. > > >>> As Al Stewart once sang, "I was jumping to conclusions, and one of th= em > >>> jumped back." > >> People who assumed that FORTRAN local variables *must* be static got j= umped > >> on from the opposite direction when they used FORTRAN compilers that > >> actually did put them on the stack, as the ANS FORTRAN standard was > >> carefully worded to permit. > > > All these decades I thought that was the case.... =A0of course, I only > > programmed FORTRAN for a couple of years around 1980. > > With the older FORTRAN's, you have to "know your implementation". > Tricks were used especially to handle ASCII data in numeric > variables in the early days. > In really older FORTRANs, you would more likely know the tricks used to handle BCDIC or SIXBIT character data as numeric variables. Bruce B. Reynolds, Trailing Edge Technologies, Warminster PAArticle: 146006
On Mar 3, 9:48=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > I'm going to be travelling soon, and will continue to > do FPGA design from the road. I'll need to get a > new laptop for this. > > Any thoughts? Since you're on ISE 10.1, there's no support for multi-threading. Going with the higher speed i7-620M would give you the best bang for your buck until or unless you upgrade ISE. While 11.2 introduced multi-threading for placement, routing won't be multi-threaded until 12.x sometime according to one Xilinx Answer. Multi-threading is great when software's designed for it. We've stepped back from highest-speed processors in favor of more cores to leverage the performance. While I appreciate being able to check email during a place & route, I have yet to truly utilize the 8 threads across 4 cores in my desktop i7. Do you want a laptop to perform better now or to perform better in a year or two? I can provide no guidance on operating system.Article: 146007
On Wed, 03 Mar 2010 06:48:33 -0800, Pete Fraser wrote: > I'm going to be travelling soon, and will continue to do FPGA design > from the road. I'll need to get a new laptop for this. > > Any thoughts? > I think something based on the Core i7-620M might be fast enough and low > power, but they seem rare. Looks like I'll probably end up with > something with a Core i7-720QM or a Core i7-820QM. > Anybody here have any experience with on of these machines? Is there > another processor I should be looking at? > > The obvious OS with a new machine would be Windows 7, 64-bit, but I'm > not sure my software will run on that. I'm running ISE Foundation 10.1 > (and don't plan on upgrading quite yet). I also use Modelsim XE, but > will be upgrading to Modelsim PE or Aldec. > > It's not clear what software runs on what OS. It seems that I might be > safer with 32-bit XP for the Modelsim and the Xilinx software. Windows 7 > Professional seems to have a downgrade option to XP. Does that mean I > choose to install one or the other OS, or can I install both and switch > between them? 7 Pro seems to have some sort of XP mode. Will that work > for these tools? Is there a performance penalty over a real XP > installation? Can I emulate XP 32-bit under W7 64-bit? > > Thanks for your thoughts and suggestions. > > Pete The most important thing for the hardware is cache size and RAM. Get 8G of RAM and make sure that you don't get a bargain processor with an undersized cache. As for the OS, my suggestion would be to use 64 bit Fedora 12. CAE tools have been running on 64 bit Linux for years so they are completely stable. I use both Altera and Xilinx tools on Fedora. ModelSim runs on 64 bit Linux also and of course NCsim and VCS are Linux only. The iCore7 has hardware virtualization support and Fedora 12 comes with KVM built in so you can run multiple VMs painlessly. I run both XP and CentOS5.4 VMs on top of Fedora, the performance is very close to native, I've benchmarked CentOS and it's at least 95% of native speed. I haven't benchmarked XP but it feels very fast as long as you use Rdesktop to access it instead of the console. If you need to run Windows CAE tools for some reason the advantage of using a VM is that you can have more then one VM which gets around XPs 3G total memory limit, although you would still have that limit for each application. Obviously I don't recommend using XP for anything more intense then MS Word, CAE tools should be run on Linux.Article: 146008
On Mar 3, 7:48=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > I'm going to be travelling soon, and will continue to > do FPGA design from the road. I'll need to get a > new laptop for this. > > Any thoughts? > I think something based on the Core i7-620M might > be fast enough and low power, but they seem rare. > Looks like I'll probably end up with something with > a Core i7-720QM or a Core i7-820QM. > Anybody here have any experience with on of these > machines? Is there another processor I should be looking at? > > The obvious OS with a new machine would be Windows 7, > 64-bit, but I'm not sure my software will run on that. > I'm running ISE Foundation 10.1 (and don't plan on > upgrading quite yet). I also use Modelsim XE, but will > be upgrading to Modelsim PE or Aldec. > > It's not clear what software runs on what OS. It seems > that I might be safer with 32-bit XP for the Modelsim > and the Xilinx software. Windows 7 Professional > seems to have a downgrade option to XP. Does that > mean I choose to install one or the other OS, or can > I install both and switch between them? 7 Pro seems > to have some sort of XP mode. Will that work for these > tools? Is there a performance penalty over a real XP > installation? Can I emulate XP 32-bit under W7 64-bit? > > Thanks for your thoughts and suggestions. > > Pete What size of designs are you working on? FWIW, I've had good luck doing smaller stuff in WinXP running from the Bootcamp partition on a MacBook using VMware. I've also gotten stuff built on an EEE901A with WebPack 10.1 under EEEbuntu. EricArticle: 146009
Hi All, I got this newbie Q I hope to get answer for. I'm looking at some example code sent to me by outside contractor, the code makes use of inout ports of the FPGA: -- begin quote IOBUF1 : IOBUF16 port map(DIN => PCI_data(31 downto 16) , DIO => SABD(15 downto 0), DOUT=> SABD_i(15 downto 0), T => PCI_en); -- end quote this iobuf16 is actually an array of 16 IOBUF units, each responsible for an appropriate bit. for example: -- begin quote OBUFT0: IOBUF port map (O => DOUT(0), IO => DIO(0), I => DIN(0), T => T); -- end quote Now, I'm not clear on the operation of this IOBUF 1. The users manual for IOBUF says when T = "1" the IO is in HighZ state, but what happens to O port? is the signal on I port propagated to O? 2. Also, the user's manual does not specify what happens when T = "0" i.e. is the IO propagated to O port? Is the I port propagated to IO? or maybe the I and IO ports compete for "who's driving the O port stronger"? Again, sorry for the newbie Q, but the user's manual isn't too clear on thisArticle: 146010
The IO port goes out of the FPGA. The I port is an input port so it just has whatever value is on the IO port irrespective of signal T. The O port is what you drive to send data out of the FPGA on the IO port. The T signal needs to be low for your data to propagate out. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146011
On Wed, 3 Mar 2010 06:54:00 -0800 (PST) Dave <doomeddave@yahoo.co.uk> wrote: > We bought Active-HDL since they are offering Mixed Language (VHDL & > Verilog) simulation at an excellent price point. > > Also, the Active-HDL gui is much nicer to use (especially the waveform > viewer) than Modelsim. Most likely since it is not TCL/TK based like > Modelsim (as far as I know). > > I would vote for Active-HDL even if it was the same price as Modelsim. > > My experience with both has been that I prefer Active-HDL. The GUI is _much_ more polished; I found the ModelSim GUI to be an active impediment to work. In terms of the simulator itself I had serious problems (in both cases dealing with the Xilinx libraries) with both Active-HDL, which I paid for, and with ModelSim, which I evaled. For what it's worth I found ModelSim's support to be more responsive. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 146012
>Any thoughts as to the relative merits of Modelsim PE and >Active-HDL (PE) for FPGA simulation? > Have had good luck with both. Active-HDL supports command line equivalent of ModelSim. One issue, the "default" format for the Active-HDL waveforms is large and slow (??). I think it was an extra license (cost) for the fast format. I don't recall which version of Active-HDL we had but it might be worth checking before a purchase. Another small note, Mentor had FAE locally (CO) that was useful. Didn't have as good access to Aldec FAE. But maybe I never needed to ask, so it was needed, can't remember? We ran all simulations from scripts (command line) and both worked from that perspective. chris --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146013
I'm trying to use bidirectional pins in Quartus with Verilog. What's the correct way to do it? Altera has some example code: http://www.altera.com/support/examples/verilog/ver_bidirec.html But I don't really understand it. For example, it says it can drive the value b out but I can't see bidir being assigned to at all, rather just being connected to a when oe is asserted.Article: 146014
On Mar 3, 8:36=A0am, Hunter <igal.hun...@gmail.com> wrote: > Hi All, > > I got this newbie Q I hope to get answer for. > > I'm looking at some example code sent to me by outside contractor, the > code makes use of inout ports of the FPGA: > > -- begin quote > IOBUF1 : IOBUF16 > =A0 =A0 =A0 =A0 port map(DIN =3D> PCI_data(31 downto 16) , DIO =3D> SABD(= 15 downto 0), > DOUT=3D> SABD_i(15 downto 0), T =3D> PCI_en); > -- end quote > > this iobuf16 is actually an array of 16 IOBUF units, each responsible > for an appropriate bit. > for example: > -- begin quote > OBUFT0: IOBUF =A0 port map (O =3D> DOUT(0), =A0IO =3D> DIO(0), I =3D> DIN= (0), T =3D> > T); > -- end quote > > Now, I'm not clear on the operation of this IOBUF > 1. The users manual for IOBUF says when T =3D "1" the IO is in HighZ > state, but what happens to O port? is the signal on I port propagated > to O? > 2. Also, the user's manual does not specify what happens when T =3D "0" > i.e. is the IO propagated to O port? Is the I port propagated to IO? > or maybe the I and IO ports compete for "who's driving the O port > stronger"? > > Again, sorry for the newbie Q, but the user's manual isn't too clear > on this This is pretty basic information so I'm a bit surprised that the information isn't clear in the documentation. Which "user's manual" were you reading? Ed McGettigan -- Xilinx Inc.Article: 146015
On 03/03/2010 11:20 AM, emeb wrote: > On Mar 3, 7:48 am, "Pete Fraser"<pfra...@covad.net> wrote: >> I'm going to be travelling soon, and will continue to >> do FPGA design from the road. I'll need to get a >> new laptop for this. >> >> Any thoughts? >> I think something based on the Core i7-620M might >> be fast enough and low power, but they seem rare. >> Looks like I'll probably end up with something with >> a Core i7-720QM or a Core i7-820QM. >> Anybody here have any experience with on of these >> machines? Is there another processor I should be looking at? >> >> The obvious OS with a new machine would be Windows 7, >> 64-bit, but I'm not sure my software will run on that. >> I'm running ISE Foundation 10.1 (and don't plan on >> upgrading quite yet). I also use Modelsim XE, but will >> be upgrading to Modelsim PE or Aldec. >> >> It's not clear what software runs on what OS. It seems >> that I might be safer with 32-bit XP for the Modelsim >> and the Xilinx software. Windows 7 Professional >> seems to have a downgrade option to XP. Does that >> mean I choose to install one or the other OS, or can >> I install both and switch between them? 7 Pro seems >> to have some sort of XP mode. Will that work for these >> tools? Is there a performance penalty over a real XP >> installation? Can I emulate XP 32-bit under W7 64-bit? >> >> Thanks for your thoughts and suggestions. >> >> Pete > > What size of designs are you working on? FWIW, I've had good luck > doing smaller stuff in WinXP running from the Bootcamp partition on a > MacBook using VMware. I've also gotten stuff built on an EEE901A with > WebPack 10.1 under EEEbuntu. > > Eric I think it is important to note the size of your designs. I actually use an HP mini 210HD for a lot of my designs. I run Fedora 12, and ISE 11.1. Sure its not as speedy as can be, but it gets the job done. -- Jason Thibodeau www.jayt.orgArticle: 146016
On Mar 3, 2:33=A0pm, Giorgos Tzampanakis <g...@hw.ac.uk> wrote:
> I'm trying to use bidirectional pins in Quartus with Verilog.
> What's the correct way to do it? Altera has some example code:
>
> http://www.altera.com/support/examples/verilog/ver_bidirec.html
>
> But I don't really understand it. For example, it says it can
> drive the value b out but I can't see bidir being assigned to at
> all, rather just being connected to a when oe is asserted.
assign bidir =3D oe ? a : 8'bZ ;
So why is this different to bidir "being assigned to"? It
says drive bidir with whatever value is on "a" when oe is
high. "a" itself is assigned in the synchronous always
block:
always @ (posedge clk)
begin
a <=3D inp;
end
This presumably shows a registered output. If you wanted
a combinatorial I/O you'd just assign inp directly to bidir
like:
assign bidir =3D oe ? inp : 8'bZ ;
HTH,
Gabor
Article: 146017"Jason Thibodeau" <jason.p.thibodeau@gmail.com> wrote in message news:hmmfsq$gvr$1@news.eternal-september.org... > On 03/03/2010 11:20 AM, emeb wrote: >> What size of designs are you working on? FWIW, I've had good luck >> doing smaller stuff in WinXP running from the Bootcamp partition on a >> MacBook using VMware. I've also gotten stuff built on an EEE901A with >> WebPack 10.1 under EEEbuntu. > > I think it is important to note the size of your designs. I actually use > an HP mini 210HD for a lot of my designs. I run Fedora 12, and ISE 11.1. > Sure its not as speedy as can be, but it gets the job done. It varies. My current design is very small (XC3S250E). Mostly I design with XC5VSX50T, but I'm a consultant, so it's whatever the client wants. Typically the SX50T is a nice sweet spot for price / performance for video processing. My current project is audio, hence the tiny part. PeteArticle: 146018
On Mar 3, 5:02=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > I've finally decided to buy a better simulator > (I've been making do with Modelsim XE so far). > > Any thoughts as to the relative merits of Modelsim PE and > Active-HDL (PE) for FPGA simulation? > > Thanks > > Pete One complaint I have about Active-HDL is that it insists on making a copy of the sources and hiding them in a not so easy to find location. It will then simulate these, and only these copies. If you change a file while simulating, you have to remember to copy it out. If you change something between simulations, you have to re-import it. This "feature" makes the simulator mostly useful only *after* all the bugs are fixed. (argh) The ModelSim windows GUI is definitely getting worse with time. The Linux GUI seems to be getting better though. RKArticle: 146019
Peter Flass <Peter_Flass@Yahoo.com> writes: > Michael Wojcik wrote: >> Peter Flass wrote: >>> Hey! C's finally caught up to PL/I. Only took them 50 years, and then >>> of course all the features are just tacked-on in true C fashion, instead >>> of thought-through. >> >> Well, that's rather insulting to the members of WG14, who spent a >> decade designing those features. Fortunately, they published the >> Rationale showing that, in fact, they were thought through.[1] And a >> great deal of documentation describing the process is available in the >> archives.[2] >> >> If you'd care to show why you think otherwise, perhaps there would be >> some grounds for debate. > > "The flexible array must be last"? > > "sizeof applied to the structure ignores the array but counts any > padding before it"? > > C is a collection of ad-hoc ideas. WG14 may have put a great deal of > thought into how to extend it without breaking the existing mosh, but > that's my point, it's still a mosh. iostream formatting operators, because we really need more operator overloading and no enhancements are too bizarre in service of making everything, (for particular values of everything), specialized? Oh but wait, you can compile, install and dig your way through Boost so as to avoid the fun & games of vanilla iostream. Thank goodness printf and friends are still around. Which I suppose isn't an argument that the feature wasn't designed, but is perhaps in support of the "ad-hoc" argument. One more wacky idea thrown on the pile for the amusement of the programmer. GregmArticle: 146020
On Mar 3, 4:19=A0pm, "Pete Fraser" <pfra...@covad.net> wrote: > "Jason Thibodeau" <jason.p.thibod...@gmail.com> wrote in message > > news:hmmfsq$gvr$1@news.eternal-september.org... > > > On 03/03/2010 11:20 AM, emeb wrote: > >> What size of designs are you working on? FWIW, I've had good luck > >> doing smaller stuff in WinXP running from the Bootcamp partition on a > >> MacBook using VMware. I've also gotten stuff built on an EEE901A with > >> WebPack 10.1 under EEEbuntu. > > > I think it is important to note the size of your designs. I actually us= e > > an HP mini 210HD for a lot of my designs. I run Fedora 12, and ISE 11.1= . > > Sure its not as speedy as can be, but it gets the job done. > > It varies. > My current design is very small (XC3S250E). > Mostly I design with XC5VSX50T, but I'm a consultant, so it's whatever th= e > client wants. > Typically the SX50T is a nice sweet spot for price / performance for vide= o > processing. > My current project is audio, hence the tiny part. My personal preference is to optimize the part I deal with, the LCD. My main requirement in the laptop I bought was a 17" screen and I pretty much always go for the low price. I got a deal on a unit being discontinued even though it has an AMD processor. The only shortcoming is the small battery so it only runs and hour and a half on battery. I spend hours writing code and looking at simulations, but the time spent crunching the design or running the simulation is a very small percentage of that. For what you will pay for an i7 laptop you can by a low end unit today and in two years also buy the i7 you are looking at now. So think of it this way, the design software does not require so much more than it did two years ago. So the low end laptop you buy today is more than adequate for the job! If you later need the i7 laptop for some big job you can buy one then for a lot less or an even better one for the same price. On the other hand, I suggest that you spend time and money on a backup procedure and use it religiously. No machine is immune from hard drive crashes and a laptop is especially bad. Worse, if you are traveling with it, it can be stolen. So make sure your backups are separate and secure. US Mail will safely transport CD/DVDs to the repository of your choice. BTW, for a simulator I find the Aldec software to be good. I seem to have very little trouble with it while every version of Modelsim I've ever used seems to have at least one problem, a memory leak (or so I suspect) that crashes the program after some arbitrary amount of time. But then I haven't used Modelsim in three or four years. RickArticle: 146021
On Mar 3, 5:42=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Mar 3, 5:02=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > > > I've finally decided to buy a better simulator > > (I've been making do with Modelsim XE so far). > > > Any thoughts as to the relative merits of Modelsim PE and > > Active-HDL (PE) for FPGA simulation? > > > Thanks > > > Pete > > One complaint I have about Active-HDL is that it insists on making a > copy of the sources and hiding them in a not so easy to find > location. =A0It will then simulate these, and only these copies. =A0If yo= u > change a file while simulating, you have to remember to copy it out. > If you change something between simulations, you have to re-import it. > > This "feature" makes the simulator mostly useful only *after* all the > bugs are fixed. =A0(argh) > > The ModelSim windows GUI is definitely getting worse with time. =A0The > Linux GUI seems to be getting better though. > > RK The copying of source files to a folder within the simulation directory is the default, but you can override it. The "Add Files" dialog box has a "Make Local Copy" checkbox which once you uncheck it, seems to stay unchecked. My most recent issue with ActiveHDL is how to copy a project. But I finally figured out that "Save Design As" in the File menu does what I want. Just "Save As" only seems to save the waveform file. I kept looking under things titled "Workspace" which was not the ticket. RickArticle: 146022
"d_s_klein" <d_s_klein@yahoo.com> wrote in message news:1f799796-32dd-4768-b66a-a935352c24f1@u19g2000prh.googlegroups.com... On Mar 3, 5:02 am, "Pete Fraser" <pfra...@covad.net> wrote: > I've finally decided to buy a better simulator > (I've been making do with Modelsim XE so far). > >One complaint I have about Active-HDL is that it insists on making a >copy of the sources and hiding them in a not so easy to find >location. It will then simulate these, and only these copies. If you >change a file while simulating, you have to remember to copy it out. >If you change something between simulations, you have to re-import it. > >This "feature" makes the simulator mostly useful only *after* all the >bugs are fixed. (argh) > > >The ModelSim windows GUI is definitely getting worse with time. Yes, I found the same, however, when you install a new version of Modelsim the registry keys are not overwritten so to preserve your GUI settings. I found that deleting (or renaming) this entry fixes a lot of GUI instabilities. When you restart Modelsim it automatically rebuilds them. See: HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim Hans www.ht-lab.comArticle: 146023
A few years ago I designed a small prototype board to allow access to an FPGA internal registers via a single bi-directional pin. This replaces an RS232 type interface but is USB driven so removes the need for external power supplies for level shifters etc. This has been invaluable, I've used it with almost every board I have designed over the last few years, so I have developed the prototype and have come up with the 1 Pin Interface... www.1pin-interface.com This allows easy access to an FPGAs status or control registers via a simple Excel driven interface. Any comments, questions or orders are welcome. Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883 32/12 Hardengreen Business Park Fax: +44 131 663 8771 Dalkeith, Midlothian EH22 3NX www.nialstewartdevelopments.co.ukArticle: 146024
> www.1pin-interface.com I've been emailed to say that some people are having problems with this. This is based on a Tiddlywiki, a quick google shows that the Skype plug-in breaks some wiki-sites. It's in the Skype bug list to be fixed. If you do have any problems try disabling Skype to view it. Hardly an auspicious start. :-( Nial
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