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On Mar 5, 12:50=A0pm, -jg <jim.granvi...@gmail.com> wrote: > =A0But the chatter on actually using this with DLLs, seems ominously > quiet.. it does not like the DLL syntax, and examples were not easy to > find... I found an all important working example. http://sourceforge.net/projects/realterm/files/ http://realterm.sourceforge.net/ This needs a dll downloaded from http://www.i2cchip.com/digital_display_module.html#I2CHelper DLL and win registered, and then the Basic Code from Open Office Seems to do what it should. Should make a good starting point ? -jgArticle: 146076
-jg wrote: > This needs a dll downloaded from > http://www.i2cchip.com/digital_display_module.html#I2CHelper DLL > > and win registered, and then the Basic Code from Open Office Seems to > do what it should. > > Should make a good starting point ? dunno, i'm on Debian, Fedora and Slackware... ;-) > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 146077
On Thu, 04 Mar 2010 16:45:40 -0500 Peter Flass <Peter_Flass@Yahoo.com> wrote: > I've said before, C started out as a fairly simple and clean language, > with possibly a few rough spots. Unfortunately instead of accepting it > on its own terms, and maybe coming up with "D", people tried to turn it This also happened read about D here http://www.digitalmars.com/d/ -- Steve O'Hara-Smith | Directable Mirror Arrays C:>WIN | A better way to focus the sun The computer obeys and wins. | licences available see You lose and Bill collects. | http://www.sohara.org/Article: 146078
On Fri, 5 Mar 2010 02:22:20 +0000 (UTC), Giorgos Tzampanakis wrote:
>I've tried to use an inout reg with quartus and it doesn't give a
>warning. However, I read on the internet that an inout port can
>only be a wire. Which one is true?
It is unquestionably true that an inout port must be a net
(wire), and also that you must connect a net to any inout
port when you instantiate the module. "reg" on either
side of an inout port is definitely illegal.
If your design uses the inout port in a unidirectional
manner, it is possible that synthesis might be able to
do something useful with a reg on one or other side of it.
However, the resulting illegal Verilog code will never
work in any simulator. Don't do it.
The classic use of an inout port, to provide a bidi
tri-state signal, is straightforward. Inside the module
you need two signals or expressions - probably reg -
to provide the buffer enable and buffer data. You then
use a continuous assign to imply the buffer:
module has_bidi ( inout bidi, ...);
...
reg bidi_enable;
reg bidi_drive_value;
wire bidi_receive_value;
...
assign bidi = bidi_enable? bidi_drive_value: 1'bx;
assign bidi_receive_value = bidi;
...
.... other logic to use "bidi_receive_value"
.... and generate "bidi_enable" and "bidi_drive_value"
endmodule
The second "assign" does nothing more than renaming the port
for internal use, but it can often be convenient to do that.
--
Jonathan Bromley
Article: 146079On Fri, 05 Mar 2010 00:29:51 +0000, Symon wrote: >> time they ship product. Successful startups usually have something >> that is *many* times better than the existing products, on some axis >> almost entirely orthogonal to the prior metrics. > >Mate, >Ever wonder if you've been doing this too long? Did you write that last >phrase with a straight face? Aw, c'mon, don't give us a hard time. Sometimes we're so exposed to that kind of MBA-speak that a bit of it leaks into our heads unbidden. At least Eric didn't talk about "crossing the chasm" (squirm). -- Jonathan BromleyArticle: 146080
> Should make a good starting point ? It could but I'm so busy with client work I just don't have the time to investigate. I've had the assembled PCBs and enclosures for this production run for over six months, I've just had so much else on that I haven't been able to 'launch' it until now. I'm afraid that for the forseeable future Excel is all that I will be supporting. I'll publish as much information as I can to let people use other interface languages/techniques but I can't support it. Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883 32/12 Hardengreen Business Park Fax: +44 131 663 8771 Dalkeith, Midlothian EH22 3NX www.nialstewartdevelopments.co.ukArticle: 146081
On Mar 4, 11:08=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Mar 5, 9:14=A0am, Andy Peters <goo...@latke.net> wrote: > > > Putting a processor inside an FPGA has proven to us to be a bigger PITA= than it's worth. > > Consider than instead of V4FX, you can use an S3AN and a standalone > > PPC and you'll pay a whole lot less. Plus the various Freescale PPCs > > have DDR memory and Ethernet and DMA controllers that don't suck, and > > you're not stuck with crappy tools. > > Yes, you should always 'reality check' the alternatives. > It can make sense if the resource really is 'free', but SRAM FPGA's > still need external code memory, and when you look at those newest uC > prices, they are LESS than SRAM!! > > We could use the A2F060, if the price and package are right. - but we > consider it more a uC + CPLD, than > a FPGA. > > -jg dont judge on the mouser pricing yet, the price issue will be key issue that is recognized by Actel also, specially A2F060 must come to low price to make it an option to choose at all, at the mouser prices for A2F200 i guess it would be very little applications where on would pay that price AnttiArticle: 146082
On 3/5/2010 8:32 AM, Jonathan Bromley wrote: > On Fri, 05 Mar 2010 00:29:51 +0000, Symon wrote: > >>> time they ship product. Successful startups usually have something >>> that is *many* times better than the existing products, on some axis >>> almost entirely orthogonal to the prior metrics. >> >> Mate, >> Ever wonder if you've been doing this too long? Did you write that last >> phrase with a straight face? > > Aw, c'mon, don't give us a hard time. Sometimes we're so > exposed to that kind of MBA-speak that a bit of it leaks > into our heads unbidden. > > At least Eric didn't talk about "crossing the chasm" (squirm). I forgot the smiley, sorry! I hope I've not upset the FPGA community? :-) I particularly chuckled at 'almost entirely'. A bit like 'nearly unique', or '82% pregnant'. I wonder if a lot of small companies are stymied by the legal stuff surrounding patent law. It seems the big boys patent anything and everything, whether it's novel and innovative or not, and then use the lawyers to kill anyone who tries to compete. Here's a recent example:- http://www.theregister.co.uk/2010/03/03/apple_htc_google/ I wonder if there should be some kind of vexatious litigant law, or a SLAPP type law. I guess that's why these patent cases are never heard in California which seems to have fairly sensible legislation in this area. My iPhone has designed in California on it, why are Apple suing HTC in Delaware? Cheers, Syms.Article: 146083
Andy Peters <google@latke.net> writes: > ModelSim has one project file (the .mpf) which is plain text and > easily edited by hand. Various others have also mentioned project files and workspaces and the like... Am I the only one that makes *no* use of the various "project things" (either in Modelsim or Aldec)? I just have a makefile and use the GUI to run the sim (from "their" command-line) and show me the waveforms. I guess I don't like to be tied to a tool (as much as I can manage) much as I don't like to be tied to a particular silicon vendor (as much as I can manage :) Am I missing something valuable, or is it just different? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 146084
> Am I the only one that makes *no* use of the various "project things" > (either in Modelsim or Aldec)? =A0I just have a makefile and use the GUI > to run the sim (from "their" command-line) and show me the waveforms. I do the same so that makes at least two of us! Scripts are best for source control, staying sane and having weekends free...Article: 146085
Hello to all !
I've problem with finite state machine. Because I have not much place in my
FPGA and I need to create few more FSM i found that FSM logic can be packed
in to BRAM. I created simple FSM in VHDL and it shows in raport that it
uses Bram but there is a warning :
WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please
check that the RAM contents is read synchronously.
I tried to make the simplest FSM but it dont change anything...
Can someone show me an example of code in VHDL of simple state machine that
can be packed in to BRAM with any warnings, errors. I just worry that my
design won't work. I have ISE 11.1 and Spartan 3a...
Thanks for any response...
XST log :
Reading design: binary.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/FPGA PRAM/Debug/MultiCore/Example.vhd" in Library
work.
Architecture behv of Entity binary is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <binary> in library <work> (architecture
<behv>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <binary> in library <work> (Architecture <behv>).
Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal
<CS>.
Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal
<NS>.
Entity <binary> analyzed. Unit <binary> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <binary>.
Related source file is "C:/FPGA PRAM/Debug/MultiCore/Example.vhd".
Found finite state machine <FSM_0> for signal <CS>.
-----------------------------------------------------------------------
| States | 7
|
| Transitions | 16
|
| Inputs | 6
|
| Outputs | 3
|
| Clock | CLOCK (rising_edge)
|
| Power Up State | s1
|
| Encoding | compact
|
| Implementation | BRAM
|
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <binary> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Implementing FSM <FSM_0> on signal <CS> on BRAM.
Synthesizing (advanced) Unit <CS>.
WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please
check that the RAM contents is read synchronously.
-----------------------------------------------------------------------
| ram_type | Block |
|
-----------------------------------------------------------------------
| Port A
|
| aspect ratio | 512-word x 6-bit |
|
| mode | write-first |
|
| clkA | connected to signal <Clk_FSM> | rise
|
| weA | connected to internal node | high
|
| addrA | connected to signal <In0> |
|
| diA | connected to internal node |
|
| doA | connected to signal <Out2> |
|
-----------------------------------------------------------------------
| optimization | area |
|
-----------------------------------------------------------------------
Unit <CS> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <binary> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block binary, actual ratio is
0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 2.625ns (Maximum Frequency: 380.952MHz)
Minimum input arrival time before clock: 1.342ns
Maximum output required time after clock: 6.860ns
Maximum combinational path delay: No path found
=========================================================================
Process "Synthesis" completed successfully
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 146086On 3/5/2010 11:39 AM, de4 wrote: > > Can someone show me an example of code in VHDL of simple state machine that > can be packed in to BRAM with any warnings, errors. I just worry that my > design won't work. I have ISE 11.1 and Spartan 3a... > XAPP291Article: 146087
On 2 Mrz., 22:28, -jg <jim.granvi...@gmail.com> wrote: > On Mar 3, 12:22=A0am, Symon <symon_bre...@hotmail.com> wrote: > meanwhile, over in the other corners, anyone remember Triscend ? I do. I tried to use their Arm7 part. I gave up after i discovered their P&R software Fastchip entirely written in Java still sucked after giving it a new machine with lots of memory and processing power. But at that time a Arm7 MCU alone was quite interesting...Article: 146088
rickman pisze: > On Mar 4, 7:42 am, Adam Górski <totutousungors...@malpawp.pl> wrote: >> Pete Fraser pisze: >> >> >> >>> I'm going to be travelling soon, and will continue to >>> do FPGA design from the road. I'll need to get a >>> new laptop for this. >>> Any thoughts? >>> I think something based on the Core i7-620M might >>> be fast enough and low power, but they seem rare. >>> Looks like I'll probably end up with something with >>> a Core i7-720QM or a Core i7-820QM. >>> Anybody here have any experience with on of these >>> machines? Is there another processor I should be looking at? >>> The obvious OS with a new machine would be Windows 7, >>> 64-bit, but I'm not sure my software will run on that. >>> I'm running ISE Foundation 10.1 (and don't plan on >>> upgrading quite yet). I also use Modelsim XE, but will >>> be upgrading to Modelsim PE or Aldec. >>> It's not clear what software runs on what OS. It seems >>> that I might be safer with 32-bit XP for the Modelsim >>> and the Xilinx software. Windows 7 Professional >>> seems to have a downgrade option to XP. Does that >>> mean I choose to install one or the other OS, or can >>> I install both and switch between them? 7 Pro seems >>> to have some sort of XP mode. Will that work for these >>> tools? Is there a performance penalty over a real XP >>> installation? Can I emulate XP 32-bit under W7 64-bit? >>> Thanks for your thoughts and suggestions. >>> Pete >> Use Remote desktop or similar . >> You can have really powerful PC for fpga compilation this way. >> If you have inet connection of course. >> >> Adam > > Way back when, this software was purchased (PC Anywhere sticks in my > mind). Then I believe MS included it with WinXP, that was how IT used > to "fix" my PC. But I see now it is back to being commercial > software. This this software different somehow than the stuff they > had in WinXP or is that gone again? Remote desktop is included in WinXp Profesional and higher. also in Vista Pro and higher. AdamArticle: 146089
Martin Thompson <martin.j.thompson@trw.com> writes: > Am I the only one that makes *no* use of the various "project things" > (either in Modelsim or Aldec)? I just have a makefile and use the GUI I almost always use my own set of command line tools to run the simulation and eventually I use the waveform viewer for debugging. I've been very happy with VCS in this regard. I never use the bundled project or revision control stuff (I use mostly git and/or svn). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 146090
Hi folks, I have been introduced to a project where I have to implement a TFT display controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200 and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a total newbie in the field of image processing on FPGAs I would ask you for your recommendation about size and type of FPGA, especially in terms of logic for video scaling and SRAM memories for frame buffer storage. Many thanks in advance. KR, MauriceArticle: 146091
On Mar 5, 10:00=A0am, "Maurice Branson" <trauben...@arcor.de> wrote: > Hi folks, > > I have been introduced to a project where I have to implement a TFT displ= ay > controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controlle= r > has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x120= 0 > and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am= a > total newbie in the field of image processing on FPGAs I would ask you fo= r > your recommendation about size and type of FPGA, especially in terms of > logic for video scaling and SRAM memories for frame buffer storage. > > Many thanks in advance. > > KR, Maurice Depending on how much processing you do, you might find that you're actually limited in choice by the number of I/O's you need rather than the fabric capacity of the part. The family choice probably depends on your interface speed. If you need Panel-Link at high data rates, for example you probably want to look at newer parts. Most video designs use SDRAM for frame buffer, as there is no speed penalty when the bulk of your access is sequential, and latency is almost never an issue. DDR2 works well without all the external terminating components or Vtt supply if you can use just one or two parts and keep the routes down around an inch. For scaling it's best to pick a family with built-in multipliers, but again since latency is usually not an issue, you could build multipliers from the fabric as long as you pipeline them enough to run at speed. The number of multipliers depends to some extent on the maximum scaling ratio, because you'll need to build better filters for higher scaling ratios (more taps). At small scaling ratios, like 1.2:1 for example, you can probably ditch the filters and just use interpolation. HTH, GaborArticle: 146092
On Mar 5, 2:41=A0pm, Symon <symon_bre...@hotmail.com> wrote: > On 3/5/2010 11:39 AM, de4 wrote: > > > > > Can someone show me an example of code in VHDL of simple state machine = that > > can be packed in to BRAM with any warnings, errors. I just worry that m= y > > design won't work. I have ISE 11.1 and Spartan 3a... > > XAPP291 xapp291 does NOT show how from SM VHDL code a implementation using BRAM is generated by the tools AnttiArticle: 146093
On 3/5/2010 4:08 PM, Antti wrote: > On Mar 5, 2:41 pm, Symon<symon_bre...@hotmail.com> wrote: >> On 3/5/2010 11:39 AM, de4 wrote: >> >> >> >>> Can someone show me an example of code in VHDL of simple state machine that >>> can be packed in to BRAM with any warnings, errors. I just worry that my >>> design won't work. I have ISE 11.1 and Spartan 3a... >> >> XAPP291 > > xapp291 does NOT show how from SM VHDL code a implementation using > BRAM is generated by the tools > > Antti But it _IS_ an example of 'code in VHDL of [a] simple state machine that can be packed in to BRAM'. Syms.Article: 146094
On Mar 5, 4:39=A0am, "de4" <de4@n_o_s_p_a_m.poczta.onet.pl> wrote: > Hello to all ! > > I've problem with finite state machine. Because I have not much place in = my > FPGA and I need to create few more FSM i found that FSM logic can be pack= ed > in to BRAM. I created simple FSM in VHDL and it shows =A0in raport that i= t > uses Bram but there is a warning : > > WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please > check that the RAM contents is read synchronously. > > I tried to make the simplest FSM but it dont change anything... Are you using the two-process state machine construct? If so, DON'T. -aArticle: 146095
On Mar 4, 1:20=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Does anyone know if the information needed to do that still exists? I suspect it was _very_ closely guarded back in the day, because it would have been a matter of very serious concern had the Russians been able to make a 360/195 equivalent to top out their RJAD/EC line. So I'm thinking more along the line of a design from scratch to match the public specifications, working from the 360/91 descriptions in the open literature, and adding a cache (which shouldn't be too difficult, there being caches on OpenCores). I'm not saying *I* could do stuff like that on my very own, but there's a lot out there one could use as a starting point. John SavardArticle: 146096
On Mar 5, 7:54=A0am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote: > rickman pisze: > > > > > On Mar 4, 7:42 am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote: > >> Pete Fraser pisze: > > >>> I'm going to be travelling soon, and will continue to > >>> do FPGA design from the road. I'll need to get a > >>> new laptop for this. > >>> Any thoughts? > >>> I think something based on the Core i7-620M might > >>> be fast enough and low power, but they seem rare. > >>> Looks like I'll probably end up with something with > >>> a Core i7-720QM or a Core i7-820QM. > >>> Anybody here have any experience with on of these > >>> machines? Is there another processor I should be looking at? > >>> The obvious OS with a new machine would be Windows 7, > >>> 64-bit, but I'm not sure my software will run on that. > >>> I'm running ISE Foundation 10.1 (and don't plan on > >>> upgrading quite yet). I also use Modelsim XE, but will > >>> be upgrading to Modelsim PE or Aldec. > >>> It's not clear what software runs on what OS. It seems > >>> that I might be safer with 32-bit XP for the Modelsim > >>> and the Xilinx software. Windows 7 Professional > >>> seems to have a downgrade option to XP. Does that > >>> mean I choose to install one or the other OS, or can > >>> I install both and switch between them? 7 Pro seems > >>> to have some sort of XP mode. Will that work for these > >>> tools? Is there a performance penalty over a real XP > >>> installation? Can I emulate XP 32-bit under W7 64-bit? > >>> Thanks for your thoughts and suggestions. > >>> Pete > >> Use Remote desktop or similar . > >> You can have really powerful PC for fpga compilation this way. > >> If you have inet connection of course. > > >> Adam > > > Way back when, this software was purchased (PC Anywhere sticks in my > > mind). =A0Then I believe MS included it with WinXP, that was how IT use= d > > to "fix" my PC. =A0But I see now it is back to being commercial > > software. =A0This this software different somehow than the stuff they > > had in WinXP or is that gone again? > > Remote desktop is included in WinXp Profesional and higher. > also in Vista Pro and higher. > > Adam Vista *what* pro? I've got Vista Home Pro. Do I have this? I expect not. RickArticle: 146097
On Feb 26, 4:56=A0am, Ahem A Rivet's Shot <ste...@eircom.net> wrote: > =A0 =A0 =A0 =A0 No, he's saying that C doesn't really implement an array = type, the > var[offset] syntax is just syntactic sugar for *(var + offset) which is w= hy > things like 3[x] work the same as x[3] in C. Um, no. x =3D y + 3 ; in a C program will _not_ store in x the value of y plus the contents of memory location 3. On a big-endian machine, long int x[5] ; x[0] =3D 3 ; x[1] =3D 12 ; y =3D x[0] ; or, on a little-endian machine, long int x[5] ; x[1] =3D 3 ; x[0] =3D 12 ; y =3D x[1] ; will not result in zero being stored in y, since a long int variable occupies more than one byte in storage, and hence the two assignments are being made to overlapping variables. Yes, C doesn't do _bounds checking_, but that is a far cry from "syntactic sugar for variable plus address offset". John SavardArticle: 146098
On Mar 5, 12:06=A0pm, rickman <gnu...@gmail.com> wrote: > On Mar 5, 7:54=A0am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote: > > > > > rickman pisze: > > > > On Mar 4, 7:42 am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote= : > > >> Pete Fraser pisze: > > > >>> I'm going to be travelling soon, and will continue to > > >>> do FPGA design from the road. I'll need to get a > > >>> new laptop for this. > > >>> Any thoughts? > > >>> I think something based on the Core i7-620M might > > >>> be fast enough and low power, but they seem rare. > > >>> Looks like I'll probably end up with something with > > >>> a Core i7-720QM or a Core i7-820QM. > > >>> Anybody here have any experience with on of these > > >>> machines? Is there another processor I should be looking at? > > >>> The obvious OS with a new machine would be Windows 7, > > >>> 64-bit, but I'm not sure my software will run on that. > > >>> I'm running ISE Foundation 10.1 (and don't plan on > > >>> upgrading quite yet). I also use Modelsim XE, but will > > >>> be upgrading to Modelsim PE or Aldec. > > >>> It's not clear what software runs on what OS. It seems > > >>> that I might be safer with 32-bit XP for the Modelsim > > >>> and the Xilinx software. Windows 7 Professional > > >>> seems to have a downgrade option to XP. Does that > > >>> mean I choose to install one or the other OS, or can > > >>> I install both and switch between them? 7 Pro seems > > >>> to have some sort of XP mode. Will that work for these > > >>> tools? Is there a performance penalty over a real XP > > >>> installation? Can I emulate XP 32-bit under W7 64-bit? > > >>> Thanks for your thoughts and suggestions. > > >>> Pete > > >> Use Remote desktop or similar . > > >> You can have really powerful PC for fpga compilation this way. > > >> If you have inet connection of course. > > > >> Adam > > > > Way back when, this software was purchased (PC Anywhere sticks in my > > > mind). =A0Then I believe MS included it with WinXP, that was how IT u= sed > > > to "fix" my PC. =A0But I see now it is back to being commercial > > > software. =A0This this software different somehow than the stuff they > > > had in WinXP or is that gone again? > > > Remote desktop is included in WinXp Profesional and higher. > > also in Vista Pro and higher. > > > Adam > > Vista *what* pro? =A0I've got Vista Home Pro. =A0Do I have this? =A0I exp= ect > not. > > Rick Doh! Nevermind. I have Vista Home *Premium*. The business version is Vista Professional which is what you said... RickArticle: 146099
On Feb 22, 3:53=A0pm, Peter Flass <Peter_Fl...@Yahoo.com> wrote: > PL/I can be, but doesn't have to be. =A0If the arguments of a procedure > match the parameters, only the argument address (and possibly a > descriptor address for strings structures, and arrays) is passed. Doesn't PL/I (or, rather, normal implementations thereof) support separate compilation of subroutines, just like FORTRAN and COBOL? John Savard
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