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Hi all, I have a Spartan 3 Starter Board. I want to make a simple application with microblaze. But when I generate the bitstream an error error has appeared wich is: ERROR:Pack:2310 - Too many comps of type "RAMB16" found to fit this device. ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed. NOTE: An NCD file will still be generated to allow you to examine the mapped design. This file is intended for evaluation use only, and will not process successfully through PAR. Mapping completed. See MAP report file "system_map.mrp" for details. Problem encountered during the packing phase. Design Summary -------------- Number of errors : 2 Number of warnings : 18 ERROR:Xflow - Program map returned error code 2. Aborting flow execution... make: *** [__xps/system_routed] Error 1 Done! This error bothers me and I can't understand where is the problem resides?? Note that my design and my software application are as simple as possible, and I was respected the address range of lmb_bram_if_cntlr (8k for spartan 3). If anybody has a useful idea,i Iwill be thankfull if he give me some help. Best Regards, INESArticle: 145676
On 2/18/2010 1:11 PM, de4 wrote: >> > PROCESS(D, Clock, Reset) > BEGIN > IF Reset = '1' THEN -- Don’t wait for clock > Q<= '0'; > notQ<= '1'; > ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge > Q<= D; > notQ<= not D; > END IF; > END PROCESS; > > end CPU; > > > and this reset is connected to button on a board... > So I think rather not... > Hi, So, it probably isn't the problem, but why is 'D' in your sensitivity list? You should build a debounce circuit for the reset button that is synchronous to your clock. http://en.wikipedia.org/wiki/Switch#Contact_bounce HTH., Syms.Article: 145677
Also http://www.xilinx.com/support/documentation/white_papers/wp272.pdfArticle: 145678
Ines, What is it about "it does not fit, you used too many BRAMs, please examine these files to discover your error" that you do not understand? Remember the BRAM blocks are in kilobits, not kilobytes. It is very easy to exceed the number of BRAMS in a part by simple requiring too much addressable memory space, Additionally, if you are specifying cache for the MicroBlaze core, that cache will also eat up BRAM blocks, depending on how much cache you requested (for data and/or instructions). AustinArticle: 145679
On Feb 17, 7:51=A0pm, rickman <gnu...@gmail.com> wrote: > On Feb 17, 8:05 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Feb 17, 4:29 pm, rickman <gnu...@gmail.com> wrote: > > > Fight fire with fire! =A0The two reports below show that both the > > > missing else and the missing assignment (which is also missing in the > > > missing else case) produce latches. > > > > @W: CL117 :"C:\arius\boards\tdc_upgrade\tests\latchsynthtest.vhd": > > > 57:4:57:7|Latch generated from process for signal Latch, probably > > > caused by a missing assignment in an if or case stmt > > > @W: CL117 :"C:\arius\boards\tdc_upgrade\tests\latchsynthtest.vhd": > > > 40:4:40:7|Latch generated from process for signal Comb, probably > > > caused by a missing assignment in an if or case stmt > > > > library ieee; > > > use ieee.std_logic_1164.all; > > > use ieee.numeric_std.all; > > > > entity LatchSynthTest is > > > =A0 port( > > > =A0 =A0 =A0 =A0 =A0 CLK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0 = =A0std_logic ; > > > =A0 =A0 =A0 =A0 =A0 RESET =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0 = =A0std_logic ; > > > =A0 =A0 =A0 =A0 =A0 C01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0 = =A0std_logic ; > > > =A0 =A0 =A0 =A0 =A0 C02 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0 = =A0std_logic ; > > > =A0 =A0 =A0 =A0 =A0 LatchOutput =A0 : out =A0 std_logic ; > > > =A0 =A0 =A0 =A0 =A0 CombOutput =A0 =A0: out =A0 std_logic > > > =A0 =A0 =A0 =A0 =A0 ); > > > end LatchSynthTest ; > > > > architecture behavior of LatchSynthTest is > > > =A0 SIGNAL Latch =A0 =A0 =A0 =A0 =A0: std_logic; > > > =A0 SIGNAL Comb =A0 =A0 =A0 =A0 =A0 : std_logic; > > > =A0 SIGNAL LatchReg =A0 =A0 =A0 : std_logic; > > > =A0 SIGNAL CombReg =A0 =A0 =A0 =A0: std_logic; > > > > begin > > > > =A0 CombOutput =A0 =A0<=3D CombReg; > > > =A0 LatchOutput =A0 <=3D LatchReg; > > > > =A0 Process_1 : process(RESET, CLK) > > > =A0 begin > > > =A0 =A0 if (RESET =3D '1') then > > > =A0 =A0 =A0 LatchReg =A0<=3D '0'; > > > =A0 =A0 =A0 CombReg =A0 <=3D '0'; > > > =A0 =A0 elsif (rising_edge(CLK)) then > > > =A0 =A0 =A0 LatchReg =A0<=3D Latch; > > > =A0 =A0 =A0 CombReg =A0 <=3D Comb; > > > =A0 =A0 end if; > > > =A0 end process; > > > > =A0 CombProc : process(CombReg, C01, C02) > > > =A0 begin > > > =A0 =A0 case CombReg is > > > =A0 =A0 =A0 when '0' =3D> > > > =A0 =A0 =A0 =A0 if (C01 =3D '1') then > > > =A0 =A0 =A0 =A0 =A0 Comb <=3D '0'; > > > =A0 =A0 =A0 =A0 elsif (C02 =3D '1') then > > > =A0 =A0 =A0 =A0 =A0 Comb <=3D '1'; > > > =A0 =A0 =A0 =A0 else > > > =A0 =A0 =A0 =A0 =A0 -- Here an assignment statement is missing, but i= t doesn't > > > =A0 =A0 =A0 =A0 =A0 -- generate latch. =A0It is treated as a null sta= tement. - > > > Weng > > > =A0 =A0 =A0 =A0 end if; > > > =A0 =A0 =A0 when others =3D> > > > =A0 =A0 =A0 =A0 Comb <=3D '1'; > > > =A0 =A0 end case; > > > =A0 end process; > > > > =A0 LatchProc : process(LatchReg, C01, C02) > > > =A0 begin > > > =A0 =A0 case LatchReg is > > > =A0 =A0 =A0 when '0' =3D> > > > =A0 =A0 =A0 =A0 if C01 =3D '1' then > > > =A0 =A0 =A0 =A0 =A0 Latch <=3D '0'; > > > =A0 =A0 =A0 =A0 elsif C02 =3D '1' then > > > =A0 =A0 =A0 =A0 =A0 Latch <=3D '1'; > > > =A0 =A0 =A0 =A0 =A0 -- Here the else is missing, and it does > > > =A0 =A0 =A0 =A0 =A0 -- generate latch. =A0It is treated as a null sta= tement. > > > =A0 =A0 =A0 =A0 end if; > > > =A0 =A0 =A0 when others =3D> > > > =A0 =A0 =A0 =A0 Latch <=3D '1'; > > > =A0 =A0 end case; > > > =A0 end process; > > > > end behavior; > > > Hi, > > Thank you, Andy, Rick and everyone, I am wrong in the second point: > > missing "else" or missing an assignment statement. > > > But my first point is how to generate a latch for a compiler. Rick, > > can you see the floor plan to show how the latch is generated: for the > > state only or for full states? > > > Weng > > I'm not clear what you mean by "how". =A0Are you asking about the detail > of how it is implemented in the FPGA? =A0In the Lattice part they used a > FF as a latch. =A0A register is between the latch and the output. =A0They > drive the latch oddly driving both the clock and the async reset > inputs with logic, but then if you look at the code what would you > think is the clock? =A0I don't see why they did it the way they did, but > it works correctly according to the VHDL. =A0With only four inputs I > would expect they could have just used a single LUT4 and the latch > with the clock always enabled. > > Din =3D=3D '1' > Latch Enable =3D=3D CombReg + C02 > Async Clear =A0=3D=3D ~CombReg * C01 > > Is this what you are asking? > > Rick Rick, Yes, that is what I want. Could you please send the code and a window screen frame using Window's Paint so that I can see the full picture. Thank you. WengArticle: 145680
On Feb 18, 2:21=A0am, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk>
wrote:
> You need to post your code so we can see how you have coded the DCM.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com
Here is it, thanks.
DCM_1 : DCM_ADV
generic map(
CLK_FEEDBACK =3D> "1X",
CLKDV_DIVIDE =3D> 2.0,
CLKFX_DIVIDE =3D> 1,
CLKFX_MULTIPLY =3D> 2,
CLKIN_DIVIDE_BY_2 =3D> FALSE,
CLKIN_PERIOD =3D> 7.6921, -- 7.69 for 130MHz
CLKOUT_PHASE_SHIFT =3D> "NONE",
DCM_PERFORMANCE_MODE =3D> "MAX_SPEED",
DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE =3D> "LOW",
DLL_FREQUENCY_MODE =3D> "LOW",
DUTY_CYCLE_CORRECTION =3D> TRUE,
PHASE_SHIFT =3D> 0,
STARTUP_WAIT =3D> FALSE
)
port map (
CLK0 =3D> SClkPre, -- *****violation here
CLK180 =3D> open,
CLK270 =3D> open,
CLK2X =3D> open,
CLK2X180 =3D> open,
CLK90 =3D> open,
CLKDV =3D> open,
CLKFX =3D> open,
CLKFX180 =3D> open,
DO =3D> open,
DRDY =3D> open,
LOCKED =3D> DLL_LOCKED,
PSDONE =3D> open,
CLKFB =3D> SClk,
CLKIN =3D> SClkIn,
DADDR =3D> "0000000",
DCLK =3D> '0',
DEN =3D> '0',
DI =3D> "0000000000000000",
DWE =3D> '0',
PSCLK =3D> '0',
PSEN =3D> '0',
PSINCDEC =3D> '0',
RST =3D> MasterRst
);
Article: 145681Verictor pisze: > Hi, > > I have a V4 with input clock frequency running at 130MHz. This clock > goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > named as "derived_clock" by Synplify. Now the timing report on the > input 130MHz is fine (positive slack) but the derived_clock doesn't > meet timing. How to contrain that? > > Thanks. Hi, If incoming (external ) clock is used only to drive DCM, you have problem with your design. In different words your logic is too slow. Anyway you can find everything in timing report. I don't know xilinx tools to well but clock coming from DCM should be constrained automatically. Correct me if I'm wrong AdamArticle: 145682
>Also > >http://www.xilinx.com/support/documentation/white_papers/wp272.pdf > Okey I will try it, I only wondering if those papers telling about problems with debouncing and does it refers also to capacity switches ? About case why D in on sensitivity list - I must tell I don't now, I will remove it from there... Thank you for intresting in my stupid case, I will try trick with debounce and will see... Once again thank you for ideas :) Best Regards, Maciek --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145683
Weng, Maybe we are using this patent, maybe not. Just because it is a Xilinx patent does not automatically mean we actually do this now, or ever. AustinArticle: 145684
"Eric Chomko" <pne.chomko@comcast.net> wrote in message
news:badc12c3-cb2b-4ce9-9543-237d60fc22d5@o8g2000vbm.googlegroups.com...
> Has anyone created a copy machine of an old system using an
> FPGA? I
> was wondering if it would be possible to take an entire SWTPC
> 6800 and
> compile the schematics and have it run on an FPGA board.?
> Wouldn't
> even have to be the latest Xylinx product, I suspect.
Absolutely. There a number of them. This guy has done a PDP-4
and PDP-8,
http://homepage.mac.com/dgcx/pdp4x/
http://homepage.mac.com/dgcx/pdp4x/
I am in the process of doing a PDP-1. My background is high
performance computers so it is a high performance design.
Todays FPGAs and CAD allow a much more agressive implementation
than the original designers could afford and with far less
effort. The original PDP-1s sold for about $100K in early
1960s' dollars. Mine will cost only a few hundred dollars to
build.
Those interested in the subject might also be interested in the
simh group,
http://simh.trailing-edge.com/
which does simulators for legacy computers.
Gary
Article: 145685On Wed, 17 Feb 2010 17:55:07 -0600, "de4" <de4@n_o_s_p_a_m.poczta.onet.pl> wrote: >Hello ! > >I have a very big problem. I created a simple procesor and on simulation it >works fine, on step mode it works fine but when it is running on full speed >of clock it got crazy... :( It should execute instruction i order >0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it >executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 or >0.1 or sometimes it is as it should. Sometimes it stops suddenly executing >or executing too much. It is written in VHDL on Spartan 3A. It is too big >to show it here but maybe some experts will be able to tell me what is >going on... I have constraints like this in UCF file : > >NET "Clock" LOC = C10; >NET "Clock" IOSTANDARD = LVCMOS33; >NET "Clock" PERIOD = 62.5ns HIGH 50%; >NET "Reset" LOC = H4; >NET "Reset" IOSTANDARD = LVCMOS33; >NET "TX" LOC = B3; >NET "TX" IOSTANDARD = LVCMOS33; >NET "RX" LOC = A3; >NET "RX" IOSTANDARD = LVCMOS33; > >are there any other constraint useful for me ? Can it be constraint fault ? >Or it must be design problem ? Or something else ? 16Mhz clock is >connected to FPGA. It works OK using step by step mode but on full speed >it's stragne bevahior... I really need help, I trying to solve it for three >days and nothing... > >Thank you all for any answers... > >--------------------------------------- >Posted through http://www.FPGARelated.com Have you tried running at a lower clock rate? This would seem a simple way of determining if it is a per-cycle overall path delay type thing or a setup/hold, race condition etc. due to internal propagation times.Article: 145686
On Feb 18, 11:00=A0am, austin <aus...@xilinx.com> wrote: > Ines, > > What is it about "it does not fit, you used too many BRAMs, please > examine these files to discover your error" that you do not > understand? > > Remember the BRAM blocks are in kilobits, not kilobytes. =A0It is very > easy to exceed the number of BRAMS in a part by simple requiring too > much addressable memory space, > > Additionally, if you are specifying cache for the MicroBlaze core, > that cache will also eat up BRAM blocks, depending on how much cache > you requested (for data and/or instructions). > > Austin There's also a bug in ISE 10.1 that causes overmapping of BRAM if you check "Map slice logic into unused block RAMs". Makes me wonder what part of "unused" the tools don't understand. - GaborArticle: 145687
Gabor, Using BRAM blocks as 'look up tables' for logic is a way to pack more "stuff" into the design, so, yes, the BRAMs are only "unused" until you then use them for this purpose (the English language is probably one of the worst languages for describing technical stuff, except for all the others). That is a fairly arcane use of the BRAM blocks, and it would be interesting to know how often folks do this, AustinArticle: 145688
>Verictor pisze: >> Hi, >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> named as "derived_clock" by Synplify. Now the timing report on the >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> meet timing. How to contrain that? >> >> Thanks. > You havent added any clock buffers (BUFG) on the output of the DCM. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145689
In article <lMmdneY0IJR65-DWnZ2dnUVZ_uKdnZ2d@supernews.com>, Abby Brown <abbybrown@charter.net> wrote: > >"Eric Chomko" <pne.chomko@comcast.net> wrote in message >news:badc12c3-cb2b-4ce9-9543-237d60fc22d5@o8g2000vbm.googlegroups.com... >> Has anyone created a copy machine of an old system using an >> FPGA? I >> was wondering if it would be possible to take an entire SWTPC >> 6800 and >> compile the schematics and have it run on an FPGA board.? >> Wouldn't >> even have to be the latest Xylinx product, I suspect. > >Absolutely. There a number of them. This guy has done a PDP-4 >and PDP-8, > > http://homepage.mac.com/dgcx/pdp4x/ > > http://homepage.mac.com/dgcx/pdp4x/ > >I am in the process of doing a PDP-1. My background is high >performance computers so it is a high performance design. Do you pipeline it? Any issues? >Todays FPGAs and CAD allow a much more agressive implementation >than the original designers could afford and with far less >effort. The original PDP-1s sold for about $100K in early >1960s' dollars. Mine will cost only a few hundred dollars to >build. A PDP1 is cool. Please tell when you have a production run. If I have the money, I may shell out for a kit suitable for an economist to assemble. But a PDP6, or a '10 with a modern performance design would be ultracool. >Those interested in the subject might also be interested in the >simh group, > > http://simh.trailing-edge.com/ > >which does simulators for legacy computers. I have used several of these emulators for years. Thank you for your excellent work. -- mrrArticle: 145690
On Feb 18, 11:10=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Feb 17, 7:51=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Feb 17, 8:05 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Feb 17, 4:29 pm, rickman <gnu...@gmail.com> wrote: > > > > Fight fire with fire! =A0The two reports below show that both the > > > > missing else and the missing assignment (which is also missing in t= he > > > > missing else case) produce latches. > > > > > @W: CL117 :"C:\arius\boards\tdc_upgrade\tests\latchsynthtest.vhd": > > > > 57:4:57:7|Latch generated from process for signal Latch, probably > > > > caused by a missing assignment in an if or case stmt > > > > @W: CL117 :"C:\arius\boards\tdc_upgrade\tests\latchsynthtest.vhd": > > > > 40:4:40:7|Latch generated from process for signal Comb, probably > > > > caused by a missing assignment in an if or case stmt > > > > > library ieee; > > > > use ieee.std_logic_1164.all; > > > > use ieee.numeric_std.all; > > > > > entity LatchSynthTest is > > > > =A0 port( > > > > =A0 =A0 =A0 =A0 =A0 CLK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in = =A0 =A0std_logic ; > > > > =A0 =A0 =A0 =A0 =A0 RESET =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0 = =A0std_logic ; > > > > =A0 =A0 =A0 =A0 =A0 C01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in = =A0 =A0std_logic ; > > > > =A0 =A0 =A0 =A0 =A0 C02 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in = =A0 =A0std_logic ; > > > > =A0 =A0 =A0 =A0 =A0 LatchOutput =A0 : out =A0 std_logic ; > > > > =A0 =A0 =A0 =A0 =A0 CombOutput =A0 =A0: out =A0 std_logic > > > > =A0 =A0 =A0 =A0 =A0 ); > > > > end LatchSynthTest ; > > > > > architecture behavior of LatchSynthTest is > > > > =A0 SIGNAL Latch =A0 =A0 =A0 =A0 =A0: std_logic; > > > > =A0 SIGNAL Comb =A0 =A0 =A0 =A0 =A0 : std_logic; > > > > =A0 SIGNAL LatchReg =A0 =A0 =A0 : std_logic; > > > > =A0 SIGNAL CombReg =A0 =A0 =A0 =A0: std_logic; > > > > > begin > > > > > =A0 CombOutput =A0 =A0<=3D CombReg; > > > > =A0 LatchOutput =A0 <=3D LatchReg; > > > > > =A0 Process_1 : process(RESET, CLK) > > > > =A0 begin > > > > =A0 =A0 if (RESET =3D '1') then > > > > =A0 =A0 =A0 LatchReg =A0<=3D '0'; > > > > =A0 =A0 =A0 CombReg =A0 <=3D '0'; > > > > =A0 =A0 elsif (rising_edge(CLK)) then > > > > =A0 =A0 =A0 LatchReg =A0<=3D Latch; > > > > =A0 =A0 =A0 CombReg =A0 <=3D Comb; > > > > =A0 =A0 end if; > > > > =A0 end process; > > > > > =A0 CombProc : process(CombReg, C01, C02) > > > > =A0 begin > > > > =A0 =A0 case CombReg is > > > > =A0 =A0 =A0 when '0' =3D> > > > > =A0 =A0 =A0 =A0 if (C01 =3D '1') then > > > > =A0 =A0 =A0 =A0 =A0 Comb <=3D '0'; > > > > =A0 =A0 =A0 =A0 elsif (C02 =3D '1') then > > > > =A0 =A0 =A0 =A0 =A0 Comb <=3D '1'; > > > > =A0 =A0 =A0 =A0 else > > > > =A0 =A0 =A0 =A0 =A0 -- Here an assignment statement is missing, but= it doesn't > > > > =A0 =A0 =A0 =A0 =A0 -- generate latch. =A0It is treated as a null s= tatement. - > > > > Weng > > > > =A0 =A0 =A0 =A0 end if; > > > > =A0 =A0 =A0 when others =3D> > > > > =A0 =A0 =A0 =A0 Comb <=3D '1'; > > > > =A0 =A0 end case; > > > > =A0 end process; > > > > > =A0 LatchProc : process(LatchReg, C01, C02) > > > > =A0 begin > > > > =A0 =A0 case LatchReg is > > > > =A0 =A0 =A0 when '0' =3D> > > > > =A0 =A0 =A0 =A0 if C01 =3D '1' then > > > > =A0 =A0 =A0 =A0 =A0 Latch <=3D '0'; > > > > =A0 =A0 =A0 =A0 elsif C02 =3D '1' then > > > > =A0 =A0 =A0 =A0 =A0 Latch <=3D '1'; > > > > =A0 =A0 =A0 =A0 =A0 -- Here the else is missing, and it does > > > > =A0 =A0 =A0 =A0 =A0 -- generate latch. =A0It is treated as a null s= tatement. > > > > =A0 =A0 =A0 =A0 end if; > > > > =A0 =A0 =A0 when others =3D> > > > > =A0 =A0 =A0 =A0 Latch <=3D '1'; > > > > =A0 =A0 end case; > > > > =A0 end process; > > > > > end behavior; > > > > Hi, > > > Thank you, Andy, Rick and everyone, I am wrong in the second point: > > > missing "else" or missing an assignment statement. > > > > But my first point is how to generate a latch for a compiler. Rick, > > > can you see the floor plan to show how the latch is generated: for th= e > > > state only or for full states? > > > > Weng > > > I'm not clear what you mean by "how". =A0Are you asking about the detai= l > > of how it is implemented in the FPGA? =A0In the Lattice part they used = a > > FF as a latch. =A0A register is between the latch and the output. =A0Th= ey > > drive the latch oddly driving both the clock and the async reset > > inputs with logic, but then if you look at the code what would you > > think is the clock? =A0I don't see why they did it the way they did, bu= t > > it works correctly according to the VHDL. =A0With only four inputs I > > would expect they could have just used a single LUT4 and the latch > > with the clock always enabled. > > > Din =3D=3D '1' > > Latch Enable =3D=3D CombReg + C02 > > Async Clear =A0=3D=3D ~CombReg * C01 > > > Is this what you are asking? > > > Rick > > Rick, > Yes, that is what I want. > > Could you please send the code and a window screen frame using > Window's Paint so that I can see the full picture. > > Thank you. > > Weng I'm not clear on what you want. I posted the full code a couple of posts back. What is it that you want a screen shot of? The text I quoted was from the Synthesis report. If you want an image of the chip editor, the latch only shows in the logic block editor dialog box. It is just a check box on a schematic of the functional elements in the logic block. Is that of any value to you? RickArticle: 145691
"Morten Reistad" <first@last.name> wrote in message news:emm057-j0a.ln1@laptop.reistad.name... > In article <lMmdneY0IJR65-DWnZ2dnUVZ_uKdnZ2d@supernews.com>, > Abby Brown <abbybrown@charter.net> wrote: >> >>"Eric Chomko" <pne.chomko@comcast.net> wrote in message >>news:badc12c3-cb2b-4ce9-9543-237d60fc22d5@o8g2000vbm.googlegroups.com... >>> Has anyone created a copy machine of an old system using an >>> FPGA? I ... >>I am in the process of doing a PDP-1. My background is high >>performance computers so it is a high performance design. > > Do you pipeline it? Any issues? The current design is not pipelined. Ultimately, I expect it will be pipelined and latched. > A PDP1 is cool. Please tell when you have a production run. If > I have the money, I may shell out for a kit suitable for an > economist to assemble. I can make the board and chip design available. > But a PDP6, or a '10 with a modern performance design would > be ultracool. That would be a group effort. I have an emotional attachment to PDP-1s. I spent many happy hours playing Spacewar on a PDP-1 and learned to program on it as well. GaryArticle: 145692
On Feb 18, 12:51=A0pm, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk> wrote: > >Verictor pisze: > >> Hi, > > >> I have a V4 with input clock frequency running at 130MHz. This clock > >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > >> named as "derived_clock" by Synplify. Now the timing report on the > >> input 130MHz is fine (positive slack) but the derived_clock doesn't > >> meet timing. How to contrain that? > > >> Thanks. > > You havent added any clock buffers (BUFG) on the output of the DCM. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com No, I do have inserted IBUFG to input clock and BUFG to the output of the DCM. Just not shown on my post.Article: 145693
On Feb 18, 9:28=A0am, austin <aus...@xilinx.com> wrote: > Weng, > > Maybe we are using this patent, maybe not. > > Just because it is a Xilinx patent does not automatically mean we > actually do this now, or ever. > > Austin Hi Austin, Whether or not Xilinx uses the technique doesn't matter to me, I am not working for Altera or any other FPGA companies, what matters to me is the technique itself behind the patent. Those are techniques you cannot learn from any textbooks. Thank Xilinx, I learn a lot by reading Xilinx's patents. WengArticle: 145694
You should only need to specify the clock into the DCM in the Synplify constraint file. If your design is not meeting timing then you need to look in the Synplify report and find the problem. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145695
On Feb 18, 7:48=A0pm, austin <aus...@xilinx.com> wrote: > Gabor, > > Using BRAM blocks as 'look up tables' for logic is a way to pack more > "stuff" into the design, so, yes, the BRAMs are only "unused" until > you then use them for this purpose (the English language is probably > one of the worst languages for describing technical stuff, except for > all the others). > > That is a fairly arcane use of the BRAM blocks, and it would be > interesting to know how often folks do this, > > Austin Hi, Thank you (Austin and Gabor) for the answers. But is this error caused by the fact that the application software is big enough? I dont' think so cause the soft application is very simple, it just light the 8 LEDs. Also in the MHS file I put 16k for DLMB and 16k for the ILMB too! So I couldn'tt understand where the problem lies: in the design in hard or soft implementation!! I will be thankfull if you give me some help!! Best Regards, InesArticle: 145696
Hi all, I am a budding FPGA designer and I am in the process of designing first system. Until now I have partitioned my system into various entities, each entity implementing a small part of the system. It is also easier for implementation. However I have found myself in routing a lot of signals from one entity to another which increases complexity in a way. The other option is implement the system in a single entity and a number of process. This would simplify matters because I would not need to route lots signals between one entity and another. The disadvantage is a lack of clarity. What is the best way for implementation? Any ideas and suggestions would be welcome. Thanks very much, Regards, JosephArticle: 145697
>Hi all, > >I am a budding FPGA designer and I am in the process of designing >first system. Until now I have partitioned my system into various >entities, each entity implementing a small part of the system. It is >also easier for implementation. However I have found myself in routing >a lot of signals from one entity to another which increases complexity >in a way. > >The other option is implement the system in a single entity and a >number of process. This would simplify matters because I would not >need to route lots signals between one entity and another. The >disadvantage is a lack of clarity. > >What is the best way for implementation? Any ideas and suggestions >would be welcome. > >Thanks very much, > >Regards, > >Joseph > Part of the "art" of system design is structuring and organizing the hierarchy in a near-optimal way. Don't expect to get it right the first time that you do it. Do aspire to get better with subsequent projects. HTH! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145698
On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehuang@gmail.com> wrote: >On Feb 18, 12:51 pm, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk> >wrote: >> >Verictor pisze: >> >> Hi, >> >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> >> named as "derived_clock" by Synplify. Now the timing report on the >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> >> meet timing. How to contrain that? >> >> >> Thanks. >> >> You havent added any clock buffers (BUFG) on the output of the DCM. >> >> Jon >> >> --------------------------------------- >> Posted throughhttp://www.FPGARelated.com > >No, I do have inserted IBUFG to input clock and BUFG to the output of >the DCM. Just not shown on my post. Then we have to guess that the BUFG has SClkPre as input and SClk as output, since SClk is taken to ClkFB (feedback) on the DCM. Then SClk should be correctly aligned with the DCM input clock, which means there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal). Is that what you are observing? - BrianArticle: 145699
> >NET "Clock" PERIOD =3D 62.5ns HIGH 50%; > Have you tried running at a =A0lower clock rate? Just to be devil's advocate, it still seems as if timing/skew is not met, although you have indicated otherwise (1 - PERIOD=3D62.5ns, 2 - no timing errors). Can you configure the STA tool to list the longest routes (even though they are passing), just to get an idea that it is being measured for the 16 MHz? In other words, prove that design is being timed to 16 MHz.
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