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On 22 Feb, 16:45, austin <aus...@xilinx.com> wrote: > Dek, > > It is a warning: =A0you do not necessarily have to fix it. > > The tools are telling you that a net to a constant (1=3Dpower, or > 0=3Dground) had its timing constraint removed (ignored). > > That is a perfectly OK thing to do. > > It is up to you to read each warning, and check out what it means. > > This one is easy, let it go. > > Austin Hi Austin Thanks for the reply; the point is that I have a project that uses some block ram; In functional simulation everything works fine, when I do synthesys and place and route I got no errors, no timing related problems, and just 2 kind of warnings: Xst:2211: ... line 130: Instantiating black box module <ram_128> ( see http://groups.google.it/group/comp.lang.vhdl/browse_thread/thread/cf7= 02b52f28c2674/702ad29181e18171#702ad29181e18171 ) and Pack:231 - trimming timing constraints from pin as described above If I try to do a post layout simulation of this design with Modelsim; I got this warning: # ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected :=3D 0.195 ns; Observed :=3D 0.006 ns; At : 191.527 ns # Time: 191527 ps Iteration: 1 Instance: /newdaedalus_tb/top/ control_cnt_0 and the design does not behave like in functional analysis. I also implemented the bitfile on real hardware but it doesn't work. That's why I was asking about that warning, because I really can't get where the problem could be... I'm using the block ram @ 40 MHz, but it shouldn't be a problem, right? Thanks Bye DekArticle: 145776
Thomas Stanka <usenet_nospam_valid@stanka-web.de> writes: > For normal FPGA Design Windows is common, as some (backend-) FPGA > tools are either Windows only or show better performance under > Windows. Which tools do you have in mind here? > For general digital design (and especially frontend of code entry and > simulation) professionals use often Linux/Solaris when it comes to > complex and large designs. Especially if you're using Synopsys tools. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145777
On Feb 19, 4:22=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...@gmail.com> w= rote: > >On Feb 18, 12:51=A0pm, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk> > >wrote: > >> >Verictor pisze: > >> >> Hi, > > >> >> I have a V4 with input clock frequency running at 130MHz. This cloc= k > >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > >> >> named as "derived_clock" by Synplify. Now the timing report on the > >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't > >> >> meet timing. How to contrain that? > > >> >> Thanks. > > >> You havent added any clock buffers (BUFG) on the output of the DCM. > > >> Jon =A0 =A0 =A0 =A0 > > >> --------------------------------------- =A0 =A0 =A0 =A0 > >> Posted throughhttp://www.FPGARelated.com > > >No, I do have inserted IBUFG to input clock and BUFG to the output of > >the DCM. Just not shown on my post. > > Then we have to guess that the BUFG has SClkPre as input and SClk as outp= ut, > since SClk is taken to ClkFB (feedback) on the DCM. > > Then SClk should be correctly aligned with the DCM input clock, which mea= ns > there will be several ns skew (=3D the BUFG delay) on SClkPre (the DCM0 s= ignal). > Is that what you are observing? > > - Brian- Hide quoted text - > > - Show quoted text - Brian, Your guess of BUFG is exactly right. Also yes, SClk should be aligned with CLKIN, as you pointed out. When you said "observing", I think you mean post-layout simulation? I haven't done that. But I think the alignment should be ok. Thanks,Article: 145778
On Feb 14, 9:12=A0am, rickman <gnu...@gmail.com> wrote: > On Feb 8, 7:51=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > > > > Hello serkan, > > > The latest version of the TimingAnalyzer now reads VCD files and > > automatically converts and saves it as a timing diagram. =A0This is > > useful for documenting simulation results for specifications, reviews, > > and presentations. > > >http://www.timing-diagrams.com/dokuwiki/doku.php?id=3Ddocs:vcd_files > > > Dan > > > On Feb 5, 5:29=A0pm, "M.Randelzhofer" <techsel...@gmx.de> wrote: > > > > "Serkan" <ok...@su.sabanciuniv.edu> schrieb im Newsbeitragnews:382d62= 81-244f-48d7-a0ae-ff76e69316db@p24g2000yqm.googlegroups.com... > > > > > Any suggestions for a free waveform drawing tool? > > > > > inkscape or word alike tools take too much time for edition. > > > > some free tools does not let more than 10 clock cycles > > > > some free tools does not let more than 5 or 6 signals > > > > > kind regards > > > > serkan > > > >http://www.timing-diagrams.com/doku.php > > > > MIKE > > I am having trouble figuring out other aspects of using this program. > I noticed that the author's web site doesn't have a forum for users, > so I've started a Yahoo group for users to discuss this program and > hopefully provide support to one another. > > http://tech.groups.yahoo.com/group/TimingAnalyzer/ > > I am trying to draw a diagram to help me visualize the advantages of > replacing registers with latches in designs with tight timing. =A0It > seems like an uphill struggle given that I can't tell if the things I > try don't work because that isn't the way the tool works or if I'm > just not using it right. =A0I'm not finding this tool to be very > intuitive. =A0But then maybe I'm just not thinking along the right > vein. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I was away for week and didn't see your response. Yes, the program is now freeware and I'm the only developer at this time. I work full time as a design engineer so I don't get a lot of time to develop the program. As a result, progress is slow but I'm always working on new features and bug fixes. I'm focusing the next few releases on bug fixes and improvements and better documentation.. I did at one time have a user forum, so I will add that back again. There is also a new code repository started for python scripts at: http://code.google.com/p/timing-analyzer-plugins/ Printing will be supported, but for now, you have to save the diagram as an image and print the image. I realize the program is not as polished as some of the commercial quality alternatives, but that will change in time. If you have any questions, just let me know, my email is: timinganalyzer@gmail.com Thanks, DanArticle: 145779
On Feb 22, 5:10=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > In comp.arch.fpga Eric Chomko <pne.cho...@comcast.net> wrote: > (snip) > > > I'm pretty sure ALGOL and PL/I are far worse WRT to stack > > bloat than is C. > > ALGOL, PL/I, and C pretty much require local variables to > be automatic. =A0(PL/I procedures without the RECURSIVE attribute > might get away with static allocation.) > > Fortran up through Fortran 77 allowed local variables to be > statically allocated. =A0Without the RECURSIVE attribute, it > probably still does. > > Other than passing of arguments, it depends on how you allocate > your variables. =A0PL/I has the STATIC attribute which will keep > variables off the stack, as does C. =A0Be careful with recursion, though. > For ALGOL, maybe you need internal procedures using variables from > outside, and to minimize actual local variables. =A0PL/I can easily > generate temporary variables, including arrays. The thing about ALGOL parameter passing was that there was four ways to do it according to the ALGOL 60 spec. As I recall from my Comp Sci days at U of MD, ALGOL used call by value, call by reference, call by value/result, and call by name. I'll tell you I still didn't understand why more than call by value and call by reference are needed. Anyway... Speaking of ALGOL parameter passing, what's a "thunk"? Anyone get that and they get a gold star for the day. Suffice to say, my prof back in the day (Dr. John Gannon, may he RIP), was the sort of guy that knew everything about everything thing when it came to computer language translation, even the trivia! EricArticle: 145780
On Feb 22, 5:53=A0pm, Peter Flass <Peter_Fl...@Yahoo.com> wrote: > Eric Chomko wrote: > > > I'm pretty sure ALGOL and PL/I are far worse WRT to stack bloat than > > is C. > > PL/I can be, but doesn't have to be. =A0If the arguments of a procedure > match the parameters, only the argument address (and possibly a > descriptor address for strings structures, and arrays) is passed. =A0If > the argument doesn't match, the compiler nicely copies it to a "dummy > argument" that does. =A0As usual, the programmer needs to have some idea > what's going on. But an ALGOL "activation record" (stack frame) had a lot more than that. As I recall, they copied a lot more just pointers and parameter values.Article: 145781
On Feb 23, 7:39=A0am, "(see below)" <yaldni...@blueyonder.co.uk> wrote: > On 23/02/2010 09:39, in article > e59b10e9-83f7-4fb6-8ecf-a9d8fd13f...@v25g2000yqk.googlegroups.com, > > "Quadibloc" <jsav...@ecn.ab.ca> wrote: > > On Feb 22, 12:27 pm, rickman <gnu...@gmail.com> wrote: > > >> A hardware stack for C is a bit of a problem. C tends to need a > >> rather large stack because of the stack frames used. > > > What could happen, though, on a computer with a small hardware stack > > is that the compiler would use a software stack for things like > > subroutine calls (which must always work, no matter how deeply they > > are nested) and use the hardware stack for things it can control - > > such as the layers of parentheses in assignment statements. > > > That, for example, is presumably how one would go about writing a C > > compiler for a KDF 9. > > The way the Algol 60 compilers on KDF9 worked is well documented. > The Whetstone compiler generated its own Algol-oriented byte code, which = is > very similar to the slightly later B6500 machine code. > > The Kidsgrove and EGDON compilers generated KDF9 machine code. > Managing the hardware stacks difficult, as it would have needed global da= ta > flow and control flow analyses. The Kidsgrove compiler made a basic but n= ot > very successful attempt at this. > > See <http://sw.ccs.bcs.org/KidsgroveAlgol/INDEX.HTM>. > I am more familiar with the Norway University version of ALGOL on a UNIVAC 1100 series machine. NU-ALGOL it was called. I sold a book called "ALGOL Implementation" based upon the Whetsone compiler on eBay about a decade ago. Got a pretty good price for it as well as I recall.Article: 145782
On 23/02/2010 17:48, in article 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric Chomko" <pne.chomko@comcast.net> wrote: > The thing about ALGOL parameter passing was that there was four ways > to do it according to the ALGOL 60 spec. No. Algol 60 had value parameters and name parameters only. A name parameter was actually an anonymous function, re-evaluated at every use within the procedure; or it could be a pair of such functions, one member of the pair delivering an L value and the other one an R value. These functions had to be generated by the compiler from the actual parameter expression expressions. The above refers to parameters of storable types; of course there were other kinds of parameter such as switches, strings, procedures and (named) functions to which the value/name distinction did not apply. > As I recall from my Comp Sci > days at U of MD, ALGOL used call by value, call by reference, call by > value/result, and call by name. I'll tell you I still didn't > understand why more than call by value and call by reference are > needed. Anyway... Algol W had value, result, value-result and name modes; but no reference parameters; plus procedures and (named) functions. Algol 68 arguably had only storable value parameters, but the value passed could be of a reference type (this was quite well handled in Algol 68, but soon degenerated into C's semantic sludge). > Speaking of ALGOL parameter passing, what's a "thunk"? A thunk is the anonymous function (pair) described above. -- Bill Findlay <surname><forename> chez blueyonder.co.ukArticle: 145783
On 23/02/2010 17:52, in article 3ec03225-3a0f-4bcd-9db1-51201d1b3d53@w12g2000vbj.googlegroups.com, "Eric Chomko" <pne.chomko@comcast.net> wrote: > But an ALGOL "activation record" (stack frame) had a lot more than > that. As I recall, they copied a lot more just pointers and parameter > values. Just the usual red tape: return address, frame pointer of caller; and either a static pointer or some housekeeping for 'display' registers (if used) to access non-locals. But bear in mind that in decent languages arrays are storable values, so a value array parameter gets copied in toto, unlike C. -- Bill Findlay <surname><forename> chez blueyonder.co.ukArticle: 145784
On 23/02/2010 17:57, in article 57442c25-2046-4193-879b-3ff71c0f1433@z25g2000vbb.googlegroups.com, "Eric Chomko" <pne.chomko@comcast.net> wrote: > On Feb 23, 7:39 am, "(see below)" <yaldni...@blueyonder.co.uk> wrote: >> On 23/02/2010 09:39, in article >> e59b10e9-83f7-4fb6-8ecf-a9d8fd13f...@v25g2000yqk.googlegroups.com, >> >> "Quadibloc" <jsav...@ecn.ab.ca> wrote: >>> On Feb 22, 12:27 pm, rickman <gnu...@gmail.com> wrote: >> >>>> A hardware stack for C is a bit of a problem. C tends to need a >>>> rather large stack because of the stack frames used. >> >>> What could happen, though, on a computer with a small hardware stack >>> is that the compiler would use a software stack for things like >>> subroutine calls (which must always work, no matter how deeply they >>> are nested) and use the hardware stack for things it can control - >>> such as the layers of parentheses in assignment statements. >> >>> That, for example, is presumably how one would go about writing a C >>> compiler for a KDF 9. >> >> The way the Algol 60 compilers on KDF9 worked is well documented. >> The Whetstone compiler generated its own Algol-oriented byte code, which is >> very similar to the slightly later B6500 machine code. >> >> The Kidsgrove and EGDON compilers generated KDF9 machine code. >> Managing the hardware stacks difficult, as it would have needed global data >> flow and control flow analyses. The Kidsgrove compiler made a basic but not >> very successful attempt at this. >> >> See <http://sw.ccs.bcs.org/KidsgroveAlgol/INDEX.HTM>. >> > > I am more familiar with the Norway University version of ALGOL on a > UNIVAC 1100 series machine. NU-ALGOL it was called. > > I sold a book called "ALGOL Implementation" based upon the Whetsone > compiler on eBay about a decade ago. Got a pretty good price for it as > well as I recall. That was Randell & Russell's classic documentation of KDF9 Whetstone Algol. It was used as a manual for the implementation of the Whetstone dialect of Algol 60 on many other architectures, including the EE DEUCE, the Ferranti Pegasus, the NPL ACE, the EE KDF6, the Soviet Minsk range, the EE System 4/50, the IBM System 360/25, the Phillips PRS8000, and the Indian ECIL TDC-316. There is a lot more information about Algol 60 and the KDF9 implementations at <http://sw.ccs.bcs.org/CCs/KDF9/Wichmann/index.html>. -- Bill Findlay <surname><forename> chez blueyonder.co.ukArticle: 145785
I have just constructed a bootloader for a Xilinx FPGA. I am trying to get my main application converted to MCS using the flow described in XAPP482 (run data2mem and then xapp482.exe). The issue I'm having is that data2mem seems to ignore .rodata and .data sections in the .elf file, leaving me with uninitialized memory after a boot. Is there a way to get data2mem to include these sections or is there another way to read the ELF file and get it combined with an MCS file for burning in the PROM that includes these sections? Thanks, Steve --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145786
>I'm FPGA beginner and can anybody tell me what to do in steps to create >those .bmm files and .mem files. I was searching it for few hours and I >don't catch this... If you are trying to initialize with a software project, you can use the BRAM Init function in the EDK tools. This will invoke data2mem in the background, turn you application into a .MEM file and then combine this with you .BIT file to produce a new .BIT file. If you are initializing with something different, you will probably need to invoke data2mem yourself. There is a guide on data2mem that explains how to use it in more detail here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/data2mem.pdf or you could invoke the BRAM Init took in EDK and watch how it works and mimic what it is doing with your data. Steve --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145787
On Tue, 23 Feb 2010 06:53:08 -0800 (PST), Verictor <stehuang@gmail.com> wrote: >On Feb 19, 4:22 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...@gmail.com> wrote: >> >On Feb 18, 12:51 pm, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk> >> >wrote: >> >> >Verictor pisze: >> >> >> Hi, >> >> >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> >> >> named as "derived_clock" by Synplify. Now the timing report on the >> >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> >> >> meet timing. How to contrain that? >> >> >> You havent added any clock buffers (BUFG) on the output of the DCM. >> >No, I do have inserted IBUFG to input clock and BUFG to the output of >> >the DCM. Just not shown on my post. >> Then SClk should be correctly aligned with the DCM input clock, which means >> there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal). >> Is that what you are observing? >Your guess of BUFG is exactly right. Also yes, SClk should be aligned >with CLKIN, as you pointed out. When you said "observing", I think you >mean post-layout simulation? I haven't done that. But I think the >alignment should be ok. I actually meant "observing" because you observed in your original query, you reported the "derived clock" DCM0 signal (skewed as above) didn't meet timing. Since the skew is expected, the question is, what exactly doesn't meet timing? If there is any logic clocked off DCM0 it will probably not meet timing; but there shouldn't be any. DCM0 should only connect to the BUFG and nothing else. - BrianArticle: 145788
(see below) wrote: > On 23/02/2010 17:48, in article > 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric > Chomko" <pne.chomko@comcast.net> wrote: > > [snip...] [snip...] [snip...] > >> Speaking of ALGOL parameter passing, what's a "thunk"? > > A thunk is the anonymous function (pair) described above. > A "thunk" was a method of implementing "call by name". -- +----------------------------------------+ | Charles and Francis Richmond | | | | plano dot net at aquaporin4 dot com | +----------------------------------------+Article: 145789
Charles Richmond wrote: > (see below) wrote: >> On 23/02/2010 17:48, in article >> 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric >> Chomko" <pne.chomko@comcast.net> wrote: >> >> [snip...] [snip...] [snip...] >> >>> Speaking of ALGOL parameter passing, what's a "thunk"? >> >> A thunk is the anonymous function (pair) described above. >> > > A "thunk" was a method of implementing "call by name". > http://www.jargon.net/jargonfile/t/thunk.html -- +----------------------------------------+ | Charles and Francis Richmond | | | | plano dot net at aquaporin4 dot com | +----------------------------------------+Article: 145790
On 23/02/2010 22:35, in article hm1l73$q4q$1@news.eternal-september.org, "Charles Richmond" <frizzle@tx.rr.com> wrote: > (see below) wrote: >> On 23/02/2010 17:48, in article >> 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric >> Chomko" <pne.chomko@comcast.net> wrote: >> >> [snip...] [snip...] [snip...] >> >>> Speaking of ALGOL parameter passing, what's a "thunk"? >> >> A thunk is the anonymous function (pair) described above. >> > > A "thunk" was a method of implementing "call by name". Strangely, enough, that is precisely what I said. -- Bill Findlay <surname><forename> chez blueyonder.co.ukArticle: 145791
"n5ac" <n5ac@n5ac.com> writes: > Is there a way to get data2mem to include these sections or is there > another way to read the ELF file and get it combined with an MCS file for > burning in the PROM that includes these sections? It's been a while since I used the Xilinx tools, but in general you should be able to modify the linker script to put your .rodata into .text or .css (or whatever data2mem will include). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145792
In article <C7AA0F62.137643%yaldnif.w@blueyonder.co.uk>, (see below) <yaldnif.w@blueyonder.co.uk> wrote: >On 23/02/2010 22:35, in article hm1l73$q4q$1@news.eternal-september.org, >"Charles Richmond" <frizzle@tx.rr.com> wrote: > >> (see below) wrote: >>> On 23/02/2010 17:48, in article >>> 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric >>> Chomko" <pne.chomko@comcast.net> wrote: >>> >>> [snip...] [snip...] [snip...] >>> >>>> Speaking of ALGOL parameter passing, what's a "thunk"? >>> >>> A thunk is the anonymous function (pair) described above. >>> >> >> A "thunk" was a method of implementing "call by name". > >Strangely, enough, that is precisely what I said. Or rather, to be pedantic, "what you had said, precisely".Article: 145793
In comp.arch.fpga Charles Richmond <frizzle@tx.rr.com> wrote: > (see below) wrote: >> On 23/02/2010 17:48, in article >> 4178548f-5618-49dd-ad72-008bdb53ed3b@z25g2000vbb.googlegroups.com, "Eric >> Chomko" <pne.chomko@comcast.net> wrote: >> [snip...] [snip...] [snip...] >>> Speaking of ALGOL parameter passing, what's a "thunk"? >> A thunk is the anonymous function (pair) described above. > A "thunk" was a method of implementing "call by name". Much of the discussion about ALGOL, including this, is in the past tense. As ALGOL60 hasn't changed recently, and the compilers still exist, even if new ones aren't being written, it seems to me that present tense is fine. A "thunk" is a method of implementing "call by name". More to the hardware side, an archetecture still exists even if no implementations of it exist. (Though in most cases at least one still does.) The PDP8 still IS a 12 bit machine, even if you implement it in an FPGA. -- glen -- glenArticle: 145794
On Feb 23, 10:56=A0am, timinganalyzer <timinganaly...@gmail.com> wrote: > On Feb 14, 9:12=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Feb 8, 7:51=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > Hello serkan, > > > > The latest version of the TimingAnalyzer now reads VCD files and > > > automatically converts and saves it as a timing diagram. =A0This is > > > useful for documenting simulation results for specifications, reviews= , > > > and presentations. > > > >http://www.timing-diagrams.com/dokuwiki/doku.php?id=3Ddocs:vcd_files > > > > Dan > > > > On Feb 5, 5:29=A0pm, "M.Randelzhofer" <techsel...@gmx.de> wrote: > > > > > "Serkan" <ok...@su.sabanciuniv.edu> schrieb im Newsbeitragnews:382d= 6281-244f-48d7-a0ae-ff76e69316db@p24g2000yqm.googlegroups.com... > > > > > > Any suggestions for a free waveform drawing tool? > > > > > > inkscape or word alike tools take too much time for edition. > > > > > some free tools does not let more than 10 clock cycles > > > > > some free tools does not let more than 5 or 6 signals > > > > > > kind regards > > > > > serkan > > > > >http://www.timing-diagrams.com/doku.php > > > > > MIKE > > > I am having trouble figuring out other aspects of using this program. > > I noticed that the author's web site doesn't have a forum for users, > > so I've started a Yahoo group for users to discuss this program and > > hopefully provide support to one another. > > >http://tech.groups.yahoo.com/group/TimingAnalyzer/ > > > I am trying to draw a diagram to help me visualize the advantages of > > replacing registers with latches in designs with tight timing. =A0It > > seems like an uphill struggle given that I can't tell if the things I > > try don't work because that isn't the way the tool works or if I'm > > just not using it right. =A0I'm not finding this tool to be very > > intuitive. =A0But then maybe I'm just not thinking along the right > > vein. > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > > I was away for week and didn't see your response. =A0Yes, =A0the program > is now freeware and I'm the only developer at this time. =A0I work full > time as a design engineer so I don't get a lot of time to develop the > program. =A0As a result, =A0progress is slow but I'm always working on ne= w > features and bug fixes. =A0I'm focusing the next few releases on bug > fixes and improvements and better documentation.. =A0I did at one time > have a user forum, so I will add that back again. =A0There is also a new > code repository started for python scripts at: > > http://code.google.com/p/timing-analyzer-plugins/ > > Printing will be supported, =A0but for now, you have to save the diagram > as an image and print the image. =A0 I realize the program is not as > polished as some of the commercial quality alternatives, but that will > change in time. > > If you have any questions, =A0just let me know, my email is: > > timinganaly...@gmail.com > > Thanks, Dan Hi Rick, I added 3 new user forums on the website. GUI HELP, Script HELP, and New Features and Improvement Request. www.timing-diagrams.com/forums/index.php -DanArticle: 145795
What is the syntax of this below constraint? I am using xilinx 11.4, spartan 6, and VHDL I have a signal say "a" that goes to 2 different "obufds". The delay between this "a" signal to the pins/pads are 4.8 ns and 2.8ns. Can I have a constraint that these 4,8 and 2,8 ns delays are smaller like 1 ns and close to each other. Extra information is below if needed. ============================= input component comp "a", site "SLICE_X1Y61", type = SLICEX ============================= ============================= output component 1 comp "a_p_1", site "B16", bonded type = IOBM, pad name = PAD65, pin name = B16 ============================= ============================= output component 2 comp "a_p_2", site "B6", bonded type = IOBM, pad name = PAD15, pin name = B6 =============================Article: 145796
Ok I guess I found the solution. I need to create 2 a signals and use
the syntax below.
By the way 2.160ns is the minumum delay for spartan6slx16 or I am
doing something wrong.
NET "a_1" MAXDELAY = 2 ns;
NET "a_2" MAXDELAY = 2 ns;
==========================================================
Now I have a smaller question: How can I have both a_1 and a_2 in my
design.
xilinx xst eliminates one of these and I have a problem with keep
signal.
a_b_r_process : process (reset_n, clk_50mhz)
begin
if (reset_n = '0') then
a_1 <= '0';
a_2 <= '0';
elsif (clk_48mhz'event and clk_48mhz = '0') then
a_1 <= a;
a_2 <= a;
end if;
end process;
best regards
Serkan
Article: 145797I found the solution on the forums Please ignore the post. serkanArticle: 145798
glen herrmannsfeldt wrote: > > More to the hardware side, an archetecture still exists even > if no implementations of it exist. (Though in most cases at > least one still does.) The PDP8 still IS a 12 bit machine, > even if you implement it in an FPGA. > Glad to see I'm not the only one who puzzles over the correct tense;-) I tend to use past tense for something I don't think too much of, and present tense for stuff IO like.Article: 145799
>> Is there a way to get data2mem to include these sections or is there >> another way to read the ELF file and get it combined with an MCS file for >> burning in the PROM that includes these sections? > >It's been a while since I used the Xilinx tools, but in general you >should be able to modify the linker script to put your .rodata into >.text or .css (or whatever data2mem will include). > >Petter Petter -- not sure why I didn't think of this! I had been working with the linker script but it didn't occur to me to place everything in .text. This did fix the problem. Unfortunately I did have to add the .bss section which is very large because of the structures I have in memory so this significantly increases the size of my PROM image, but it did solve the problem. Thanks! --------------------------------------- Posted through http://www.FPGARelated.com
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