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>> >>This error tells you that when you remove your reset signal that the flip >>flops see it 520 ps before the next rising edge of the clock and that Actually it needs to see it 520 ps before the clock but you only have 516 ps. It is barely missing >>thanks for your reply ,i have set the rst==1 in "initialize inputs" in my >test.v .but there are aslo two errors . > # .main_pane.signals.interior.cs ># ** Error: >F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold( >negedge CLK:447545 ps, negedge I &&& in_clk_enable1:447552 ps, 118 ps ); ># Time: 447552 ps Iteration: 1 Instance: /test_v/uut/yuv_addr_1_1 ># ** Error: >F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold( >negedge CLK:863545 ps, negedge I &&& in_clk_enable1:863552 ps, 118 ps ); ># Time: 863552 ps Iteration: 1 Instance: /test_v/uut/yuv_addr_1_1 > These are hold time violations. You need to hold your inputs for 118 ps after the clock edge but you are only seeing 7 ps. The inputs are chainging to soon. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144901
using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need the terminations at the end of the fly-by routing of the address bus? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144902
I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDOArticle: 144903
It seems our veterans are not familiar with the subject. any comments anyone? SerkanArticle: 144904
It's a while (>10 years) since I worked with EDIFs, but... > questions > 1- Is there a way other than sending my top module and other 15 edifs > to the client. Can you not generate one EDIF for the whole design? The user bits will be instantiated as a black box which will be pulled in during syntesis. ? Nial.Article: 144905
On Thu, 14 Jan 2010 00:18:33 -0800 (PST), Serkan <oktem@su.sabanciuniv.edu> wrote: >It seems our veterans are not familiar with the subject. >any comments anyone? Try approach (2) yourself. You can test it by writing a module which mimics the user's module (has the same interface) but doesn't actually do the work (e.g. it just passes the inputs to the outputs) See how separately synthesised modules are treated as black boxes and combined at the NGDbuild stage in the EDK flow EDK. THat may help with the details. - BrianArticle: 144906
> any comments anyone? Don't be impatient, both your posts only turned up on my server this morning. This is usenet remember. Nial.Article: 144907
lonny pisze: > using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need > the terminations > at the end of the fly-by routing of the address bus? > > > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface on > http://www.FPGARelated.com DDR3 has got not only max frequency. See min frequency or min tck. AdamArticle: 144908
On Jan 14, 11:50=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > It's a while (>10 years) since I worked with EDIFs, but... > > > questions > > 1- Is there a way other than sending my top module and other 15 edifs > > to the client. > > Can you not generate one EDIF for the whole design? > > The user bits will be instantiated as a black box which will be pulled in > during syntesis. > > ? > > Nial. if EDIF itself can be generated with a black box inside option 2 may actually work. thank you very much for the comments. serkanArticle: 144909
On Jan 14, 12:00=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 14 Jan 2010 00:18:33 -0800 (PST), Serkan <ok...@su.sabanciuniv.ed= u> > wrote: > > >It seems our veterans are not familiar with the subject. > >any comments anyone? > > Try approach (2) yourself. > > You can test it by writing a module which mimics the user's module (has t= he same > interface) but doesn't actually do the work (e.g. it just passes the inpu= ts to > the outputs) > > See how separately synthesised modules are treated as black boxes and com= bined > at the NGDbuild stage in the EDK flow EDK. THat may help with the details= . > > - Brian Actually I started option 3 but will try option 2 and post the results here. thanks SerkanArticle: 144910
Leland, Go to the website, xilinx.com, and search for "classic" software. This takes you to the latest and best last webpack, and also has references to past best releases. The notes on the releases tells you what they support. AB6VU (Austin)Article: 144911
=?ISO-8859-2?Q?Adam_G=F3rski?= <totutousungorskia@malpawp.pl> wrote: >lonny pisze: >> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need >> the terminations >> at the end of the fly-by routing of the address bus? Probably not. >> >> >> --------------------------------------- >> This message was sent using the comp.arch.fpga web interface on >> http://www.FPGARelated.com > >DDR3 has got not only max frequency. See min frequency or min tck. AFAIK only the PLL has a minimum frequency. In order to detect and configure the memory you have to run it at a lower frequency which implies DDR3 memory can also be used at (poorly specified) lower frequencies. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 144912
Adam Górski wrote: > lonny pisze: >> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you >> need >> the terminations >> at the end of the fly-by routing of the address bus? > > DDR3 has got not only max frequency. See min frequency or min tck. He has the DLL disabled, which is the only component that actually has the minimum frequency restriction. If you disable the DLL, the phase relationship between input clock and output data strobe and data is not fixed and specified, but at 50MHz that might not be a problem. But the DRAM manufacturers usually don't specify or guarantee anything when you run the chips in that mode, so I've never used it... As to the OP's question: It depends... On your stackup, the length of the routes, the number of chips hanging on the address bus... It's not just the frequency that matters. It would be best to simulate the transmission lines beforehand. HTH, SeanArticle: 144913
Hello, I've been using the Quartus Simulator for many years and have recently started learning about the SystemVerilog Verification. I was hoping to find someone that has done this and is using Quartus. I am new to ModelSim and I configure Quartus to launch ModelSim to run my simulation. If anyone could provide a simple example of a program and a Verification testbench I would very much appreciate it. I've been reading Chris Spear's book SystemVerilog for Verification and would like to see an example that works in Quartus. I'm still trying to get a handle of what is a Generator, Agent, Drier, Monitor, and Checker, terms found in Spear's book. Thanks everyone, joeArticle: 144914
Griffin <captain.griffin@gmail.com> writes: > Has anyone got any experience programming the ML402 using only JTAG? > Is it even possible? Well, sure. You can always program just the FPGA over JTAG and worry about permanent storage later.Article: 144915
I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDOArticle: 144916
I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDOArticle: 144917
I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDOArticle: 144918
On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote: >Hello, I've been using the Quartus Simulator for many years and have >recently started learning about the SystemVerilog Verification. I was >hoping to find someone that has done this and is using Quartus. I am >new to ModelSim and I configure Quartus to launch ModelSim to run my >simulation. If anyone could provide a simple example of a program and >a Verification testbench I would very much appreciate it. I've been >reading Chris Spear's book SystemVerilog for Verification and would >like to see an example that works in Quartus. I'm still trying to get >a handle of what is a Generator, Agent, Drier, Monitor, and Checker, >terms found in Spear's book. Note that you will need the enhanced version of ModelSim (Questa, or possibly Modelsim SE with various additional license features) to run most of the new SystemVerilog verification features. Chris Spear's book mainly describes verification architecture using SystemVerilog's object-oriented programming features, and those definitely require top-end features of the simulator that you simply won't get in the cheaper or "student" editions. If you do have access to a full version of Questa or Modelsim, you will also need to be aware that the examples in Spear's book were written to run on Synopsys' VCS simulator. Although the SystemVerilog language is IEEE standardized, there remain some differences among the simulators - and the book was written a while ago, at a time when those differences were somewhat greater. So don't be too surprised if you get compile errors for some examples - folk here will certainly be able to help straighten that out for you. Also, take a look at the two big-name methodology websites www.vmmcentral.org www.ovmworld.org Both have downloads of toolkits, documentation and examples, and both have active user forums. -- Jonathan BromleyArticle: 144919
>On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote: > >>Hello, I've been using the Quartus Simulator for many years and have >>recently started learning about the SystemVerilog Verification. I was >>hoping to find someone that has done this and is using Quartus. I am >>new to ModelSim and I configure Quartus to launch ModelSim to run my >>simulation. If anyone could provide a simple example of a program and >>a Verification testbench I would very much appreciate it. I've been >>reading Chris Spear's book SystemVerilog for Verification and would >>like to see an example that works in Quartus. I'm still trying to get >>a handle of what is a Generator, Agent, Drier, Monitor, and Checker, >>terms found in Spear's book. > >Note that you will need the enhanced version of ModelSim (Questa, >or possibly Modelsim SE with various additional license features) >to run most of the new SystemVerilog verification features. >Chris Spear's book mainly describes verification architecture >using SystemVerilog's object-oriented programming features, >and those definitely require top-end features of the simulator >that you simply won't get in the cheaper or "student" editions. > >If you do have access to a full version of Questa or Modelsim, >you will also need to be aware that the examples in Spear's >book were written to run on Synopsys' VCS simulator. Although >the SystemVerilog language is IEEE standardized, there remain >some differences among the simulators - and the book was written >a while ago, at a time when those differences were somewhat >greater. So don't be too surprised if you get compile errors >for some examples - folk here will certainly be able to >help straighten that out for you. > >Also, take a look at the two big-name methodology websites > www.vmmcentral.org www.ovmworld.org >Both have downloads of toolkits, documentation and examples, >and both have active user forums. >-- >Jonathan Bromley > And Janick Bergeron's "Verification Guild" site at http://verificationguild.com/ is a great resource for SystemVerilog verification information (and some good stuff for other languages). --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144920
>>> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need >>> the terminations >>> at the end of the fly-by routing of the address bus? >> DDR3 has got not only max frequency. See min frequency or min tck. > > AFAIK only the PLL has a minimum frequency. In order to detect and > configure the memory you have to run it at a lower frequency which > implies DDR3 memory can also be used at (poorly specified) lower > frequencies. > For me if I see tck min in datasheet it means it has min tck. You can't relay on "maybe". AdamArticle: 144921
On Thu, 14 Jan 2010 18:36:05 -0500, "Leland C. Scott" <kc8ldo@arrl.net> wrote: >I'm looking for a good stable version of WebPack that supports the old >Spartan and Spartan-2 devices for legacy product maintenance. Any >recommendations? > >Regards; I would suggest 7.1 as stable and pretty good; but check the documentation for supported devices before downloading. - BrianArticle: 144922
On Jan 15, 12:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote: > >Hello, I've been using the Quartus Simulator for many years and have > >recently started learning about the SystemVerilog Verification. I was > >hoping to find someone that has done this and is using Quartus. I am > >new to ModelSim and I configure Quartus to launch ModelSim to run my > >simulation. If anyone could provide a simple example of a program and > >a Verification testbench I would very much appreciate it. I've been > >reading Chris Spear's book SystemVerilog for Verification and would > >like to see an example that works in Quartus. I'm still trying to get > >a handle of what is a Generator, Agent, Drier, Monitor, and Checker, > >terms found in Spear's book. > > Note that you will need the enhanced version of ModelSim (Questa, > or possibly Modelsim SE with various additional license features) > to run most of the new SystemVerilog verification features. > Chris Spear's book mainly describes verification architecture > using SystemVerilog's object-oriented programming features, > and those definitely require top-end features of the simulator > that you simply won't get in the cheaper or "student" editions. > > If you do have access to a full version of Questa or Modelsim, > you will also need to be aware that the examples in Spear's > book were written to run on Synopsys' VCS simulator. =A0Although > the SystemVerilog language is IEEE standardized, there remain > some differences among the simulators - and the book was written > a while ago, at a time when those differences were somewhat > greater. =A0So don't be too surprised if you get compile errors > for some examples - folk here will certainly be able to > help straighten that out for you. > > Also, take a look at the two big-name methodology websites > =A0www.vmmcentral.org=A0www.ovmworld.org > Both have downloads of toolkits, documentation and examples, > and both have active user forums. > -- > Jonathan Bromley Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will that be okay?Article: 144923
On Jan 15, 2:20=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.gmail.com> wrote: > >On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote: > > >>Hello, I've been using the Quartus Simulator for many years and have > >>recently started learning about the SystemVerilog Verification. I was > >>hoping to find someone that has done this and is using Quartus. I am > >>new to ModelSim and I configure Quartus to launch ModelSim to run my > >>simulation. If anyone could provide a simple example of a program and > >>a Verification testbench I would very much appreciate it. I've been > >>reading Chris Spear's book SystemVerilog for Verification and would > >>like to see an example that works in Quartus. I'm still trying to get > >>a handle of what is a Generator, Agent, Drier, Monitor, and Checker, > >>terms found in Spear's book. > > >Note that you will need the enhanced version of ModelSim (Questa, > >or possibly Modelsim SE with various additional license features) > >to run most of the new SystemVerilog verification features. > >Chris Spear's book mainly describes verification architecture > >using SystemVerilog's object-oriented programming features, > >and those definitely require top-end features of the simulator > >that you simply won't get in the cheaper or "student" editions. > > >If you do have access to a full version of Questa or Modelsim, > >you will also need to be aware that the examples in Spear's > >book were written to run on Synopsys' VCS simulator. =A0Although > >the SystemVerilog language is IEEE standardized, there remain > >some differences among the simulators - and the book was written > >a while ago, at a time when those differences were somewhat > >greater. =A0So don't be too surprised if you get compile errors > >for some examples - folk here will certainly be able to > >help straighten that out for you. > > >Also, take a look at the two big-name methodology websites > > =A0www.vmmcentral.org=A0www.ovmworld.org > >Both have downloads of toolkits, documentation and examples, > >and both have active user forums. > >-- > >Jonathan Bromley > > And Janick Bergeron's "Verification Guild" site athttp://verificationguil= d.com/is a great resource for SystemVerilog > verification information (and some good stuff for other languages). > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Thanks everyone for your comments.Article: 144924
>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >that be okay? I wouldnt of thought that version of Modelsim will work. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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