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On Fri, 25 Feb 2011 16:00:34 +0100, "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote: >"Dom Bannon" <nospam@nospam.com> wrote in message >news:la1fm6pel35182jhpkd5b19cvus3h28te7@4ax.com... >> BTW, if you do integer conversion first, as you suggest in another >> post, it won't 'work' either. If you use 'TO_01', you'll get a warning >> if you try to convert an 'X'. You can convert '0' to integer 0 if you >> want to, but that wont affect any of the numeric_std multiplies. > >A warning I can live with. But I wonder what the invalid result will be.. >Since integers cant go 'x' the result may end up with what I need. I prefer >that to conditional simulation code. Integers can't be X, but you've got an X in your circuit somewhere. You could convert your X's to 0 with the numeric_std to_01 (to_01(my_int, '0')). The default is to set X's to '0' if you leave out the second parameter. This is not a smart thing to do, though. You need to get rid of your X's instead of persuading the simulator to treat them 'correctly' according to your application.Article: 150976
Dom Bannon <nospam@nospam.com> writes: > Why? What is a 'std_logic_vector'? What does it encode? It could be an > IEEE float, for example. In this case, it's not true that I made an assumption that he was representing integers, which was wrong. Like you say, it could as well have been IEEE-754, then 0 times whatever is not always 0. //Petter -- .sig removed by request.Article: 150977
On Feb 23, 3:50=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > =A0That's what I wanted to do, but I couldn't find > ANYTHING in Xilinx's documentation or the forum that mentioned this optio= n. > > Jon It's out there: <http://www.xilinx.com/support/answers/3404.htm> You just don't have keys to the ivory tower yet. RKArticle: 150978
On 02/25/2011 10:19 AM, NeedCleverHandle wrote: > On Feb 23, 3:50 pm, Jon Elson<jmel...@wustl.edu> wrote: >> That's what I wanted to do, but I couldn't find >> ANYTHING in Xilinx's documentation or the forum that mentioned this option. >> >> Jon > > It's out there:<http://www.xilinx.com/support/answers/3404.htm> No, that tells you how TO ground them, I wanted it to NOT ground several that were currently unused, but declared in the VHDL port list. That is the "preserve unused inputs" option, on the same page. JonArticle: 150979
On Friday, February 25, 2011 3:12:47 PM UTC-5, Jon Elson wrote:
> On 02/25/2011 10:19 AM, NeedCleverHandle wrote:
> > On Feb 23, 3:50 pm, Jon Elson<jme...@wustl.edu> wrote:
> >> That's what I wanted to do, but I couldn't find
> >> ANYTHING in Xilinx's documentation or the forum that mentioned this option.
> >>
> >> Jon
> >
> > It's out there:<http://www.xilinx.com/support/answers/3404.htm>
> No, that tells you how TO ground them, I wanted it to NOT ground several
> that were currently unused, but declared in the VHDL port list. That is
> the "preserve unused inputs" option, on the same page.
>
> Jon
It seems a bit backwards for the tools to automatically
ground pins that are unused, and then require you to
specifically include and float pins you DON'T want
grounded. I'm always worried that a pin will be
optimized out of the design and end up frying something
at the other end of the net. My defaults would be to
float unused pins, then specifically create an output
like (Verilog):
parameter PINS_TO_GND = 18;
output [PINS_TO_GND-1:0] grounded_pins;
assign grounded_pins = {PINS_TO_GND{1'b0}};
and then place the pins requiring grounding in the
.ucf file.
On the other hand I usually work with boards that are
already designed when I design the innards of
the programmable logic, so a lot of things about the
Xilinx tools seems backwards. For example I have
to set a special switch to allow unmatched LOC
constraints for pins that are on the board, and
have names, but I don't use in a particular
version of the design. At the same time if I have
an output port in my design WITHOUT a LOC constraint
I get no error or warning. The latter case can
cause havoc on a board where the un-LOCed output
gets assigned to some random pin. As far as I
can see there's no "production" mode for
constraints that would make it an error to
have any un-LOCed IOB's.
-- Gabor
Article: 150980Hey folks, we've just posted the latest edition of Xcell Journal at http://www.xilinx.com/publications/xcellonline/index.htm This issue's covers story looks at our stacked silicon interconnect and 28-Gbps transceiver Virtex-7 FPGAs. The issue also includes a bunch of cool features, including: FPGAs Speed the Computation of Complex Credit Derivatives Using MicroBlaze=99 to Build Mil-grade Navigation Systems FPGA Houses Single-Board Computer with SATA Old School: Using Xilinx Tools in Command-Line Mode Also, I'm always looking for great technical content for upcoming issues so if you have a technique or methodology you'd like to share with your colleagues, contact me. Cheers, Mike SantariniArticle: 150981
I am moving a design from Xilinx V4 to Altera's Cyclone II. There is an ODDR component in the original design. Can someone point to an equivalent component in Cyclone II? Thanks in advance.Article: 150982
The Megawizard name is ALTDDIO_OUT. I do not recall if CII has this in its IOE. On 2/25/2011 9:29 PM, Verictor wrote: > I am moving a design from Xilinx V4 to Altera's Cyclone II. There is > an ODDR component in the original design. Can someone point to an > equivalent component in Cyclone II? > > Thanks in advance.Article: 150983
I have a PCB with big pads all around the FPGA (XC3S50A VQFP 100) so I can solder the wires on the pads and do some testing. I've done plenty of tests, possibly damaging the chip. After the last soldering, the test prog didn't work anymore. I've zipped some data bus signal photos here: http://www24.zippyshare.com/v/80404483/file.html 1V / 100ns, 0V on 2nd hor. line. VCCINT around 1.15V VCCINT, VCCAUX around 3.2V D7.jpg: ------- Besides one input-only signal, D7 is the only I/O located in Bank 0, P78. It differs from "others.jpg". VCCINT and VCCIO looks the same as in all other banks. Wire length is the same as the rest. D4-D6.jpg: ---------- This photo is taken with drive strength of 4mA and more. It only works if I use 2mA - and it looks like "others.jpg" D4-P64, D5-P71, D6-P73. others.jpg: ---------- This is how all the other signals look, which is about normal. I've been using all the pins at 12mA at first, for at least a week, even though WASSO said it was overdrive. Could that cause damage to the pins?Article: 150984
On 2/20/2011 4:42 AM, silvio.baccari wrote: >> >> By the time you captured all of the "FPGA-ness" you would have a >> mathematical description that would be so complex it would be useless. >> A mathematical description of what you call "FPGA-ness" may be very useful, since it may be a very effective way to verify your logic before any component is available. >> In general the art of mathematical modeling lies not in capturing >> everything there is to capture about a thing that you want to model. >> Rather, it lies in capturing _just enough_ information about the thing so >> that you can get a _representative_ answer for your _immediate problem_. >> Capture too much information, and at best your model will be confusing, >> and at worst it'll be so unwieldy that you can't do anything useful with >> it. >> A mathematical model *does not* give up the complexity of the phenomenon, it rather describe the relationships between variables in within precisely described boundary conditions and most of the time it is harder to describe the latter rather than the phenomenon itself. > I'm interested only to the logical behavior of an FPGA; not the > complex (transitory) phenomenons between two steady states and the way > to implement the logic core and the memory ones. IMHO it should not be very hard to model the logic and it has nothing to do with the FPGA. I just want to draw your attention to the following example: A = B and C is already a mathematical description, with a boolean operation on a set of signals. Unfortunately this description is limited to deterministic logic, while it is not suitable to describe the behavior of non-deterministic, where a state maybe defined with a probability function (time dependent). There exists a mathematical abstraction called graph, which is often used to represent finite state machines and I believe that is the most appropriate object to represent logical paths. > Thanks, > SilvioArticle: 150985
ISE Webpack 12.2 project is here: http://www52.zippyshare.com/v/86894412/file.html This should be a simple test: get an external clock (20MHz), multiply it by 2, then use that clock to toggle a pin. I've checked with the scope - the input clock is there, but output pin is not toggling. I admit that I didn't read the docs much, I just did what seemed logical - created a new project, added the code to toggle a pin, run coregen to create a DCM, and paste&edit the generated vhdl. Maybe someone could take a quick glimpse?Article: 150986
On Feb 26, 2:25=A0pm, Alessandro Basili <alessandro.bas...@cern.ch> wrote: > On 2/20/2011 4:42 AM, silvio.baccari wrote: > > > > >> By the time you captured all of the "FPGA-ness" you would have a > >> mathematical description that would be so complex it would be useless. > > A mathematical description of what you call "FPGA-ness" may be very > useful, since it may be a very effective way to verify your logic before > any component is available. > > >> In general the art of mathematical modeling lies not in capturing > >> everything there is to capture about a thing that you want to model. > >> Rather, it lies in capturing _just enough_ information about the thing= so > >> that you can get a _representative_ answer for your _immediate problem= _. > >> Capture too much information, and at best your model will be confusing= , > >> and at worst it'll be so unwieldy that you can't do anything useful wi= th > >> it. > > A mathematical model *does not* give up the complexity of the > phenomenon, it rather describe the relationships between variables in > within precisely described boundary conditions and most of the time it > is harder to describe the latter rather than the phenomenon itself. > > > I'm interested only to the logical behavior of an FPGA; not the > > complex (transitory) phenomenons between two steady states and the way > > to implement the logic core and the memory ones. > > IMHO it should not be very hard to model the logic and it has nothing to > do with the FPGA. I just want to draw your attention to the following > example: > > A =3D B and C > > is already a mathematical description, with a boolean operation on a set > of signals. > Unfortunately this description is limited to deterministic logic, while > it is not suitable to describe the behavior of non-deterministic, where > a state maybe defined with a probability function (time dependent). > > There exists a mathematical abstraction called graph, which is often > used to represent finite state machines and I believe that is the most > appropriate object to represent logical paths. > > > Thanks, > > Silvio Hi Alessandro, in the last period, are you talking about Petri net? SilvioArticle: 150987
On Saturday, February 26, 2011 4:29:03 PM UTC-5, aleksa wrote: > ISE Webpack 12.2 project is here: > http://www52.zippyshare.com/v/86894412/file.html > > This should be a simple test: get an external clock (20MHz), > multiply it by 2, then use that clock to toggle a pin. > > I've checked with the scope - the input clock is there, > but output pin is not toggling. > > I admit that I didn't read the docs much, I just did > what seemed logical - created a new project, added > the code to toggle a pin, run coregen to create a DCM, > and paste&edit the generated vhdl. > > Maybe someone could take a quick glimpse? I'd look at it, but my stupid Win7 computer doesn't know how to open a .rar file. Anyway things to check: 1) Input range of the DCM. For many devices the minimum is 24 MHz. 2) DCM reset signal. Most devices require at least 3 input clock cycles of reset assertion. Also note that the output clocks don't toggle while reset is asserted, so you need to use another clock to generate the reset. 3) Input clock jitter. If the source has high cycle to cycle jitter a DCM won't lock. They are much more sensitive to input jitter than PLL's -- GaborArticle: 150988
The IO pins are pretty rugged in terms of output drive to a low impedance load. The WASSO limit has to do with ground bounce and should not affect the long term chip reliability. If I had to guess, it is more likely that the damage was caused by ESD from an un- grounded soldering iron. -- GaborArticle: 150989
Here is the ZIP file http://www24.zippyshare.com/v/26054846/file.htmlArticle: 150990
Its the RESET thing, thanks. In the final app the FPGA will receive the input clock all the time, even during configuration, so I've removed the RES input from a DCM. However, in this test I didn't apply the input clock right away, but seconds later. After adding the RES input, it popped to life. Depending on the activity of the main CPU, the DCM seems to stop working, but thats probably due to bad grounding. (the PCB is made out of wires)Article: 150991
On 2/27/2011 4:52 AM, silvio.baccari wrote: [snip] >> There exists a mathematical abstraction called graph, which is often >> used to represent finite state machines and I believe that is the most >> appropriate object to represent logical paths. >> > Hi Alessandro, > in the last period, are you talking about Petri net? I'm talking about graphs: http://en.wikipedia.org/wiki/Graph_%28mathematics%29 A Petri net is a bipartite graph, where the nodes are divided in two disjoint sets. The latter can be useful to describe a computer system where you have resources (one set) and events that will utilize the resources (another set) and it is of particular interest in concurrency studies.Article: 150992
Hi again,
Thanks to all your input, I implemented your suggestions, however the
problem remains the same. The result in simulation works fine, but the
hardware
outputs something different. Just to briefly recap, I have two ctrl
signals that determine the behaviour of the entity:
GET (ctrl = "00000000") sets register tx to input of op1
SH1_L (ctrl = "00000001") res := (op1 << 1) | tx;
tx := tx >> 31;
library ieee;
use ieee.std_logic_1164.all;
entity test is
port
(
op1 : in std_logic_vector(31 downto 0); -- Input operand
ctrl : in std_logic_vector(7 downto 0); -- Control signal
clk : in std_logic; -- clock
res : out std_logic_vector(31 downto 0) -- Result
);
end;
architecture rtl of test is
type res_sel_type is (GET, SH1_L);
constant Z : std_logic_vector(31 downto 0) := (others => '0');
signal res_sel : res_sel_type;
signal load : std_logic := '0';
signal shl : std_logic := '0';
signal tx : std_logic_vector(31 downto 0) := (others => '0');
signal inp1 : std_logic_vector(31 downto 0) := (others => '0');
begin
dec_op: process (ctrl, op1)
begin
res_sel <= GET;
load <= '0';
shl <= '0';
inp1 <= ( others => '0');
case ctrl is
-- store operand
when "00000000" =>
inp1 <= op1;
load <= '1';
res_sel <= GET;
-- 1-bit left-shift with carry
when "00000001" =>
inp1 <= op1;
shl <= '1';
res_sel <= SH1_L;
when others =>
-- Leave default values
end case;
end process;
sel_out: process (res_sel, inp1, tx)
begin
case res_sel is
when SH1_L =>
res <= ( inp1(30 downto 0) & '0' ) or tx;
when others =>
res <= (others => '0');
end case;
end process;
sync: process(clk)
begin
if clk'event and clk = '1' then
if load = '1' then
tx <= op1;
elsif shl = '1' then
tx <= Z(30 downto 0) & op1(31);
end if;
end if;
end process;
end rtl;
TESTPROGRAM
GET 0 (this sets tx <= 0 )
SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521
SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643f
SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace
As you can see, the last bit is wrong for the first SH1_L operation. The
first SH1_L operation produces a carry for the NEXT SH1_L operation since
the MSB is set to one of the input, however, it seems that this carry is
already considered in the current SH1_L operation, which is wrong (tx
should be zero).
I checked the synthesis report and there are no latches, so I am a bit
clueless and almost desperate what is going wrong here. I use Xilinx ISE
12.1 for
synthesis, could there be a problem because I do not have a reset signal
in my architecture, that the wrong kind of latches are instantiated?
Many thanks for further helpful comments to solve this issue,
Patrick
Article: 150993On Sunday, February 27, 2011 9:11:18 AM UTC-5, aleksa wrote: > Its the RESET thing, thanks. > > In the final app the FPGA will receive the input clock > all the time, even during configuration, so I've removed > the RES input from a DCM. > > However, in this test I didn't apply the input clock right away, > but seconds later. After adding the RES input, it popped to life. > > Depending on the activity of the main CPU, the DCM seems > to stop working, but thats probably due to bad grounding. > (the PCB is made out of wires) As I said, the DCM is sensitive to jitter on the input clock. One source of jitter is noise on the power supply or ground return. The noise causes a shift in the effective threshold voltage. This in turn shows up as timing jitter because the rise and fall of the input clock is not instantaneous. In the old days when I was working with wire-wrapped prototypes we generally used a board with at least a ground plane and usually also a +5V plane (those were the simpler days of all 5V logic). Only the signals were routed with wires. Hopefully a proper board layout with power and ground planes will clean up your design. -- GaborArticle: 150994
Hi all, I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end up with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream can run standalone on a FPGA. However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that? Many thanks, RichiArticle: 150995
Hello all!
I need pll which can:
1) 40 MHz -> 320 MHz (0 deg),
320 MHz (15 deg),
320 MHz (30 deg),
320 MHz (45 deg),
320 MHz (60 deg)
320 MHz (75 deg),
320 MHz (90 deg),
320 MHz (105 deg),
320 MHz (120 deg),
320 MHz (135 deg),
320 MHz (150 deg),
320 MHz (165 deg),
320 MHz (180 deg).
They can be together or not.
And I have two fpgas: Cyclone III (Altera), Spartan-3AN.
What fpga is better for me? Why? Or its no difference?
Thanks all for answers!
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 150996Hello, I'm a novice in FPGA, so please forgive me if I'm asking simple questions. I've got Spartan-3E Evaluation Kit and I need to realize a programmable generator of pulses of nanosecond duration. The problem is as follows: I've got a trigger pulse and I need to generate a TTL pulse of nanosecond duration with programmable width (with step about 200-500 ps, range 2 ns - 100 ns (for example)) and programmable delay (with 200-500 ps step). The maximum delay from in to out must not be more than 10 ns. Actually I need to realize a wide-range pulse generator, but as I understand there is no problem generate wide pulses (more than 100 ns) with larger step (10 ns) working in synchroneous regime and using clock. But for narrow pulses I think I should work in asynchroneous regime. I could use elements with known delay and link them into a chain. If it possible to realize such project using Spartan-3E FPGA chip, or maybe I need something from Virtex family. Thank you in advance. Alex. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150997
hi....Im new to fpga boards .....I need to load pixels of an image serially for image processing....I've written the code in verilog hdl for noise removal algorithm and now i should dump my code onto an fpga board so that i can serially access the pixels of an image (256x256 or 512x512) and perform noise removal by scanning each and every pixel.....kindly suggest me some method to do this...and also help me choose the right fpga board.....in my college lab we have xilinx spartan 2....spartan 3.....altera cyclone2....de2.....boards......please help me. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150998
I need to route a FAST CLK (that is used for deserializing and input to only one bank) to another bank's IODELAY2 and IOSERDES2 elements. Is this possible? Please remember that I also need to send signals like, -serdesstrobe, -fast ioclk(sampling fast serial data), -parallel clk(clk whose frequency is the same as parallel data(deserialized data)) to these elements. SerkanArticle: 150999
On Feb 28, 4:37=A0pm, "praneeth87" <praneeth87@n_o_s_p_a_m.gmail.com> wrote: > hi....Im new to fpga boards .....I need to load pixels of an image serial= ly > for image processing....I've written the code in verilog hdl for noise > removal algorithm and now i should dump my code onto an fpga board so tha= t > i can serially access the pixels of an image (256x256 or 512x512) and > perform noise removal by scanning each and every pixel.....kindly suggest > me some method to do this...and also help me choose the right fpga > board.....in my college lab we have xilinx spartan 2....spartan > 3.....altera cyclone2....de2.....boards......please help me. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Put your vhdl module that does the algorithm on a top module Put this top module on a testbench and simulate it. Do a post place and route simulation if required (it the design is complex) Check it meets timings and fulfills algorithm. Using ISE, open a new project , select your FPGA,(spartan 3 is ok) Add your source vhdl top block and others Prepare a ucf file that tells the ISE which input is coming from which pad Using ISE compile your code. Generate a programming file. Check all the warnings. Connect your FPGA to your computer Program your FPGA If it does not work put signals on a test point or some led or do another post place and route simulation
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