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On Wed, 02 Mar 2011 08:37:35 -0600, francesco_pincio wrote: > Hello! > I'm new in the forum and just done an FPGA university course, very very > small...we have only turned on/off led with finite state machine and so > on...now i'm tryng to develope an IIR filter with XSA50 board form Xess > with spartanIIe50 fpga. FIlter kernel is just a 2 pole system with a > zero in 0, i would do a bandpass with changable passaband with > pushbuttons; i 've idealized that main structure of the program would be > a module with a counter for generating clock for the ADC/DAC, a module > that pass this samples in the filtern kernel, the filter kernel iir > itself and a module that passes filtererd samples to DAC; mainly i have > 2 problems: > > 1) i can do only operation with radix-2 coefficient, so i can use only > 1/2, 1/4 an so on. i don't understand how to pass a float value and > multiply it Who needs floating point? You can do this all with fixed point arithmetic. Let your coefficients range from -1 to 1, or 0 to 2, or whatever you need, then implement your filter. In an HDL, this is a matter of doing your multiplication, and picking the leftmost (or nearly leftmost) bits out of the answer, instead of the rightmost. > 2)do i need a ram to store at least y[n-2] sample? Are you trying to do this in batch mode, or continuous? If it's continuous, you should only need to keep two filter states. You will find that you need to keep more precision on your filter states than you have on your incoming (and probably outgoing) data. This is not a subject that can be done justice to in a newsgroup posting, and everyone and his sister wants to know. Do a web search on "IIR Filter for FPGA" and you should find at least one tutorial. -- http://www.wescottdesign.comArticle: 151051
Thanks for publishing your results! It is interesting how little variance there is in the SynplifyPro results from widely different RTL implementations. This allows you, within limits, to code something so that it makes sense functionally to you and others, and the synthesis tool will still get pretty darn close to "the optimal" implementation so that it will work even in demanding environments (speed and/or space constrained). This also allows reuse of the same code across more environments. AndyArticle: 151052
Hi, On one of our boards we use a serial (SPI) flash as configuration chip for a Xilinx spartan3e. We program this memory with the Platform Cable USB, using the SPI programming mode in impact (ise9.1). This works fine. One of these boards is at a remote site and they happen to have an old parallel cable III available. Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16) using the parallel cable III? Do I need a specific impact version for this or can I just use the 9.1 or the latest version? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Democracy is a process by which the people are free to choose the man who will get the blame. -- Laurence J. PeterArticle: 151053
On Wednesday, March 2, 2011 2:33:34 AM UTC-5, a s wrote: > Johnp, Brian, thank you too for your input! Much appreciated. > > I have ran your code through 2 synthesisers and have updated the table > of required resources. > > -------------- 32-bit input data -------------- > unrolled: XST 74 LUTs, 41 slices > unrolled: SynplifyPro 57 LUTs, 34 slices > > loop: XST 100 LUTs, 54 slices > loop: SynplifyPro 57 LUTs, 34 slices > > funct: XST 317 LUTs, 161 slices > funct: SynplifyPro 58 LUTs, 34 slices > > JohnpV1: XST 62 LUTs, 35 slices > JohnpV1: SynplifyPro 57 LUTs, 33 slices > > JohnpV2: XST 78 LUTs, 43 slices > JohnpV2: SynplifyPro 54 LUTs, 32 slices > > Brian: XST 57 LUTs, 39 slices > Brian: SynplifyPro 57 LUTs, 41 slices > > > The latest 3 pairs of results are interesting because even > XST produces good results, especially in Brian's version > where XST is surprisingly even slightly better. But anyway, > it's not that XST is so clever, it is a clever coding of the design. > > Regards, > Peter I didn't catch which device you are targeting, but I decided to try this myself with XST and Spartan 3A, using Verilog to see if there are any significant differences in synthesis performance. Here's the code: module count_bits #( parameter IN_WIDTH = 32, parameter OUT_WIDTH = 6 ) ( input wire [IN_WIDTH-1:0] data_in, output reg [OUT_WIDTH-1:0] data_out ); always @* begin : proc integer i; integer sum; sum = 0; for (i = 0;i < IN_WIDTH;i = i + 1) sum = sum + data_in[i]; data_out = sum; end endmodule And the results for the 32-bit case (XST) Number of Slices: 41 out of 1792 2% Number of 4 input LUTs: 73 out of 3584 2% which is very close to your original unrolled result. -- GaborArticle: 151054
"Gabor" <gabor@alacron.com> wrote in message news:0e538dee-d282-49ce-a340-7c4d851399a4@glegroupsg2000goo.googlegroups.com...
> The IO pins are pretty rugged in terms
> of output drive to a low impedance load.
> The WASSO limit has to do with ground
> bounce and should not affect the long
> term chip reliability.
>
> If I had to guess, it is more likely that
> the damage was caused by ESD from an un-
> grounded soldering iron.
>
> -- Gabor
I have D4-D6 now working at all drive strengths,
meaning that the chip wasn't damaged...
Surely it hasn't fixed itself, right? :)
I had ringing on RD and WR clocks, and also induction in those lines.
After adding series resistors, all problems have vanished.
For example, I did a test: on risingedge(WR) reg <= reg +1.
The CPU was only reading the reg all the time
and the value kept increasing.
I think I understand now the behavior that D4-D6 were showing:
1. CPU did a READ.
2. FPGA updated DATAOUT and placed it on DBUS.
3. induction caused WRITE to activate (and change REG0).
4. ringing on RD caused another READ (with now changed data).
if rising_edge(CLKWR) then
if CS='0' then
if ADDR=0 then REG0 <= DBUS; end if;
end if;
end if;
if falling_edge(CLKRD) then
if CS='0' then
if ADDR=0 then DATAOUT <= REG0; end if;
end if;
end if;
DBUS <= DATAOUT when (CLKRD='0' and CS='0') else "ZZZZZZZZZZZZZZZZ";
Why is D7 different, I don't know...
Article: 151055In comp.arch.fpga Andy <jonesandy@comcast.net> wrote: > It is interesting how little variance there is in the SynplifyPro > results from widely different RTL implementations. This allows you, > within limits, to code something so that it makes sense functionally > to you and others, and the synthesis tool will still get pretty darn > close to "the optimal" implementation so that it will work even in > demanding environments (speed and/or space constrained). This also > allows reuse of the same code across more environments. As far as I know, yes, the tools are pretty good at optimizing combinatorial logic. This problem can be pipelined, though, and as far as I know the tools don't have a way to optimize that. You would at least have to specify the number of pipeline stages. It would be nice to have a tool that would optimize the partition between stages. Even more, given the clock frequency, it would be nice to have a tool that would find the optimal number of pipeline stages. -- glenArticle: 151056
On 03/02/2011 10:35 AM, Stef wrote: > Hi, > > On one of our boards we use a serial (SPI) flash as configuration chip > for a Xilinx spartan3e. We program this memory with the Platform Cable > USB, using the SPI programming mode in impact (ise9.1). This works > fine. > > One of these boards is at a remote site and they happen to have an old > parallel cable III available. > > Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16) > using the parallel cable III? Do I need a specific impact version for > this or can I just use the 9.1 or the latest version? > > This should work. I program 3.3 V CPLDs here with no problem using a parallel cable III. I am now mostly using iSE 10.1 and it seems to work fine. JonArticle: 151057
On Feb 28, 9:36=A0pm, REDDY PRASAD REDDY <reddy....@gmail.com> wrote: > my project is implementing of blowfish algorithm in FPGA and sending > the data from PC through FPGA and encrypt the data.for this which > protocols i can use.please tell me some links related to it. In 15 seconds the web revealed white papers by others that have done this as graduate projects, and a public repository with synthesizeable code targeted to an FPGA. It always amazes me that people are asking for links when they obviously have not done even the first web search - there are way too many posts where the above sentence applies. RKArticle: 151058
On Mar 2, 5:52=A0pm, Gabor <ga...@alacron.com> wrote: > I didn't catch which device you are targeting, but I > decided to try this myself with XST and Spartan 3A, > using Verilog to see if there are any significant > differences in synthesis performance. I am targeting Virtex4FX. > Here's the code: > module count_bits > #( > =A0 parameter IN_WIDTH =3D 32, > =A0 parameter OUT_WIDTH =3D 6 > ) > ( > =A0 input wire =A0[IN_WIDTH-1:0] =A0data_in, > =A0 output reg [OUT_WIDTH-1:0] =A0data_out > ); > > always @* > begin : proc > =A0 integer i; > =A0 integer sum; > =A0 sum =3D 0; > =A0 for (i =3D 0;i < IN_WIDTH;i =3D i + 1) sum =3D sum + data_in[i]; > =A0 data_out =3D sum; > end > > endmodule > > And the results for the 32-bit case (XST) > > Number of Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 41 =A0out o= f =A0 1792 =A0 =A0 2% =A0 > Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 73 =A0out of =A0 = 3584 =A0 =A0 2% =A0 > > which is very close to your original unrolled result. I get the same results with XST targeting V4. But that's really interesting how XST produces better results with Verilog than with VHDL for basically exactly the same input. Running your module through Synopsys results again in seemingly "optimum" 57LUTs and 34 slices. I find it pretty amusing how many options did we come up already with such a "basic" problem as is counting ones in a word. ;-) RegardsArticle: 151059
In comp.arch.fpga a s <nospamas@gmail.com> wrote: (snip) > Running your module through Synopsys results again > in seemingly "optimum" 57LUTs and 34 slices. One should probably also compare propagation delay in addition to the number of LUTs or slices used. I don't believe it is large, but there is some tradeoff between the two. Worst delay would be (N-1) consecutive adders, increasing in width down the line. > I find it pretty amusing how many options did we come up already > with such a "basic" problem as is counting ones in a word. ;-) -- glenArticle: 151060
In comp.arch.fpga, Jon Elson <jmelson@wustl.edu> wrote: > On 03/02/2011 10:35 AM, Stef wrote: >> Hi, >> >> On one of our boards we use a serial (SPI) flash as configuration chip >> for a Xilinx spartan3e. We program this memory with the Platform Cable >> USB, using the SPI programming mode in impact (ise9.1). This works >> fine. >> >> One of these boards is at a remote site and they happen to have an old >> parallel cable III available. >> >> Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16) >> using the parallel cable III? Do I need a specific impact version for >> this or can I just use the 9.1 or the latest version? >> > > This should work. I program 3.3 V CPLDs here with no problem using a > parallel cable III. I am now mostly using iSE 10.1 and it seems to work > fine. OK, thanks. Hope we can try it early next week. In the mean time I have found the parallel cable III schematic. It's so simple, I'm tempted to build it just for testing the above. In fact, it looks very familiar, a bit like the jtag wiggler interface. Must have one somewhere lying around. Hmm, just googled it, it's a bit different. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Yow! It's a hole all the way to downtown Burbank!Article: 151061
On Mar 2, 1:31=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > As far as I know, yes, the tools are pretty good at optimizing > combinatorial logic. =A0This problem can be pipelined, though, and > as far as I know the tools don't have a way to optimize that. > > You would at least have to specify the number of pipeline stages. > It would be nice to have a tool that would optimize the partition > between stages. =A0Even more, given the clock frequency, it would be > nice to have a tool that would find the optimal number of pipeline > stages. =A0 > > -- glen Depending on which tools to which you are referring, yes they can be very good. But there is a large difference between some tools even in their ability to optimize purely combinatorial circuits, as shown in Peter's results. The Synplicity and Mentor tools have the capability to optimize logic across register boundaries (re-balancing). Some do it over more than one boundary (moving logic more than one clock cycle forward/back). You still have to model the pipeline stages, but that can be a simple register array tacked onto the beginning or end of the logic, and you just let the tool redistribute the logic amongst them. Latency often affects other portions of the design, so unless the entire design is "floated" WRT to latency (clock cycles or pipeline stages), it makes little sense for a local optimizing routine to pick the number of stages. The behavioral C synthesis tools (Catapult-C and others) take a completely untimed C algorithm in the form of a function, and allow you to trade resources, clock speed, latency, etc. with the help of different views including a Gant chart of various resources and their utilization. They also can synthesize different types of hardware interfaces, including registers, streaming data, memories (single and dual port), etc. around the function. AndyArticle: 151062
Alright, so I'm trying to compile the example projects from xapp1026, following the instructions included in xapp1026.pdf: www.xilinx.com/support/documentation/application.../xapp1026.pdf I'm using the Xilinx SDK, and successfully managed to import the Hardware Platform Specifications and four xapp1026 example projects. My current setup is as follows: OS: Windows 7 x64 SDK Release Version: 12.3 Build SDK_MS3.70d When I try to "build all", I get the following error: **** Build of configuration Debug for project sock_apps **** make all Building file: ../dispatch.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=3D0 -mxl-soft-mul -MMD -MP - MF"dispatch.d" -MT"dispatch.d" -o"dispatch.o" "../dispatch.c" ../dispatch.c:19:23: error: lwip/inet.h: No such file or directory ../dispatch.c:20:26: error: lwip/ip_addr.h: No such file or directory ../dispatch.c: In function =91print_headers=92: ../dispatch.c:27: warning: implicit declaration of function =91xil_printf=92 ../dispatch.c:32: warning: implicit declaration of function =91print_echo_app_header=92 ../dispatch.c:35: warning: implicit declaration of function =91print_rxperf_app_header=92 ../dispatch.c:38: warning: implicit declaration of function =91print_txperf_app_header=92 ../dispatch.c:41: warning: implicit declaration of function =91print_tftp_app_header=92 ../dispatch.c:44: warning: implicit declaration of function =91print_web_app_header=92 ../dispatch.c: In function =91launch_app_threads=92: ../dispatch.c:60: warning: implicit declaration of function =91sys_thread_new=92 ../dispatch.c:62: error: =91DEFAULT_THREAD_PRIO=92 undeclared (first use in this function) ../dispatch.c:62: error: (Each undeclared identifier is reported only once ../dispatch.c:62: error: for each function it appears in.) make: *** [dispatch.o] Error 1 It looks like it's complaining that I haven't added lwip to the include path. The xapp1026 instructions don't mention anything about this, so I thought some kind of Xilinx distribution of lwip was already included, but I guess not. Therefore, my question overall is, how do I go about adding lwip to my Xilinx SDK in such a way that I can get these projects to build? If that isn't the solution to these errors, what is?Article: 151063
In comp.arch.fpga Andy <jonesandy@comcast.net> wrote: (after I wrote) >> As far as I know, yes, the tools are pretty good at optimizing >> combinatorial logic. This problem can be pipelined, though, and >> as far as I know the tools don't have a way to optimize that. > >> You would at least have to specify the number of pipeline stages. >> It would be nice to have a tool that would optimize the partition >> between stages. Even more, given the clock frequency, it would be >> nice to have a tool that would find the optimal number of pipeline >> stages. > Depending on which tools to which you are referring, yes they can be > very good. But there is a large difference between some tools even in > their ability to optimize purely combinatorial circuits, as shown in > Peter's results. > The Synplicity and Mentor tools have the capability to optimize logic > across register boundaries (re-balancing). Some do it over more than > one boundary (moving logic more than one clock cycle forward/back). > You still have to model the pipeline stages, but that can be a simple > register array tacked onto the beginning or end of the logic, and you > just let the tool redistribute the logic amongst them. That does sound pretty nice of them. Lately I mostly use Xilinx ISE which, as far as I know, doesn't do that. > Latency often affects other portions of the design, so unless the > entire design is "floated" WRT to latency (clock cycles or pipeline > stages), it makes little sense for a local optimizing routine to pick > the number of stages. I have done systolic array designs that do, as you say, float. The constraint is on the clock period. Though in addition there is the question of the number of unit cells that can fit into one FPGA. Throughput is clock frequency times (cells/FPGA). > The behavioral C synthesis tools (Catapult-C and others) take a > completely untimed C algorithm in the form of a function, and allow > you to trade resources, clock speed, latency, etc. with the help of > different views including a Gant chart of various resources and their > utilization. They also can synthesize different types of hardware > interfaces, including registers, streaming data, memories (single and > dual port), etc. around the function. Are there tools that will convert a sequential C code dynamic programming algorithm to a systolic array? That would be a pretty amazing optimization. -- glenArticle: 151064
I am his sister... he is a ufo hunter and inventor and he talks all the time...more proof? he went to Boerne High in Tx. he built an airplain in his senior yr.Article: 151065
On 03/03/2011 01:01, DaMunky89 wrote: > Alright, so I'm trying to compile the example projects from xapp1026, > following the instructions included in xapp1026.pdf: > www.xilinx.com/support/documentation/application.../xapp1026.pdf > > I'm using the Xilinx SDK, and successfully managed to import the > Hardware Platform Specifications and four xapp1026 example projects. > My current setup is as follows: > > OS: Windows 7 x64 > SDK Release Version: 12.3 Build SDK_MS3.70d > > When I try to "build all", I get the following error: > > **** Build of configuration Debug for project sock_apps **** > > make all > Building file: ../dispatch.c > Invoking: MicroBlaze gcc compiler > mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -mxl-soft-mul -MMD -MP - > MF"dispatch.d" -MT"dispatch.d" -o"dispatch.o" "../dispatch.c" > ../dispatch.c:19:23: error: lwip/inet.h: No such file or directory > ../dispatch.c:20:26: error: lwip/ip_addr.h: No such file or directory > ../dispatch.c: In function ‘print_headers’: > ../dispatch.c:27: warning: implicit declaration of function > ‘xil_printf’ > ../dispatch.c:32: warning: implicit declaration of function > ‘print_echo_app_header’ > ../dispatch.c:35: warning: implicit declaration of function > ‘print_rxperf_app_header’ > ../dispatch.c:38: warning: implicit declaration of function > ‘print_txperf_app_header’ > ../dispatch.c:41: warning: implicit declaration of function > ‘print_tftp_app_header’ > ../dispatch.c:44: warning: implicit declaration of function > ‘print_web_app_header’ > ../dispatch.c: In function ‘launch_app_threads’: > ../dispatch.c:60: warning: implicit declaration of function > ‘sys_thread_new’ > ../dispatch.c:62: error: ‘DEFAULT_THREAD_PRIO’ undeclared (first use > in this function) > ../dispatch.c:62: error: (Each undeclared identifier is reported only > once > ../dispatch.c:62: error: for each function it appears in.) > make: *** [dispatch.o] Error 1 > > It looks like it's complaining that I haven't added lwip to the > include path. The xapp1026 instructions don't mention anything about > this, so I thought some kind of Xilinx distribution of lwip was > already included, but I guess not. Therefore, my question overall is, > how do I go about adding lwip to my Xilinx SDK in such a way that I > can get these projects to build? If that isn't the solution to these > errors, what is? It sounds like you didn't include lwip library in your BSP. It is not included by default. You can add it by expanding your BSP in Project Explorer and double click *.mss file. After that click Modify this BSP's Settings and then include lwip130. You should also modify lwip's settings to suite your needs. ~AlešArticle: 151066
Hi all, I'm designing a board with a Xilnx Spartan 6 LX16, and I've some questions about clock managing and pin-planning, before the complete netlist/implementation being prepared. The clock to the FPGA is generated through an oscillator and feed on a gclk pin of the FPGA. The internal CMT (Clock Management Tile) is then used to clock an external ADC and two data-buses with the use of IOSERDES primitives, forwarding clock on one of them. This design will also include a DDR memory interface. Another clock will come from the USB interface (located on an external USB bridge). What are the best practices to follow to correctly pin-planning the most important pins (I refer to pins that will be used as clock I/O and forwarding for data busses), without an already defined implementation of the logic? Thanks a lot for the help! Best regards, Stefano.Article: 151067
Did anyone see this video of 13.1? https://xilinx.webex.com/xilinx/lsr.php?AT=pb&SP=EC&rID=3372608&rKey=38aaf4d8e5851be5 Looks like a big leap forward...Article: 151068
I'm sure others might have a more informed perspective, but from my recent personal observations.. > The internal CMT (Clock Management Tile) is then used to clock an > external ADC and two data-buses with the use of IOSERDES primitives, > forwarding clock on one of them. IOSERDES complains a bit about clocks if your bus spans more than one half bank. Keep it to one if you can, but if your data rate isn't very high it shouldn't actually be a problem. For reference, I used a 200 MHz data rate (DDR) ADC and had to span half banks and it works fine. The only real issue is that the core generator in 12.4 can't produce code that synthesises and you'll spend a bit more time fiddling with it. > This design will also include a DDR memory interface. Pin placements are more or less fixed if you want to use MIG, except that you can swap certain pins as detailed in the data sheet. JoelArticle: 151069
On Thursday, March 3, 2011 5:41:13 AM UTC-5, Stefano Moser wrote: > Hi all, > I'm designing a board with a Xilnx Spartan 6 LX16, and I've some > questions about clock managing and pin-planning, before the complete > netlist/implementation being prepared. > > The clock to the FPGA is generated through an oscillator and feed on a > gclk pin of the FPGA. The internal CMT (Clock Management Tile) is then > used to clock an external ADC and two data-buses with the use of > IOSERDES primitives, forwarding clock on one of them. This design will > also include a DDR memory interface. Another clock will come from the > USB interface (located on an external USB bridge). > > What are the best practices to follow to correctly pin-planning the most > important pins (I refer to pins that will be used as clock I/O and > forwarding for data buses), without an already defined implementation > of the logic? > > Thanks a lot for the help! > Best regards, > Stefano. Definitely build the MIG core and use its recommended (in some cases required) pinout. You don't need to have any other project code to do this, although it helps to have enough to build a "don't use" list for pins required by other functions. Think hard before clocking an ADC with an FPGA output. Depending on the application you may need better jitter specs than can be achieved by the FPGA. For example communications applications typically have input bandwidth very near the sampling rate and therefore are very sensitive to sampling clock jitter. Don't assume that the output jitter from an FPGA pin will be as good as the jitter spec on the internal DCM or PLL. There are other sources of jitter, including activity on nearby pins, and they are all additive. -- GaborArticle: 151070
Hi, On 01/27/11 09:09 PM, Michael wrote: > Hi, > > On 01/27/11 07:47 PM, Steve Ravet wrote: >> Whenever I see internal tool errors like that I first suspect a >> quota/full >> disk type problem. >> >> --steve >> > Dont top post on Usenet. http://www.caliburn.nl/topposting.html > > Then you should have a better control of your server I think and keep > track of usage per day or so. > > There are tools that can monitor diskuage and alert when you are > reaching a critical level. > > >> >> "Michael"<michael_laajanen@yahoo.com> wrote in message >> news:8qajvpF1l4U1@mid.individual.net... >>> Hi, >>> >>> I am trying a design that is from ISE 9.2 on the latest 12.4 using >>> CentOS >>> 64 bit and receive the following error, I can't find anything >>> on Xilinx that refers to it. >>> >>> Anyone seen the same and know a solution? >>> >>> >>> >>> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >>> peeked >>> does not match number of bytes requested. Corrupted file? >> >> > > /michael Just an update. CentOS is not supported and does not seam to run on IS 12.4 sadly. 9.2 does! /michaelArticle: 151071
On Wednesday, March 2, 2011 3:38:09 PM UTC-5, a s wrote: > On Mar 2, 5:52=A0pm, Gabor <ga...@alacron.com> wrote: > > I didn't catch which device you are targeting, but I > > decided to try this myself with XST and Spartan 3A, > > using Verilog to see if there are any significant > > differences in synthesis performance. >=20 > I am targeting Virtex4FX. >=20 > I get the same results with XST targeting V4. >=20 > But that's really interesting how XST produces better results > with Verilog than with VHDL for basically exactly the same input. >=20 > Running your module through Synopsys results again > in seemingly "optimum" 57LUTs and 34 slices. >=20 > I find it pretty amusing how many options did we come up already > with such a "basic" problem as is counting ones in a word. ;-) >=20 > Regards I thought I should try this with Virtex 5, since it has larger LUT's and should therefore greatly reduce the required logic. The results were less than dramatic. XST still ends up with 65 LUT's for V5. So I tried again with V6. As far as I know the V6 has a similar LUT to the V5, but suddenly XST gives me only 35 LUT's (I checked other resources to be sure it didn't also use DSP blocks). So either V6 has more flexibly carry logic, or (more likely) XST has been tuned up a bit to get better results with V6 and the new optimization is not applied to the older technology. Yet another reason to use the latest chips if you want to use the chip vendors tools. -- GaborArticle: 151072
On 03/02/2011 04:26 PM, Stef wrote: > > In the mean time I have found the parallel cable III schematic. It's so > simple, I'm tempted to build it just for testing the above. In fact, it > looks very familiar, a bit like the jtag wiggler interface. Must have one > somewhere lying around. Hmm, just googled it, it's a bit different. > Yes, I have repaired our several times when ESD or whatever popped the one chip in there. Just a voltage level translator and buffer. JonArticle: 151073
Gabor <gabor@alacron.com> wrote: (snip regarding bit counting) > I thought I should try this with Virtex 5, since it > has larger LUT's and should therefore greatly reduce > the required logic. The results were less than > dramatic. XST still ends up with 65 LUT's for V5. The CSA solution uses the fact that three bits can have four possible counts of bits that are one, and that (zero to three) fits in two bits. The extension to that would allow for seven bits with eight possible counts (zero to seven) in three bits. The six input LUT solution, with six bits going to three, would be slightly less efficient. Also, that solution would be found by putting two levels of the usual CSA tree into six input LUTs. -- glenArticle: 151074
Both A and X have what appears to be fairly similar PCIe cores for the S4 and V6 respectively. The A version uses streaming Avalon, the X version streaming AXI. I need 8X PCIe 2, with DMA support, I'm agnostic about A vs X, I'm comfortable with both. Has anyone done a comparison between the two, what are the key differences? I'd like to know what experiences people have had with these cores, what problems if any? Also do they provide Linux drivers? If so how complete are they?
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