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> hi all > stupid questions for PovTruffe (forgive me) Why stupid ? > will you make it yourself (how) or by a pcb maker (where) ? Yes I will design and make the PCB myself using a laser printer. I am limited to 2 layers. I know this is not recommended for FPGAs but this is just a learning project and reliability is not required. I could even solder some extra wires if necessary. However I hope the FPGA will start... > [not very related] and what do you think about add-on cards (where > only fpga live) I dont understand your question.Article: 151151
On Mar 10, 8:41=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > What are you trying to accomplish with this project? > > Ed McGettigan > -- > Xilinx Inc. It seems the OP is expecting an FPGA to already be doing everything that it could do without his having to do anything but purchase them. What is the ordering code for a Spartan that is pre-programmed with all possible applications? Does Digi-key have stock? Can you post the link to that bit-stream? ;)Article: 151152
On Tue, 8 Mar 2011 19:02:52 +0100 "PovTruffe" <PovTache@gaga.invalid> wrote: > Why are there 2 resistors on inputs M0 and M2 on the following > schematic? http://cjoint.com/?1dis6y5LNzz (Basys 2 board) > > By the way why is there a resistor on M1 ? Direct grounding is not > OK ? For my Spartan 3A boards, I've always used hard connections on the mode and variant select pins with no trouble. As pointed out, if you want to use those pins for something after the chip is configured, obviously you will need to arrange for them to connect to whatever external device instead of directly to a rail. ChrisArticle: 151153
On Mar 11, 3:38=A0am, geobsd <geobsd...@gmail.com> wrote: > hi Ed > > i understoud, after buying those, that fgpas can't be used directly in > any OS ! > strangely it is the most flexible PU too (and that's why i bought 5) > > my project is to have dynamic generation of bitstream to have a very > powerfull tablet in any usage ! > > i don't say protyping or R&D is bad but limit fpgas to those fields > only is a non-sense ! > > childs play to push the wheele but later they learn to use them to > make bicycle ;) > i understand that my way will be hard, i didn't saw anyone doing > bicycle yet, ~np i have harder to live in my life ! > > @bient=F4t FPGAs are not limited to prototyping or R&D. If you take a look at the revenue of Xilinx of Altera you will see that it about $4B annually. You can't do that with low volumes. Many startup companies have been started and failed over the years trying to mate FPGAs with CPUs as co-processors, but the general purpose computing space really isn't a good fit. Companies have used FPGAs to create very high end data processing engines to tackle encryption/decryption, real-time video processing and simulation acceleration engines. Usually these are dedicated platforms, but sometimes they are created as expansion cards for PC servers. When you start reading the Spartan-3E data sheet and the user guides in your quest for dynamic bitstream generation you should quickly come to understand the vast complexities that this entails and why it isn't a practical design flow. Ed McGettigan -- Xilinx Inc.Article: 151154
On 12 Mrz., 05:27, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >=A0Companies have used > FPGAs to create very high end data processing engines to tackle > encryption/decryption, real-time video processing and simulation > acceleration engines. =A0Usually these are dedicated platforms, but > sometimes they are created as expansion cards for PC servers. This reminds me of my favorite quote regarding computer architecture: "Special purpose hardware is always faster than general purpose hardware, except in the general case!" An advice to the OP: FPGAs are great, but they definitely are more difficult to use than MCUs. Try to answer your question first for an ARM MCU. (Designing the board, how to solder it, how to program it with no OS, how to connect it to your tablet, how to design the power supply, ...) Once you understood all that, you can continue with the FPGA specific questions: How to design the circuits going into the FPGA, how to do dynamic reconfiguration, how to encode the bitstream, etc. Have fun, KoljaArticle: 151155
Hi, On 03/08/11 01:28 PM, Florian Stock wrote: > Michael<michael_laajanen@yahoo.com> writes: > >>>>> I am trying a design that is from ISE 9.2 on the latest 12.4 using >>>>> CentOS >>>>> 64 bit and receive the following error, I can't find anything >>>>> on Xilinx that refers to it. >>>>> >>>>> Anyone seen the same and know a solution? >>>>> >>>>> >>>>> >>>>> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >>>>> peeked >>>>> does not match number of bytes requested. Corrupted file? >>>> >>>> >>> >>> /michael > >> Just an update. CentOS is not supported and does not seam to run on IS >> 12.4 sadly. 9.2 does! > > > we have on our Servers CentOS (5.5), and ISE 12.4 works on it. > Never saw your error, maybe its something in your design, that the new > version no longer supports? > > http://www.xilinx.com/support/answers/32912.htm indicates that maybe > some permissions are wrong (the link leads to a VISTA Problem, but > it got exact the same error message). > > Florian Is that 32 or 64 bit versions? Also, do you know what libraries is installed over the "vanilla" CentOS 5.5? And how to you setup the environment, is that using Xilins inits that is to be sourced? Much thanks for any input. /michaelArticle: 151156
On Mar 11, 5:52=A0pm, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > It seems the OP is expecting an FPGA to already be doing everything > that it could do without his having to do anything but purchase them. re read what i wrote ! > What is the ordering code for a Spartan that is pre-programmed with > all possible applications? =A0Does Digi-key have stock? =A0Can you post > the link to that bit-stream? ;) ok mister joker, i repeat i want for some usages having the abilty to use my fgpas by direct programming ! i don't need to make a vhdl simulation, on an other pc (with an OS i don't use), to finaly have the bit-stream i want ! for some "work"(i'm not paid) i'll use vhdl but for some elses dynamic- bit-stream !Article: 151157
geobsd wrote: > ok mister joker, bonjour, > i repeat i want for some usages having the abilty to > use my fgpas by direct programming ! (sorry, french ahead) si c'=E9tait possible, d'autres l'auraient fait bien avant. il y a bien eu des syst=E8mes avec reprogrammation partielle mais le temps de g=E9n=E9rer la nouvelle config est =E9norm=E9ment plus long que le chargement lui-m=EAme... comme tu as vu, la situation est bien plus complexe et d=E9sesp=E9r=E9e. c'est terrible mais c'est comme =E7a :-/ quant aux projets pour faire des FPGA "open source" =E7a a =E9t=E9 des =E9checs cuisants. mais on ne d=E9sesp=E8re pas, la situation actuelle est d=E9j=E0 tellement meilleure qu'il y a 10 ans (pour le fun regarde ce vestige du pass=E9 : http://f-cpu.seul.org/new/VHDL-HOWTO.f-cpu alors qu'aujourd'hui, un coup de GHDL et c'est fini ) > i don't need to make a vhdl simulation, on an other pc (with an OS i > don't use), to finaly have the bit-stream i want ! you seem to believe that FPGA are magic boxes that "do what you want". though there is no magic, on the contrary, because in order to get what we want, we have to go through countless tedious steps... particularly because each single technical detail is driven by very complex compromises. just as a thought exercise, which will help your definition and help us helping you : what are your expectations ? how will you generate the bitstream ? what will your input be ? sure you don't want VHDL, or Verilog, but then what would your system be ? binary decision graphs ? what are your constraints, your application field, your targets, your goals, your expected results ? > for some "work"(i'm not paid) i'll use vhdl but for some elses dynamic-= > bit-stream ! do you already use VHDL ? did you ever use a logic synthesiser ? contact me in private if you have time. yg (=E0 le premier lien) --=20 http://ygdes.com / http://yasep.orgArticle: 151158
hi Christophe, geobsd wrote: > prototyping also mean that lot of fgpas consumers have to buy a lot of > fgpas to sell the result of prototyping please quantify "a lot" :-) >> Many startup companies have been started and failed over the years >> trying to mate FPGAs with CPUs as co-processors > as i'm alone, for me, i have nothing to fail : my goal is only to use > my fpgas ;) as everybody here :-) welcome aboard ! > i saw less normal usages too (on the net) please share your finds ! > it's not cause you don't imagine as me that i must do how you tell ! Hmmm sorry but the little I know about Ed lets me suppose he knows a lot about his company's product's use (intended or not :-P) > your softwares Ed include a bit-stream compilateur, now, just wonder what input format this compiler uses, and where it comes from. the compiler i know uses EDIF, does that sound familiar ? > it impli that it > know how to programme my fpgas it will be not very difficult to use > this (if i had the source); there, i think that you dream... ask Microsoft for their kernel's source, ok (there are certain types of contracts that allow it, yet extremely expensive, but it's still possi= ble) ask Xilinx or Altera for the source code of their compilers : that is .... yeah, a pure dream. it's a very highly guarded secret. writing your own would be faster, if it was ever possible. well, S=E9bastien Bourdeauduc has some ideas about this but i'm not sure it works with your S3E. > it will not change (vhdl + fpga) usage, > you will not loose any consumers ! > i didn't said my OS will be a normal one !!! ah, your exokernel ? :-) >> Ed McGettigan >> Xilinx Inc. > if i spend too much time to know how to use those fpgas without using > your softwares in some OS i don't want to use, i may have a > functionnal demo for my project before : > http://opencores.org/project,smart-non-binary-computing,overview Created: Mar 4, 2011 Updated: Mar 11, 2011 SVN: No files checked in Category: Other Language: Other Development status: Planning Additional info: none WishBone Compliant: No this project is about a way to make non-binary computing !!! (yes the title already said it) cells in place of one electron use photons (led, oled, nano crystal, ...)= s (this way look the less expensive, there are elses) to be smart : with ofet-amoled it will keep data even on power loss also it can be highly secure : loading of color maps can take place befor= e it realy start ! you are welcome to play with infinity of models (just imagine for now) * if it's not binary, then what coding system will it use ? * who will fabricate your photonic chips ? etc. etc. > and once tasted your fgpas will not be as good mine ! sure. i'm waiting to see so I can finally run F-CPU with it :-) > so i'll not try to use them as i want in the end ! > np my 5 spartan 3E 500k will be used even with your vhdl usage > restriction what restriction ? VHDL is so much more convenient than EDIF... at least to me. > anyway as you can restrict small consumers to use the hardware you > sell as you want i will restrict all my projects to be open only for > non-xilinx&affiliated companies ! sure, it's your right. what would be the benefit of this restriction ? > sadly for you i didn't bought altera, you have one week to decide if > you can publish the bit-stream specs of old products before i restrict > all my open-sources projects with a "no-xilinx&al license" ! *tumbleweed* huh, yeah, ok... that sounds impressive. > if xilinx can't respect me cause i'm not a big buyer it's not my > problem ! note for later : no company respects anything. why would you expect Xilinx to be different ? deal with it :-/ I think that you still have a lot of things to learn about how this industry works. I never say it's fair or good, but if you want to get something done one day, you'll have to understand and practice many many things. This is why I do mostly electronics design, instead of pure software. > thanks again Ed ! we're all watching you and wishing you good luck. you seem to be passionate and driven by ideals, so at least something good must result from this :-) yg --=20 http://ygdes.com / http://yasep.orgArticle: 151159
hi Ed > FPGAs are not limited to prototyping or R&D. =A0If you take a look at > the revenue of Xilinx of Altera you will see that it about $4B > annually. =A0You can't do that with low volumes. prototyping also mean that lot of fgpas consumers have to buy a lot of fgpas to sell the result of prototyping > Many startup companies have been started and failed over the years > trying to mate FPGAs with CPUs as co-processors as i'm alone, for me, i have nothing to fail : my goal is only to use my fpgas ;) > but the general > purpose computing space really isn't a good fit. =A0Companies have used > FPGAs to create very high end data processing engines to tackle > encryption/decryption, real-time video processing and simulation > acceleration engines. =A0Usually these are dedicated platforms, but > sometimes they are created as expansion cards for PC servers. i saw less normal usages too (on the net) it's not cause you don't imagine as me that i must do how you tell ! > When you start reading the Spartan-3E data sheet and the user guides > in your quest for dynamic bitstream generation you should quickly come > to understand the vast complexities that this entails and why it isn't > a practical design flow. your softwares Ed include a bit-stream compilateur, it impli that it know how to programme my fpgas it will be not very difficult to use this (if i had the source); it will not change (vhdl + fpga) usage, you will not loose any consumers ! i didn't said my OS will be a normal one !!! > Ed McGettigan > Xilinx Inc. if i spend too much time to know how to use those fpgas without using your softwares in some OS i don't want to use, i may have a functionnal demo for my project before : http://opencores.org/project,smart-non-binary-computing,overview and once tasted your fgpas will not be as good mine ! so i'll not try to use them as i want in the end ! np my 5 spartan 3E 500k will be used even with your vhdl usage restriction anyway as you can restrict small consumers to use the hardware you sell as you want i will restrict all my projects to be open only for non-xilinx&affiliated companies ! sadly for you i didn't bought altera, you have one week to decide if you can publish the bit-stream specs of old products before i restrict all my open-sources projects with a "no-xilinx&al license" ! if xilinx can't respect me cause i'm not a big buyer it's not my problem ! thanks again Ed !Article: 151160
> An advice to the OP: > FPGAs are great, but they definitely are more difficult to use than > MCUs. how can you know what is difficult with another point of view you don't have ? > Try to answer your question first for an ARM MCU. (Designing the > board, > how to solder it, how to program it with no OS, how to connect it to > your tablet, how to > design the power supply, ...) > Once you understood all that, you can continue with the FPGA specific > questions: > How to design the circuits going into the FPGA, how to do dynamic > reconfiguration, > how to encode the bitstream, etc. > > Have fun, yes interesting for me ;) thanks KoljaArticle: 151161
salut whygee ! > si c'=E9tait possible, d'autres l'auraient fait bien avant. super arg ! > il y a bien eu des syst=E8mes avec reprogrammation partielle > mais le temps de g=E9n=E9rer la nouvelle config est =E9norm=E9ment > plus long que le chargement lui-m=EAme... > comme tu as vu, la situation est bien plus complexe et d=E9sesp=E9r=E9e. > c'est terrible mais c'est comme =E7a :-/ > quant aux projets pour faire des FPGA "open source" > =E7a a =E9t=E9 des =E9checs cuisants. mais on ne d=E9sesp=E8re pas, > la situation actuelle est d=E9j=E0 tellement meilleure qu'il y a 10 ans > (pour le fun regarde ce vestige du pass=E9 :http://f-cpu.seul.org/new/VHD= L-HOWTO.f-cpu > alors qu'aujourd'hui, un coup de GHDL et c'est fini ) GHDL =3D> spartan 3E bit-stream !?! > > i don't need to make a vhdl simulation, on an other pc (with an OS i > > don't use), to finaly have the bit-stream i want ! > > you seem to believe that FPGA are magic boxes that "do what you want". > though there is no magic, on the contrary, because in order to get > what we want, we have to go through countless tedious steps... > particularly because each single technical detail is driven > by very complex compromises. it depend the compromise and the operations the fgpas have to do ... once again i never said i'll never use vhdl for some bit-stream, i said it will be very annoying and slow for some things ! > just as a thought exercise, which will help your definition > and help us helping you : > what are your expectations ? only use my fpgas (as i want if possible) > how will you generate the bitstream ? from small chunks i think now but i'm open ;) > what will your input be ? the range is from sensors to the cpu ! > sure you don't want VHDL, or Verilog i'll learn vhdl ! > but then what would your system be ? binary decision graphs ? the OS will be a mix of exo and micro kernel, the fpgas should be used in all possibles ways ! > what are your constraints, your application field, > your targets, your goals, your expected results ? i will feel at school if you continue ;) i have no constraints, field, targets my goal is only to learn and use my fpgas ! i expect to reach my goal here ! > did you ever use a logic synthesiser ? is my brain ok !?! ;) > contact me in private if you have time. i will not annoy you if you don't have a quick way for a 5 fpga pcb now ! maybe later ;) many thanksArticle: 151162
On Mar 12, 5:50=A0pm, whygee <y...@yg.yg> wrote: > hi Christophe, re > please quantify "a lot" :-) at nose view 75% > welcome aboard ! thanks ! > please share your finds ! google give nice result > > it's not cause you don't imagine as me that i must do how you tell ! > > Hmmm sorry but the little I know about Ed lets me suppose he knows > a lot about his company's product's use (intended or not :-P) did i said he is an idiot !? > > your softwares Ed include a bit-stream compilateur, > > now, just wonder what input format this compiler uses, > and where it comes from. the compiler i know uses EDIF, > does that sound familiar ? not familar but it will come > > =A0> it impli that it> know how to programme my fpgas it will be not very= difficult to use > > this (if i had the source); > > there, i think that you dream... no ;) > ask Xilinx or Altera for the source code of their compilers : > that is .... yeah, a pure dream. it's a very highly guarded secret. i don't care of the result ! i ask to not be a traitor ! > writing your own would be faster, if it was ever possible. > well, S=E9bastien Bourdeauduc has some ideas about this > but i'm not sure it works with your S3E. ok i'll see > ah, your exokernel ? :-) yes > > >http://opencores.org/project,smart-non-binary-computing,overview > * if it's not binary, then what coding system will it use ? i didn't put a name on the many possible choices ;) > * who will fabricate your photonic chips ? many sell screens and else parts... > what restriction ? 40% selling price of the final product the affiliated or xilinx will have to give to use anything of my projects > VHDL is so much more convenient than EDIF... at least to me. you are human, not a cpu ;) > > anyway as you can restrict small consumers to use the hardware you > > sell as you want i will restrict all my projects to be open only for > > non-xilinx&affiliated companies ! > > sure, it's your right. > what would be the benefit of this restriction ? none for xilinx > > sadly for you i didn't bought altera, =A0you have one week to decide if > > you can publish the bit-stream specs of old products before i restrict > > all my open-sources projects with a "no-xilinx&al license" ! > > *tumbleweed* > > huh, yeah, ok... that sounds impressive. no but to not lie i have to tell it ! > > if xilinx can't respect me cause i'm not a big buyer it's not my > > problem ! > > note for later : no company respects anything. why would you expect > Xilinx to be different ? deal with it :-/ > > I think that you still have a lot of things to learn about how > this industry works. I never say it's fair or good, but if you want > to get something done one day, you'll have to understand > and practice many many things. ;) i know... > This is why I do mostly electronics design, instead of pure software. lucky you ! > > thanks again Ed ! > > we're all watching you and wishing you good luck. > you seem to be passionate and driven by ideals, > so at least something good must result from this :-) i am, i have no hate for Ed, the poor should not really understand why i'm not happy with my fpga... anyway i usualy do what i said, maybe i'm nothing maybe not @bient=F4tArticle: 151163
On Mar 12, 8:56=A0am, geobsd <geobsd...@gmail.com> wrote: > hi Ed > > > FPGAs are not limited to prototyping or R&D. =A0If you take a look at > > the revenue of Xilinx of Altera you will see that it about $4B > > annually. =A0You can't do that with low volumes. > > prototyping also mean that lot of fgpas consumers have to buy a lot of > fgpas to sell the result of prototyping > > > Many startup companies have been started and failed over the years > > trying to mate FPGAs with CPUs as co-processors > > as i'm alone, for me, i have nothing to fail : my goal is only to use > my fpgas ;) > > > but the general > > purpose computing space really isn't a good fit. =A0Companies have used > > FPGAs to create very high end data processing engines to tackle > > encryption/decryption, real-time video processing and simulation > > acceleration engines. =A0Usually these are dedicated platforms, but > > sometimes they are created as expansion cards for PC servers. > > i saw less normal usages too (on the net) > it's not cause you don't imagine as me that i must do how you tell ! > > > When you start reading the Spartan-3E data sheet and the user guides > > in your quest for dynamic bitstream generation you should quickly come > > to understand the vast complexities that this entails and why it isn't > > a practical design flow. > > your softwares Ed include a bit-stream compilateur, it impli that it > know how to programme my fpgas it will be not very difficult to use > this (if i had the source); it will not change (vhdl + fpga) usage, > you will not loose any consumers ! > i didn't said my OS will be a normal one !!! > > > Ed McGettigan > > Xilinx Inc. > > if i spend too much time to know how to use those fpgas without using > your softwares in some OS i don't want to use, i may have a > functionnal demo for my project before :http://opencores.org/project,smar= t-non-binary-computing,overview > and once tasted your fgpas will not be as good mine ! > so i'll not try to use them as i want in the end ! > np my 5 spartan 3E 500k will be used even with your vhdl usage > restriction > anyway as you can restrict small consumers to use the hardware you > sell as you want i will restrict all my projects to be open only for > non-xilinx&affiliated companies ! > sadly for you i didn't bought altera, you have one week to decide if > you can publish the bit-stream specs of old products before i restrict > all my open-sources projects with a "no-xilinx&al license" ! > if xilinx can't respect me cause i'm not a big buyer it's not my > problem ! > thanks again Ed ! Christophe, It appears that you have your mind set on a specific course of action. It really isn't clear what that course of action is as your responses and comments in this and other threads over the last couple of days are quite confusing. Potentially this due to French/English language issues, but some of it appears to be that you don't understand some basic FPGA, logic and hardware design concepts. In a recent post you said "how can you know what is difficult with another point of view you don't have ?" Take a moment and consider this along with the replies that you have received from a diverse set of people here. If you think that you will get farther in your goal by using FPGAs from Altera, Lattice, Microsemi (aka Actel), or QuickLogic then you should absolutely switch over. However, Xilinx has had a long history supporting reconfigurable computing research. I was the main driver behind the development and release of first Virtex bitstream architecture documentation that resulted in XAPP151 and XAPP153. Both of these documents opened the bitstream format to enable partial reconfiguration design methods for use by Xilinx customers and researchers. Equivalent information that is in XAPP151 can now be found in each FPGA family's Configuration User Guide. The same level of bistream architecture disclosure or partial reconfiguration support is not available from any other FPGA vendor. However what you will not find in this material are direct relationships between any specific bit and a specific functionality. This information is extremely complex, has a high level of variability within a FPGA family and changes completely from one family to another. This isn't the same as documentating an ISA and a register map for a CPU or peripheral device that has one task and runs at one clock frequency it would be 10,000 times more complex to fully document the entire FPGA configuration map. There were attempts to develop non-ISE design flows and a research vehicle called Jbits was developed and released by Xilinx that supported some of the Virtex, Virtex-E and Virtex-II families (no support for Spartan-3E that I am aware of). Jbits was not extremely useful beyond academic research as it lacked elements that would allow for building a robust and reliable design, features like simulation and timing analysis. No similiar vehicle has ever been released by another FPGA vendor. Best of luck in your endeavor, Ed McGettigan -- Xilinx Inc.Article: 151164
On 12 Mrz., 19:10, geobsd <geobsd...@gmail.com> wrote: > is my brain ok !?! > ;) Finally, the correct question... (Sorry, could not resist, please do not take it personally ;-) If you really want to learn something about FPGA, sell your 5 Spartans and buy a cheap evaluation-kit instead... But beside FPGA, I think you should also learn some other lessons, e.g. how to deal with people that want to help you. E.g. giving a Xilinx-representative a ultimatum for suppling there source-code is plain stupid: It is like wanting to get the recipe from Coca-Cola within 1 week, otherwise you will never ever buy a coke again. Before you even ever drank a coke, because you didn't figure out how to. I think you should try to get a more realistic and less emotional view of things. Regards, ThomasArticle: 151165
Ed, i insist on special things because the usual ones are ok with xilinx yes my english is bad ! a programmable device is programmed to "work" even if it's not the usual langage ! i don't think else fpga makers are best i don't even need a full doc of the map, just the complet map the same you have in your compiler > Best of luck in your endeavor, thanks EdArticle: 151166
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: (snip) > The same level of bistream architecture disclosure or partial > reconfiguration support is not available from any other FPGA vendor. > However what you will not find in this material are direct > relationships between any specific bit and a specific functionality. > This information is extremely complex, has a high level of variability > within a FPGA family and changes completely from one family to > another. This isn't the same as documentating an ISA and a register > map for a CPU or peripheral device that has one task and runs at one > clock frequency it would be 10,000 times more complex to fully > document the entire FPGA configuration map. Well, some processor descriptions are pretty complicated these days, so 10,000 might be a little high. I have the intel books for itanium, and it isn't just a little more than IA32. Also, since the FPGA is made up of a large number of CLBs, each pretty much the same, you don't need to separately describe each. In the XC4000 days, I was working on a design that would have used a dynamic bitstream, though most of it was data in look-up tables. That was for a systolic-array search processor, where the search pattern data was loaded into little ROMs. Some that I thought of also needed different configurations for the carry chain, but that used the XC4000 style carry chain, which wasn't continued into later families. > There were attempts to develop non-ISE design flows and a research > vehicle called Jbits was developed and released by Xilinx that > supported some of the Virtex, Virtex-E and Virtex-II families (no > support for Spartan-3E that I am aware of). Jbits was not extremely > useful beyond academic research as it lacked elements that would allow > for building a robust and reliable design, features like simulation > and timing analysis. No similiar vehicle has ever been released by > another FPGA vendor. I don't know what the OP is trying to do at all. I am still interested in systolic arrays, some of which require dynamic generation of LUT (ROM) data. The rest of the bitstream is constant. -- glenArticle: 151167
> I think you should try to get a more realistic and less emotional view > of things. i'm realistic, do you have an idea of easy i am ? re ThomasArticle: 151168
hi glen for now i'm searching a pcb for the 5 spartan (hard) i'll look later on your arrays going to sleep ! i hope there will be else interesting comments on dynamic bit-stream @bient=F4tArticle: 151169
On Mar 12, 5:46 pm, geobsd <geobsd...@gmail.com> wrote: > > I think you should try to get a more realistic and less emotional view > > of things. > > i'm realistic, do you have an idea of easy i am ? > re Thomas I think I have an idea of what you are looking to do. You want to connect an FPGA to your tablet computer to use as an attached coprocessor that is programmed on the fly by the CPU in the tablet. But not just "programmed", the programming is to be calculated on the fly as well. You have made two mistakes. One is thinking that you would find a way to directly connect FPGA chips directly to a tablet computer. Instead, you should buy a board or other unit that has an interface to your tablet computer, such as Ethernet or USB. Otherwise how would you ever hope to connect the FPGA? Even if your tablet has some internal interface that you want to use, how would you expect to connect that to the FPGA which is only designed to be soldered onto a PCB? Some internal interfaces a tablet might have are a memory socket (likely filled with memory though) and SATA which would be a nice high speed interface, but very complex to add to an FPGA. So your external interfaces are most likely the best way to go. The second mistake is thinking that you could generate a bitstream without running one of the standard OS like Linux or Windows. Yes, the FPGA makers hold the bitstream format as a proprietary secret. Opening this up would create some competition concerns, but more likely they are worried that bad bitstreams would cause reliability issues since a bad bitstream has potential of frying an FPGA. It is certainly possible to generate an EDIF description of a design complete with location info for each logic block within a design, at least I belief that is true. To turn this into a bitstream requires at least some proprietary software which will only run on Linux or Windows. However... if you have the perseverance, it should be possible to analyze small changes in the source and analyze the changes in the bitstream to learn the location and function of each control point. It would be a huge job and I believe others have attempted it with some degree of success. Further this changes with each new family if not each part. So there it is in a nutshell. If you really want to do it, you just need to get a free version of the tools and start cranking out designs until your fingers and eyes bleed! Or maybe you can figure out a way to automate this? Good luck! RickArticle: 151170
geobsd wrote: >>> thanks again Ed ! >> we're all watching you and wishing you good luck. >> you seem to be passionate and driven by ideals, >> so at least something good must result from this :-) > i am, i have no hate for Ed, the poor should not really understand why > i'm not happy with my fpga... i think he understands your problem, which explains his latest, very detailed and empathic answer. FPGA are technology marvels but they come at a high initial cost, for example, overall, I spent more for computer hardware and software than for FPGA chips themselves. it's a big investment at many levels, time, money, mentally... But when it's well done, and after quite a lot of time (sometimes years) it's really great and empowering and you appreciate that several restrictions of the vendors are nothing compared to the design freedom they provide you with. We understand that you expect to be able to use the chips that you have bought, we all expect that, but we often have to compromise and the FPGA field is the harshest domain in this respect. I don't lose hope, as some FPGA startups sometimes appear with interesting alternatives. For example, SiliconBlue had done some things right, but i have had no contact since at least a year :-( > anyway i usualy do what i said, maybe i'm nothing maybe not we become what we do :-) so you know what you have to do now. If you are in/around Paris, there were FPGA workshops at the /tmp/lab where newcomers were introduced to the S3 (by coincidence= ). http://www.tmplab.org/2009/10/21/fpga-workshop-4-behind-the-scenes-novemb= er-8/ No idea if S=E9bastien / Lekernel will organise other workshops like this= but there may be hackers/bricoleurs around Paris who could help you a bit= =2E I may have another address or two. Nobody is going to do things for you, however, but at least certain kinds= of knowledge are free :-) > @bient=F4t yg --=20 http://ygdes.com / http://yasep.orgArticle: 151171
hi rick > I think I have an idea of what you are looking to do. =A0You want to > connect an FPGA to your tablet computer to use as an attached > coprocessor that is programmed on the fly by the CPU in the tablet. > But not just "programmed", the programming is to be calculated on the > fly as well. the plan was to have a pcb where put the 5 spartan and put it in the tablet. for some computing your description is ok ! > > You have made two mistakes. i have made more, but learning come with it (often) > > The second mistake is thinking that you could generate a bitstream > without running one of the standard OS like Linux or Windows. =A0Yes, > the FPGA makers hold the bitstream format as a proprietary secret. > Opening this up would create some competition concerns, but more > likely they are worried that bad bitstreams would cause reliability > issues since a bad bitstream has potential of frying an FPGA. i think if users make a bad use of fgpa the makers are not concerned the competition concerns are not a real problem here, fpga makers surelly use strong engines to see the work of competitors > =A0It is > certainly possible to generate an EDIF description of a design > complete with location info for each logic block within a design, at > least I belief that is true. =A0To turn this into a bitstream requires > at least some proprietary software which will only run on Linux or > Windows. =A0However... if you have the perseverance, it should be > possible to analyze small changes in the source and analyze the > changes in the bitstream to learn the location and function of each > control point. =A0It would be a huge job and I believe others have > attempted it with some degree of success. =A0Further this changes with > each new family if not each part. i understand 2 way more to know my fgpa model in full but it will be long with public map fgpas could reach perfection ! > > So there it is in a nutshell. =A0If you really want to do it, you just > need to get a free version of the tools and start cranking out designs > until your fingers and eyes bleed! =A0Or maybe you can figure out a way > to automate this? i will try my friend > > Good luck! thanks RickArticle: 151172
I'm looking for cards for a couple of different applications, dual 10G Ehternet (requires dual SFP+) connectors and QDR InfiniBand (dual QSFP+). Both applications require 10G SerDes which means either a Stratix4GT or a Virtex6HXT, either is acceptable. Hitechglobal has some interesting cards that meet these requirements, what other vendors should I explore?Article: 151173
On Mar 13, 7:49=A0am, geobsd <geobsd...@gmail.com> wrote: > hi rick > > > I think I have an idea of what you are looking to do. =A0You want to > > connect an FPGA to your tablet computer to use as an attached > > coprocessor that is programmed on the fly by the CPU in the tablet. > > But not just "programmed", the programming is to be calculated on the > > fly as well. > > the plan was to have a pcb where put the 5 spartan and put it in the > tablet. > for some computing your description is ok ! Again, there are mistaken assumptions in this idea. First making a PCB for an FPGA is not the full extent of connecting an FPGA to any computer, but it is certainly one of the most painful ways of connecting an FPGA to a computer. It is expensive, time consuming and laborious. Much easier to connect is a USB device. The other issue is that you have no idea what interface you will find inside your tablet or if there will be one at all! The idea of plopping an FPGA inside the tablet is not a good one unless you have lots of money to burn. > > You have made two mistakes. > > i have made more, but learning come with it (often) > > > The second mistake is thinking that you could generate a bitstream > > without running one of the standard OS like Linux or Windows. =A0Yes, > > the FPGA makers hold the bitstream format as a proprietary secret. > > Opening this up would create some competition concerns, but more > > likely they are worried that bad bitstreams would cause reliability > > issues since a bad bitstream has potential of frying an FPGA. > > i think if users make a bad use of fgpa the makers are not concerned Yes, they are very concerned. They have said so. If a customer buys hundreds or thousands of chips and then wants to return them because they don't work right and the vendor finds they are all damaged internally, likely from a bad bitstream, how are they to prove it was because of the customer using a self designed tool and not because of the vendor supplied tool? No, they don't care about you doing this since they likely would never accept a return from you anyway. But they have to work with very high volume customers who, if the info was available, may well roll their own tools and cause the FPGA maker all sorts of difficulties. The possible problems are actually much larger than this. Don't assume you understand what it is like to be the vendor. > the competition concerns are not a real problem here, fpga makers > surelly use strong engines to see the work of competitors> =A0 Again, don't assume you know the vendor. I can't say if the competition does this or not. I do know it is outside of the tool license and I strongly suspect it is not worth the effort of the competitors since there a better ways to learn what they want to know... like reading patents. > > It is > > certainly possible to generate an EDIF description of a design > > complete with location info for each logic block within a design, at > > least I belief that is true. =A0To turn this into a bitstream requires > > at least some proprietary software which will only run on Linux or > > Windows. =A0However... if you have the perseverance, it should be > > possible to analyze small changes in the source and analyze the > > changes in the bitstream to learn the location and function of each > > control point. =A0It would be a huge job and I believe others have > > attempted it with some degree of success. =A0Further this changes with > > each new family if not each part. > > i understand 2 way more to know my fgpa model in full but it will be > long > with public map fgpas could reach perfection ! > > > So there it is in a nutshell. =A0If you really want to do it, you just > > need to get a free version of the tools and start cranking out designs > > until your fingers and eyes bleed! =A0Or maybe you can figure out a way > > to automate this? > > i will try my friend > > > Good luck! > > thanks Rick Let us know how you get on. Others have started this effort before. I think there is some sort of a Java tool that lets you manipulate the final design file before it is turned into a bitstream. I have read about others using that to make changes to placed and routed designs to reverse engineer the bitstream. Once upon a time, there was an FPGA from Xilinx that was intended to be used for this sort of work. The bitstream was public, IIRC and the device was designed to prevent damage if the bitstream was corrupted or just junk. It was popular with the schools, but they ended up dropping the entire line. I guess the business model for it dried up. RickArticle: 151174
> Again, there are mistaken assumptions in this idea. =A0First making a > PCB for an FPGA is not the full extent of connecting an FPGA to any > computer, but it is certainly one of the most painful ways of > connecting an FPGA to a computer. =A0It is expensive, time consuming and > laborious. =A0Much easier to connect is a USB device. > > The other issue is that you have no idea what interface you will find > inside your tablet or if there will be one at all! > > The idea of plopping an FPGA inside the tablet is not a good one > unless you have lots of money to burn. i will let this idea in a corner the time i learn&practice electronic to be able to do it myself if i can ... > > > Yes, they are very concerned. =A0They have said so. =A0If a customer buys > hundreds or thousands of chips and then wants to return them because > they don't work right and the vendor finds they are all damaged > internally, likely from a bad bitstream, how are they to prove it was > because of the customer using a self designed tool and not because of > the vendor supplied tool? i didn't think about not honnest peoples sorry rick > Again, don't assume you know the vendor. =A0I can't say if the > competition does this or not. =A0I do know it is outside of the tool > license and I strongly suspect it is not worth the effort of the > competitors since there a better ways to learn what they want to > know... like reading patents. not everything is patented for example in my country (france) if you import things to study them, and have an accord, you have no taxe&duty to pay ! i assume to not even know myself (without lie) > > > > > Let us know how you get on. =A0Others have started this effort before. > I think there is some sort of a Java tool that lets you manipulate the > final design file before it is turned into a bitstream. =A0I have read > about others using that to make changes to placed and routed designs > to reverse engineer the bitstream. i didn't saw it yet > > Once upon a time, there was an FPGA from Xilinx that was intended to > be used for this sort of work. =A0The bitstream was public, IIRC and the > device was designed to prevent damage if the bitstream was corrupted > or just junk. =A0It was popular with the schools, but they ended up > dropping the entire line. =A0I guess the business model for it dried > up. too bad ! while i have no pcb i can't try on those spartan :( i will find the less expensive i can fpga board to begin soon with fpga ;) thanks Rick
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