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Please inform us if You buy that one from EBV and tell the price :) Some time ago, they wanted 100EU for it, but later it became 170EU. <dormanpeter1@gmail.com> wrote in message news:fffd4bd1-3517-4852-a1b3-dfd9f3f3fffc@p24g2000vbl.googlegroups.com... Thank you for everyone who responded! This last one seems to be good for this purpose. --- Peter On márc. 5, 11:48, Socrates <mail...@gmail.com> wrote: > http://www.ebv.com/index.php?id=162&ct_ref=u103-c84&tx_ebvproductfe_pi1[uid]=2011 > > Smallest Cyclone IV GX, DDR2 RAM, embedded USB blaster and 24pins I/Os > - 170 EU @ EBV.Article: 151126
On Tuesday, March 8, 2011 3:04:49 PM UTC-5, Nicolas Matringe wrote: > Le 08/03/2011 19:02, PovTruffe a =EF=BF=BDcrit : > > Hi, > > > > I am new to the FPGA world and trying to design my first Spartan-3E boa= rd > > (mostly using "copy and paste"...). > > > > Why are there 2 resistors on inputs M0 and M2 on the following schemati= c? > > http://cjoint.com/?1dis6y5LNzz (Basys 2 board) > > > > By the way why is there a resistor on M1 ? Direct grounding is not OK ? >=20 > Hi and welcome to this wonderful world ;-) >=20 > The configuration selection pins are also user pins after configuration.= =20 > If you want to use them as IOs you won't like them to be directly=20 > connected to ground or Vcc. >=20 > Nicolas Be careful when using pull-down resistors on the Spartan 3 series. The internal "weak" pullups are not the wimpy 50K+ Ohm equivalent pullups you find in most circuits. The actual value depends on the I/O voltage supply, but can be as low as 5K ohms, meaning you need 1K or less to get a solid logic low using an external pull-down. Anyway your best place to start is the Spartan 3 series configuration users' guide. This shows recommended connections for all of the available modes of configuration. -- GaborArticle: 151127
On Mar 3, 2:38=A0am, Ale=9A Svetek <ales.sve...@gmDELail.com> wrote: > On 03/03/2011 01:01, DaMunky89 wrote: > > > > > Alright, so I'm trying to compile the example projects from xapp1026, > > following the instructions included in xapp1026.pdf: > >www.xilinx.com/support/documentation/application.../xapp1026.pdf > > > I'm using the Xilinx SDK, and successfully managed to import the > > Hardware Platform Specifications and four xapp1026 example projects. > > My current setup is as follows: > > > OS: Windows 7 x64 > > SDK Release Version: 12.3 Build SDK_MS3.70d > > > When I try to "build all", I get the following error: > > > **** Build of configuration Debug for project sock_apps **** > > > make all > > Building file: ../dispatch.c > > Invoking: MicroBlaze gcc compiler > > mb-gcc -Wall -O0 -g3 -c -fmessage-length=3D0 -mxl-soft-mul -MMD -MP - > > MF"dispatch.d" -MT"dispatch.d" -o"dispatch.o" "../dispatch.c" > > ../dispatch.c:19:23: error: lwip/inet.h: No such file or directory > > ../dispatch.c:20:26: error: lwip/ip_addr.h: No such file or directory > > ../dispatch.c: In function print_headers : > > ../dispatch.c:27: warning: implicit declaration of function > > xil_printf > > ../dispatch.c:32: warning: implicit declaration of function > > print_echo_app_header > > ../dispatch.c:35: warning: implicit declaration of function > > print_rxperf_app_header > > ../dispatch.c:38: warning: implicit declaration of function > > print_txperf_app_header > > ../dispatch.c:41: warning: implicit declaration of function > > print_tftp_app_header > > ../dispatch.c:44: warning: implicit declaration of function > > print_web_app_header > > ../dispatch.c: In function launch_app_threads : > > ../dispatch.c:60: warning: implicit declaration of function > > sys_thread_new > > ../dispatch.c:62: error: DEFAULT_THREAD_PRIO undeclared (first use > > in this function) > > ../dispatch.c:62: error: (Each undeclared identifier is reported only > > once > > ../dispatch.c:62: error: for each function it appears in.) > > make: *** [dispatch.o] Error 1 > > > It looks like it's complaining that I haven't added lwip to the > > include path. The xapp1026 instructions don't mention anything about > > this, so I thought some kind of Xilinx distribution of lwip was > > already included, but I guess not. Therefore, my question overall is, > > how do I go about adding lwip to my Xilinx SDK in such a way that I > > can get these projects to build? If that isn't the solution to these > > errors, what is? > > It sounds like you didn't include lwip library in your BSP. It is not > included by default. > > You can add it by expanding your BSP in Project Explorer and double > click *.mss file. After that click Modify this BSP's Settings and then > include lwip130. You should also modify lwip's settings to suite your nee= ds. > > ~Ale Isn't the BSP configured as part of the hardware specification in the EDK? Xilinx provides a pre-written hardware specification exclusively for use with the xapp1026 exercises. I don't see why they would have neglected to include the completely necessary lwip packages in that.. is there perhaps somewhere else I have to add these, as well?Article: 151128
Philippe posted: > > 1. There is no clear definition of what a "benchmark result" is, > you don't know when you are breaching the contract. > I agree that those clauses are a bit much. FYI, about a decade ago, there was some vendor clarification regarding this issue on comp.arch.fpga in the context of posting _single_ vendor Brand S result variations vs. tool settings/coding style: In 2001, I had posted [1] a summary of LUT counts vs. tool settings on a thread about big counters: > >And tweaking counter size/target frequency, gives: > > Synplify Synplify > CNT_MSB Frequency LUT count > __________________________________________ > 55 77 57 > 55 78 110 > > 31 95 33 > 31 96 46 > 31 122 46 > 31 123 83 > On a nearby thread about license benchmarking clauses [2], Andy P. posted [3], somewhat tongue-in-cheek : > > Uh oh! The person who posted Synplify's results for that > 56-bit counter problem is in line for an ass-whooping! > I replied [4] in part: > > Personally, I wouldn't consider answering a question on how > to make a counter synthesize better to be a "benchmark"... > Then Ken M. of Brand S, formerly known as Brand S, posted [5]: > > We don't consider it to be a "benchmark" either. > Brian Davis [1] post from thread "High level synthesis will never work well" http://groups.google.com/group/comp.arch.fpga/msg/01e9d02b8e85983d [2] Thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/a201fc7f4a639215 [3] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/6f9694e180581202 [4] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/172b3fbcb1ffe4a5 [5] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/52f4c2a915b383d3Article: 151129
On Tue, 8 Mar 2011 18:22:22 -0800 (PST), Brian Davis <brimdavis@aol.com> wrote: >Philippe posted: >> >> 1. There is no clear definition of what a "benchmark result" is, >> you don't know when you are breaching the contract. >> > I agree that those clauses are a bit much. Maybe an answer is for someone to set up a site to post benchmark results anonymously.Article: 151130
"Gabor" <gabor@alacron.com> a écrit : > Be careful when using pull-down resistors on the > Spartan 3 series. The internal "weak" pullups > are not the wimpy 50K+ Ohm equivalent pullups > you find in most circuits. The actual value > depends on the I/O voltage supply, but can be as > low as 5K ohms, meaning you need 1K or less to > get a solid logic low using an external pull-down. > Anyway your best place to start is the Spartan 3 > series configuration users' guide. This shows > recommended connections for all of the available > modes of configuration. Ouch ! yet another several hundred pages document... I have thousands of pages to study. Learning FPGAs is really a big step, even for experienced microcontroller systems designers.Article: 151131
>On Tue, 8 Mar 2011 18:22:22 -0800 (PST), Brian Davis <brimdavis@aol.com> wrote: > >>Philippe posted: >>> >>> 1. There is no clear definition of what a "benchmark result" is, >>> you don't know when you are breaching the contract. >>> >> I agree that those clauses are a bit much. > >Maybe an answer is for someone to set up a site to post benchmark results anonymously. > Somebody already did! http://www.deepchip.com/ --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151132
> >Ouch ! yet another several hundred pages document... >I have thousands of pages to study. Learning FPGAs is really a >big step, even for experienced microcontroller systems designers. > Yes. That's why we hardware writers are so well paid! ;-) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151133
Hi Brian, Thanks for pointing to this conversation from 2001. It seems that EDA vendors are not interested in enforcing this clause for small benchmark results. Still it gives them a stick to hit you with if you would ever publish something serious. That leaves al the benchmarking work for the brave and those with little to loose. -- Philippe http://www.sigasi.comArticle: 151134
hi all i stupidly bought 5 spartan 3E when i just understoud the power of fgpa ! so now i need a not expensive fgpa-pcb maker to put the 5 spartan in my tablet also i need the bitstream spec to directly use fgpas on my tablet ! unlike else *pu i can't find the doc to direct programming it and xilinx give no answer to not affiliated people !!! thanks _________________ http://opencores.org/project,smart-non-binary-computing,overviewArticle: 151135
On Mar 8, 5:58=A0pm, DaMunky89 <shwankymu...@gmail.com> wrote: > On Mar 3, 2:38=A0am, Ale=9A Svetek <ales.sve...@gmDELail.com> wrote: > > > > > > > > > > > On 03/03/2011 01:01, DaMunky89 wrote: > > > > Alright, so I'm trying to compile the example projects from xapp1026, > > > following the instructions included in xapp1026.pdf: > > >www.xilinx.com/support/documentation/application.../xapp1026.pdf > > > > I'm using the Xilinx SDK, and successfully managed to import the > > > Hardware Platform Specifications and four xapp1026 example projects. > > > My current setup is as follows: > > > > OS: Windows 7 x64 > > > SDK Release Version: 12.3 Build SDK_MS3.70d > > > > When I try to "build all", I get the following error: > > > > **** Build of configuration Debug for project sock_apps **** > > > > make all > > > Building file: ../dispatch.c > > > Invoking: MicroBlaze gcc compiler > > > mb-gcc -Wall -O0 -g3 -c -fmessage-length=3D0 -mxl-soft-mul -MMD -MP - > > > MF"dispatch.d" -MT"dispatch.d" -o"dispatch.o" "../dispatch.c" > > > ../dispatch.c:19:23: error: lwip/inet.h: No such file or directory > > > ../dispatch.c:20:26: error: lwip/ip_addr.h: No such file or directory > > > ../dispatch.c: In function print_headers : > > > ../dispatch.c:27: warning: implicit declaration of function > > > xil_printf > > > ../dispatch.c:32: warning: implicit declaration of function > > > print_echo_app_header > > > ../dispatch.c:35: warning: implicit declaration of function > > > print_rxperf_app_header > > > ../dispatch.c:38: warning: implicit declaration of function > > > print_txperf_app_header > > > ../dispatch.c:41: warning: implicit declaration of function > > > print_tftp_app_header > > > ../dispatch.c:44: warning: implicit declaration of function > > > print_web_app_header > > > ../dispatch.c: In function launch_app_threads : > > > ../dispatch.c:60: warning: implicit declaration of function > > > sys_thread_new > > > ../dispatch.c:62: error: DEFAULT_THREAD_PRIO undeclared (first use > > > in this function) > > > ../dispatch.c:62: error: (Each undeclared identifier is reported only > > > once > > > ../dispatch.c:62: error: for each function it appears in.) > > > make: *** [dispatch.o] Error 1 > > > > It looks like it's complaining that I haven't added lwip to the > > > include path. The xapp1026 instructions don't mention anything about > > > this, so I thought some kind of Xilinx distribution of lwip was > > > already included, but I guess not. Therefore, my question overall is, > > > how do I go about adding lwip to my Xilinx SDK in such a way that I > > > can get these projects to build? If that isn't the solution to these > > > errors, what is? > > > It sounds like you didn't include lwip library in your BSP. It is not > > included by default. > > > You can add it by expanding your BSP in Project Explorer and double > > click *.mss file. After that click Modify this BSP's Settings and then > > include lwip130. You should also modify lwip's settings to suite your n= eeds. > > > ~Ale > > Isn't the BSP configured as part of the hardware specification in the > EDK? Xilinx provides a pre-written hardware specification exclusively > for use with the xapp1026 exercises. I don't see why they would have > neglected to include the completely necessary lwip packages in that.. > is there perhaps somewhere else I have to add these, as well? I agree that the flow is kind of confusing, since "BSP" means different things to HW & SW. Xilinx has been trying to decouple the HW dev from the SW dev in more recent versions of EDK, reflected by XPS and SDK. The BSP in the HW case refers what is physically available on the target platform. The BSP you configure in the SDK is the software setup for the platform -- OS / stand-alone, file system, other libraries (including lwIP), etc. All you need to do to get your application access to the lwIP library is to click the appropriate check box in the SW BSP in the SDK (as long as your hardware is configured correctly i.e. a timer for the TCP callbacks has been included). MArticle: 151136
On 10/03/2011 03:45, MBodnar wrote: > On Mar 8, 5:58 pm, DaMunky89<shwankymu...@gmail.com> wrote: >> On Mar 3, 2:38 am, Aleš Svetek<ales.sve...@gmDELail.com> wrote: >> >> >> >> >> >> >> >> >> >>> On 03/03/2011 01:01, DaMunky89 wrote: >> >>>> Alright, so I'm trying to compile the example projects from xapp1026, >>>> following the instructions included in xapp1026.pdf: >>>> www.xilinx.com/support/documentation/application.../xapp1026.pdf >> >>>> I'm using the Xilinx SDK, and successfully managed to import the >>>> Hardware Platform Specifications and four xapp1026 example projects. >>>> My current setup is as follows: >> >>>> OS: Windows 7 x64 >>>> SDK Release Version: 12.3 Build SDK_MS3.70d >> >>>> When I try to "build all", I get the following error: >> >>>> **** Build of configuration Debug for project sock_apps **** >> >>>> make all >>>> Building file: ../dispatch.c >>>> Invoking: MicroBlaze gcc compiler >>>> mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -mxl-soft-mul -MMD -MP - >>>> MF"dispatch.d" -MT"dispatch.d" -o"dispatch.o" "../dispatch.c" >>>> ../dispatch.c:19:23: error: lwip/inet.h: No such file or directory >>>> ../dispatch.c:20:26: error: lwip/ip_addr.h: No such file or directory >>>> ../dispatch.c: In function print_headers : >>>> ../dispatch.c:27: warning: implicit declaration of function >>>> xil_printf >>>> ../dispatch.c:32: warning: implicit declaration of function >>>> print_echo_app_header >>>> ../dispatch.c:35: warning: implicit declaration of function >>>> print_rxperf_app_header >>>> ../dispatch.c:38: warning: implicit declaration of function >>>> print_txperf_app_header >>>> ../dispatch.c:41: warning: implicit declaration of function >>>> print_tftp_app_header >>>> ../dispatch.c:44: warning: implicit declaration of function >>>> print_web_app_header >>>> ../dispatch.c: In function launch_app_threads : >>>> ../dispatch.c:60: warning: implicit declaration of function >>>> sys_thread_new >>>> ../dispatch.c:62: error: DEFAULT_THREAD_PRIO undeclared (first use >>>> in this function) >>>> ../dispatch.c:62: error: (Each undeclared identifier is reported only >>>> once >>>> ../dispatch.c:62: error: for each function it appears in.) >>>> make: *** [dispatch.o] Error 1 >> >>>> It looks like it's complaining that I haven't added lwip to the >>>> include path. The xapp1026 instructions don't mention anything about >>>> this, so I thought some kind of Xilinx distribution of lwip was >>>> already included, but I guess not. Therefore, my question overall is, >>>> how do I go about adding lwip to my Xilinx SDK in such a way that I >>>> can get these projects to build? If that isn't the solution to these >>>> errors, what is? >> >>> It sounds like you didn't include lwip library in your BSP. It is not >>> included by default. >> >>> You can add it by expanding your BSP in Project Explorer and double >>> click *.mss file. After that click Modify this BSP's Settings and then >>> include lwip130. You should also modify lwip's settings to suite your needs. >> >>> ~Ale >> >> Isn't the BSP configured as part of the hardware specification in the >> EDK? Xilinx provides a pre-written hardware specification exclusively >> for use with the xapp1026 exercises. I don't see why they would have >> neglected to include the completely necessary lwip packages in that.. >> is there perhaps somewhere else I have to add these, as well? > > I agree that the flow is kind of confusing, since "BSP" means > different things to HW& SW. Xilinx has been trying to decouple the > HW dev from the SW dev in more recent versions of EDK, reflected by > XPS and SDK. The BSP in the HW case refers what is physically > available on the target platform. > > The BSP you configure in the SDK is the software setup for the > platform -- OS / stand-alone, file system, other libraries (including > lwIP), etc. All you need to do to get your application access to the > lwIP library is to click the appropriate check box in the SW BSP in > the SDK (as long as your hardware is configured correctly i.e. a > timer for the TCP callbacks has been included). > > M Michael is completely correct regarding the BSP above. However, the compilation problem that you have been seeing is related to the imported application projects, which are not configured correctly if you just import the projects into SDK. Somehow the inferred options are not picked up by the import. What you should do to get the compilation working is to manually specify include folder in compiler settings and also specify libraries and their search path in linker settings. More specifically, right click on the project, select "C/C++ build settings", then on the left side select "C/C++ build" -> "Settings". Under compiler settings select "Directories" and add the include path from the BSP (or platform, as is it called in this XAPP). Then go to linker settings below and select "Libraries". At Libraries (-l) field add "lwip4" and "xilkernel" and at Library search path point to lib folder from the BSP (or platform, as is it called in this XAPP). I always configure my project manually so I didn't stumble upon this problem before, but I just tried the import approach and managed to compile the project with the additional steps as described above. HTH, ~ AlesArticle: 151137
>hi all >i stupidly bought 5 spartan 3E when i just understoud the power of >fgpa ! >so now i need a not expensive fgpa-pcb maker to put the 5 spartan in >my tablet >also i need the bitstream spec to directly use fgpas on my tablet ! >unlike else *pu i can't find the doc to direct programming it and >xilinx give no answer to not affiliated people !!! >thanks >_________________ >http://opencores.org/project,smart-non-binary-computing,overview > The bitstream format is not published. Download the ISE Webpack tools to enable you to generate a bitstream. However, your best plan is probably to sell off the chips. Bespoke PCB design and build is both difficult and expensive, especially for hobbyists. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151138
On 8 Mrz., 16:09, Philippe <philippe.f...@gmail.com> wrote: > It was interesting to read some synthesis benchmarking results on > comp.lang.vhdl last week. I feel it's high time that EDA vendors drop > the anti-benchmarking clauses from their license agreements: Just make sure to purchase software in a way where that license agreement ist not included in a contract. A sales contract is finalized when goods and money have been exchanged. Afterwards no clauses can be added to the contract by one side alone. At least in Germany it is well established by court that this holds for software sales, and other countries have similar contract law. So as long as the clause is not included in a click through contract during a download purchase, or is presented to you before purchase in another way, the clause does not become part of the contract. Clauses presented during installation are irrelevant. Also note: Your contract is with the reseller, not with the vendor of the software. So information on the vendor homepage is irrelavant. For private users (not companies) the clause anyway is likely to violate EU law, because it is a surprising clause. KoljaArticle: 151139
"geobsd" <geobsd.os@gmail.com> wrote in message news:50d241f8-27a5-4308-8b81-1e515a045346@q14g2000vbf.googlegroups.com... > hi all > i stupidly bought 5 spartan 3E when i just understoud the power of > fgpa ! Just the FPGAs? > so now i need a not expensive fgpa-pcb maker to put the 5 spartan in > my tablet What tablet? What interface? > also i need the bitstream spec to directly use fgpas on my tablet ! > unlike else *pu i can't find the doc to direct programming it and It's not a CPU it's a programmable logic device. You don't program it you define how the logic will operate and configure it. > xilinx give no answer to not affiliated people !!! > thanks There's plenty of information on the web site! :-) Nial.Article: 151140
hi all stupid questions for PovTruffe (forgive me) will you make it yourself (how) or by a pcb maker (where) ? [not very related] and what do you think about add-on cards (where only fpga live) thanksArticle: 151141
> Just the FPGAs? yes ! > What tablet? a chineese tablet 8" with a freescale IMX5 > What interface? well i'm not sure what's in it without open it (i will destroy the back soon) usb-otg, wifi sure > It's not a CPU it's a programmable logic device. You don't program it you > define how the logic will operate and configure it. that's what i call programme fgpa, you can't programme cpu you programme on it, we are ok here ! > There's plenty of information on the web site! i didn't found good information to direct use of fpga without made bitstream yet, and my tablet will run my OS, ISE&al are dead for me ! thanks NialArticle: 151142
> The bitstream format is not published. that's a shame ! unlike else *pu we can't use freely ! > Download the ISE Webpack tools to enable you to generate a bitstream. i'll do this in last thing if i don't decode the spec by myself :( > However, your best plan is probably to sell off the chips. must i suicide too ? > Bespoke PCB > design and build is both difficult and expensive, especially for > hobbyists. what about reflow oven ? thanks RCInghamArticle: 151143
Alex wrote: > Hello, I'm a novice in FPGA, so please forgive me if I'm asking simple > questions. > > I've got Spartan-3E Evaluation Kit and I need to realize a programmable > generator of pulses of nanosecond duration. The problem is as follows: I've > got a trigger pulse and I need to generate a TTL pulse of nanosecond > duration with programmable width (with step about 200-500 ps, range 2 ns - > 100 ns (for example)) and programmable delay (with 200-500 ps step). The > maximum delay from in to out must not be more than 10 ns. > Actually I need to realize a wide-range pulse generator, but as I > understand there is no problem generate wide pulses (more than 100 ns) with > larger step (10 ns) working in synchroneous regime and using clock. But for > narrow pulses I think I should work in asynchroneous regime. I could use > elements with known delay and link them into a chain. > If it possible to realize such project using Spartan-3E FPGA chip, or maybe > I need something from Virtex family. > > Thank you in advance. > Alex. > > > > > > --------------------------------------- > Posted through http://www.FPGARelated.com Ask John Larkin over in sci.electronics.design. Basically, sub-ns resolution delays with large (up to seconds) total delays are done with mixed signal verniers coupled to digital counter arrangements. The counter stuff is easy. I have yet to fully grasp how the vernier stuff works, while also having fully asynchronous trigger-ability. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 151144
Mr.CRC <crobcBOGUS@removethissbcglobal.net> wrote: (snip) >> I've got Spartan-3E Evaluation Kit and I need to realize a programmable >> generator of pulses of nanosecond duration. The problem is as follows: I've >> got a trigger pulse and I need to generate a TTL pulse of nanosecond >> duration with programmable width (with step about 200-500 ps, range 2 ns - >> 100 ns (for example)) and programmable delay (with 200-500 ps step). The >> maximum delay from in to out must not be more than 10 ns. (snip) > Ask John Larkin over in sci.electronics.design. > Basically, sub-ns resolution delays with large (up to seconds) total > delays are done with mixed signal verniers coupled to digital counter > arrangements. I used to know about a TDC, (see wikipedia Time_to_digital_converter ) which works by charging a capacitor for the appropriate amount of time, and then measuring the voltage with an ADC. That is used for the fine timing (low eight bits), and a counter for the course timing. I am not sure how the analog part is calibrated, but it seems to me that it could be done with a PLL. I believe that a similar system could be used in reverse. In an FPGA, there is the complication of knowing the different delays, which are needed for calibration. The wikipedia page mentions a Vernier Johnson counter, which would seem to be more digital. > The counter stuff is easy. I have yet to fully grasp how the vernier > stuff works, while also having fully asynchronous trigger-ability. If you can generate two delays off the trigger at the appropriate resolution, then the pulse can be the difference between the two. Again, calibration is the hard part. -- glenArticle: 151145
On Mar 10, 10:06=A0am, geobsd <geobsd...@gmail.com> wrote: > > Just the FPGAs? > > yes ! > > > What tablet? > > a chineese tablet 8" with a freescale IMX5 > > > What interface? > > well i'm not sure what's in it without open it (i will destroy the > back soon) > usb-otg, wifi sure > > > It's not a CPU it's a programmable logic device. You don't program it y= ou > > define how the logic will operate and configure it. > > that's what i call programme fgpa, you can't programme cpu you > programme on it, we are ok here ! > > > There's plenty of information on the web site! > > i didn't found good information to direct use of fpga without made > bitstream yet, and my tablet will run my OS, ISE&al are dead for me ! > > thanks Nial I don't think that you fully understand what an FPGA is and how it is used. The free ISE WebPack software will running on a Windows or Linux PC to design the logic that will go into the FPGA and to generate the bitstream to configure the bitstream. Have you read the Spartan-3E datasheet? www.xilinx.com/support/documentation/data_sheets/ds312.pdf What are you trying to accomplish with this project? Ed McGettigan -- Xilinx Inc.Article: 151146
Am 11.03.2011 04:24, schrieb glen herrmannsfeldt: > I used to know about a TDC, (see wikipedia Time_to_digital_converter ) The wikipedia article about TDC is a total mess. I wouldn't recommend it to anyone. ThomasArticle: 151147
hi Ed i understoud, after buying those, that fgpas can't be used directly in any OS ! strangely it is the most flexible PU too (and that's why i bought 5) my project is to have dynamic generation of bitstream to have a very powerfull tablet in any usage ! i don't say protyping or R&D is bad but limit fpgas to those fields only is a non-sense ! childs play to push the wheele but later they learn to use them to make bicycle ;) i understand that my way will be hard, i didn't saw anyone doing bicycle yet, ~np i have harder to live in my life ! @bient=F4tArticle: 151148
why do you complain about you restricted softwares while the hardwer is much more closed ?Article: 151149
maybe just open enough door(s) to have the correct delay without thinking more and the homework is done ?
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