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Messages from 152675

Article: 152675
Subject: Implementation Issue
From: "James" <james.gahan@n_o_s_p_a_m.analog.com>
Date: Mon, 26 Sep 2011 13:10:21 -0500
Links: << >>  << T >>  << A >>
Hi Guys,

I'm using the Spartan-3E 1600E Microblaze development kit.
What I'm basically doing is writing to the on board DAC (Linear Tech
LTC2624 Quad DAC), and then reading from the on board ADC (Linear Tech
LTC6912 Dual A/D) whose analog input is connected to the DAC analog output.
The data written to the DAC and the data read from the ADC is then made
available to other modules within my design for analysis/comparison and is
also made available to my LCD driver module so as to display the data on
the LCD.

The problem that I am having is that no data is read back from the ADC (ADC
data displayed on LCD is all 0s), however the DAC was successfully written
to (DAC output voltage changed correctly). Now initially I thought I must
be reading from the ADC incorrectly so I simply brought out debug signals
to a header on the board (J4) so that they could be viewed with an
oscilloscope. The debug signals were connected to the SPI interface signals
TCK, MOSI, MISO, and ADCconv. After bringing out these debug signals, which
should not effect the design, the design then worked and ADC data was being
read back correctly.

Now when any combination of the ucf contraints that assign the debug
signals to the header pins are commented out and the design is
re-implemented (not res-synthesised) the design does not work.
 
Does anyone have any ideas about this? Any help would be greatly
appreciated.
 
Regards,
James

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152676
Subject: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 26 Sep 2011 19:12:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
jleslie48 <jon@jonathanleslie.com> wrote:
> the xilinx says it has 500,000 gates,

In the olden days (before BRAM and embedded multipliers) there was 
some use for this number, though very little.  A little less useful
than MIPS (Meaningless Indicator of Processor Speed) is of serial
CPU performance.

But now it includes the logic in BRAMs and multipliers, and anything
else that they add on.  Often your design doesn't use these additional
resources in the exact proportion that they are supplied, and so
the extras go to waste.  (Like CPU cycles while waiting for I/O.)

> the altera says it has
> 22,320 Logic elements (LEs)
> 594 Embedded memory (Kbits)
> 66 Embedded 18 x 18 multipliers
> 4 General-purpose PLLs

This allows you to separately determine the logic, block memory,
and block multplier resources.  You alse need to know the size of
an LE to compare with anything other than another device in the
same family.

> so are these two fpga's comparable in size/ computing power/ ability
> to support the same VHDL or what?

Is a 200MHz Pentium faster than a 250MHz PowerPC 620?

--glen


Article: 152677
Subject: Re: Implementation Issue
From: gtwrek@sonic.net (Mark Curry)
Date: 26 Sep 2011 19:20:03 GMT
Links: << >>  << T >>  << A >>
In article <_9GdnRsyfMSQXR3TnZ2dnUVZ_rydnZ2d@giganews.com>,
James <james.gahan@n_o_s_p_a_m.analog.com> wrote:
>Hi Guys,
>
>I'm using the Spartan-3E 1600E Microblaze development kit.
>What I'm basically doing is writing to the on board DAC (Linear Tech
>LTC2624 Quad DAC), and then reading from the on board ADC (Linear Tech
>LTC6912 Dual A/D) whose analog input is connected to the DAC analog output.
>The data written to the DAC and the data read from the ADC is then made
>available to other modules within my design for analysis/comparison and is
>also made available to my LCD driver module so as to display the data on
>the LCD.
>
>The problem that I am having is that no data is read back from the ADC (ADC
>data displayed on LCD is all 0s), however the DAC was successfully written
>to (DAC output voltage changed correctly). Now initially I thought I must
>be reading from the ADC incorrectly so I simply brought out debug signals
>to a header on the board (J4) so that they could be viewed with an
>oscilloscope. The debug signals were connected to the SPI interface signals
>TCK, MOSI, MISO, and ADCconv. After bringing out these debug signals, which
>should not effect the design, the design then worked and ADC data was being
>read back correctly.
>
>Now when any combination of the ucf contraints that assign the debug
>signals to the header pins are commented out and the design is
>re-implemented (not res-synthesised) the design does not work.

Timing constraints on the SPI input?  Do they exist?  Do they pass timing
analysis - for both implementations (with and without the debug connections)?

Depending on how/where you brought out the debug connections, it may 
affect timing greatly.  If you're not having the tool check the timing,
you're just rolling the dice.

Regards,

Mark



Article: 152678
Subject: Re: PCI core with expansion ROM support
From: "scrts" <hidden@email.com>
Date: Tue, 27 Sep 2011 08:44:57 +0300
Links: << >>  << T >>  << A >>

"fpgaiua" <fpga@n_o_s_p_a_m.i.ua> wrote in message 
news:j-mdnQ-uufQUDx3TnZ2dnUVZ_sadnZ2d@giganews.com...
> Good day,
> I'm working now with Spartan3 PCI project using the pci32tlite core.

Small question: is the pci core from opencores works fine? 



Article: 152679
Subject: Re: Implementation Issue
From: "James" <james.gahan@n_o_s_p_a_m.n_o_s_p_a_m.analog.com>
Date: Tue, 27 Sep 2011 03:14:22 -0500
Links: << >>  << T >>  << A >>
>In article <_9GdnRsyfMSQXR3TnZ2dnUVZ_rydnZ2d@giganews.com>,

Thanks for the help.

As you could probably guess I'm new to setting timing constraints and
analysing timing results.
Is there any literature or documentation that you could recommend that
might help me?

Regards,
James
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152680
Subject: Re: Implementation Issue
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Tue, 27 Sep 2011 07:58:52 -0500
Links: << >>  << T >>  << A >>
>>In article <_9GdnRsyfMSQXR3TnZ2dnUVZ_rydnZ2d@giganews.com>,
>
>Thanks for the help.
>
>As you could probably guess I'm new to setting timing constraints and
>analysing timing results.
>Is there any literature or documentation that you could recommend that
>might help me?
>
>Regards,
>James
>

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152681
Subject: Re: The Manifest Destiny of Computer Architectures
From: Paul Colin Gloster <Colin_Paul_Gloster@ACM.org>
Date: Thu, 29 Sep 2011 09:18:26 +0000 (UTC)
Links: << >>  << T >>  << A >>
Scott Michel <scooter.phd@gmail.com> sent:
|--------------------------------------------------------------------------|
|"On Sep 14, 2:06 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:  |
|> > 6.  A new language with APL-like semantics would allow programmers to|
|> > state their wishes at a high enough level for compilers to determine  |
|> > the low-level method of execution that best matches the particular    |
|> > hardware that is available to execute it.                             |
|>                                                                         |
|> APL hasn't been popular over the years, and it could have done          |
|> most of this for a long time.  On the other hand, you might look       |
|> at the ZPL language.  Not as high-level, but maybe more practical."    |
|--------------------------------------------------------------------------|

Languages can allow compilers to optimize in a way which compilers
do not bother to do. That was true of APL and other languages.

|----------------------------------------------------------------|
|"ACM killed off SIGAPL about 5-6 years ago. Sorry to see it go."|
|----------------------------------------------------------------|

SIGAPL exists. In what way was SIGAPL "killed off"?

|-----------------------------------------------------------------------|
|"Have a look at the DARPA HPCS languages, notably, Chapel, Fortress and|
|X10. Not entirely sure about their respective statuses, but they were  |
|an attempt in the HPC arena to raise the level of abstraction.         |
|                                                                       |
|                                                                       |
|-scooter"                                                              |
|-----------------------------------------------------------------------|

Someone of Oracle authored an article in "The Journal of the ACM" or in
"The Communications of the ACM", mainly re replacing efficient Fortran
code with fewer lines of Fortran with "only" a drop in performance of
circa 100%. Fortress and circa two other languages (maybe Chapel and
Fortress) were briefly mentioned.

In a manuscript by myself which is currently under review, I mention
Fortress (and Fortran). In some drafts of the manuscript I mentioned
part of Fortress which is less abstract for efficiency (or maybe
at a higher level and less efficient). I edited that observation out
before submitting the manuscript to the journal because of a space
constraint and the focus of the manuscript is something else.

The edited Fortress section still shows that the idea that the notion
that high abstraction is deployed in Fortress is laughable.

Sincerely,
Paul Colin Gloster

Article: 152682
Subject: Re: PCI core with expansion ROM support
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Thu, 29 Sep 2011 09:32:09 CEST
Links: << >>  << T >>  << A >>
On 2011-09-27, scrts <hidden@email.com> wrote:
> "fpgaiua" <fpga@n_o_s_p_a_m.i.ua> wrote in message 
> news:j-mdnQ-uufQUDx3TnZ2dnUVZ_sadnZ2d@giganews.com...
>> Good day,
>> I'm working now with Spartan3 PCI project using the pci32tlite core.
>
> Small question: is the pci core from opencores works fine? 

We used it in an Ethernet NIC project a long time ago and it worked well.
Unfortunately it had severe performance issues with repeated burst reads
and writes. The problem was that the FIFO:s in the PCI bridge didn't
implement any sort of high watermark/low watermark system. So as soon as
the FIFO was full you could only fill the FIFO with a transaction that was
one word long. At this point the performance of the system could not be
recovered if the injection rate did not decrease significantly.

More information about our experiences can be found here:
ihttp://liu.diva-portal.org/smash/get/diva2:22746/FULLTEXT01

regards
/Andreas

Article: 152683
Subject: VHDL problem
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Fri, 30 Sep 2011 10:24:22 -0500
Links: << >>  << T >>  << A >>
I want to do something like this

signal slv : std_logic_vector(7 downto 0);
signal sl  : std_logic;
signal res : std_logic;

res <= slv = x"01" and sl = '1';

But I get an error. I guess its something to do with them being different
types. But I would of thought that the two terms would both resolve to 1 or
0 and then I could just "and" them.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152684
Subject: Re: VHDL problem
From: KJ <kkjennings@sbcglobal.net>
Date: Fri, 30 Sep 2011 08:36:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 30, 11:24=A0am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I want to do something like this
>
> signal slv : std_logic_vector(7 downto 0);
> signal sl =A0: std_logic;
> signal res : std_logic;
>
> res <=3D slv =3D x"01" and sl =3D '1';
>
> But I get an error. I guess its something to do with them being different
> types. But I would of thought that the two terms would both resolve to 1 =
or
> 0 and then I could just "and" them.
>

No, (slv =3D x"01") resolves to type boolean as does (sl =3D '1').  I have
a function called to_std_logic that takes a boolean and returns a
std_logic for just such occasions.  So then you have

res <=3D to_std_logic(slv =3D x"01" and sl =3D '1');

Kevin Jennings

Article: 152685
Subject: Re: VHDL problem
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Fri, 30 Sep 2011 10:45:49 -0500
Links: << >>  << T >>  << A >>
Ok thanks, I thought there would be some kind of conversion function
required.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152686
Subject: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 30 Sep 2011 14:14:10 -0700
Links: << >>  << T >>  << A >>
OK, well I have updated to v16.5.
Nice improvement in the colors and such.
But I can't see the vias as being
isolated from the copper pours.



Article: 152687
Subject: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
From: Brian Davis <brimdavis@aol.com>
Date: Sat, 1 Oct 2011 11:17:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> I downloaded the design files and opened file 4199_SP605_brd_091909.brd
> with Allegro's Summer '09 viewer, that is, v15.7.
<snip>
> These inner plane layers display as completely filled areas with
> no regard to vias.
<snip>
>Is it possible to get these via connections to show properly?

With v15.7 :

Turn off everything else:
 display->color and visibility->global visibility->all invisible

Turn on the etch for the layer you want to see:
 Visibility Tab-> 07_Pwr2 etch checkbox

Enable display of Thermal Pads:
  Setup->Drawing Options->Display->Thermal Pads

This should show you a circle/circle-with-spokes/solid connection
for each via.

Note that this setting will "hide" the normal colored-if-connected
display of vias whenever the etch display is turned on.

>
> Another issue is the plot. I can plot to my printer, that's good. But when I
> plot to a file, the file has a .PLT extension.

IIRC, PrimoPDF worked for me a few years back to print to a pdf.

HTH,
Brian

Article: 152688
Subject: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sat, 1 Oct 2011 18:46:38 -0700
Links: << >>  << T >>  << A >>
> Enable display of Thermal Pads:
> Setup->Drawing Options->Display->Thermal Pads

Beautiful. Well worth reinstalling the 15.7 viewer again.
I uninstalled the 16.5 but maybe I didn't have to do that.
I did not see any similar option on the 16.5 viewer.

> Note that this setting will "hide" the normal colored-if-connected
> display of vias whenever the etch display is turned on.

I don't follow this.

> IIRC, PrimoPDF worked for me a few years back to print to a pdf.

I will try this if I can't find something else. I'd like to be able
to edit the images in something easier, like a JPEG. My backup is to
print onto paper and rescan.

Thank you so much Brian,

Brad Smallridge
Ai Vision



Article: 152689
Subject: Re: How do they handle shorts during the dynamic reconfiguration?
From: valtih1978 <do@not.email.me>
Date: Sun, 02 Oct 2011 20:40:02 +0300
Links: << >>  << T >>  << A >>
 > My workaround was to "idle" the chip with an "almost empty" bitstream 
first

ISE 13.2 says "The design is empty.  No processing will be done"

Moreover, what will happen during dynamic logic "tear down"? Will you 
have uncontrolled inputs (randomly uncontrolled drivers)?

Article: 152690
Subject: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
From: Brian Davis <brimdavis@aol.com>
Date: Sun, 2 Oct 2011 15:38:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> I uninstalled the 16.5 but maybe I didn't have to do that.

 They seem to co-exist OK, the default 16.5 install directory
differed from 15.7's when I ran the 16.5 installer today.

> I did not see any similar option on the 16.5 viewer.

Looks like it has been moved to:
Setup->Design Parameters->Display->Enhanced Display Modes->Thermal
Pads

>
> > Note that this setting will "hide" the normal colored-if-connected
> > display of vias whenever the etch display is turned on.
>
> I don't follow this.
>

 The boards I used to review from the local layout houses were
generally set up with different net color assignments for the
power nets ( instead of the all-white theme of that SP605 board ),
so displaying just the vias on a power plane would show a
constellation of differently colored donuts for the power vias,
and light gray for everything else.

 Particularly on power planes that haven't been poured yet,
this makes it very easy to eyeball split plane cuts.

 But when you have both vias _and_ the layer etch turned on,
_and_ that "thermal pads" option is true, this colored-donut
view is hidden by the thermal relief rendering.

[ It's been a few years since I've actively used that viewer to
review
design files, so my description above might be slightly mangled ]

 To see this effect, try using the Display->Assign Colors in 16.5 to
give some of the power nets a different color on that SP605 board.

Brian

Article: 152691
Subject: Re: VHDL problem
From: MBodnar <michaelrbodnar@gmail.com>
Date: Sun, 2 Oct 2011 16:18:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 30, 11:45=A0am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> Ok thanks, I thought there would be some kind of conversion function
> required.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

KJ's reply hints at a pretty fundamental concept in VHDL: the language-
level logic is purposefully different from the digital logic used to
describe circuits (true/false vs. hi/lo/x/z/...).

For example, I would imagine KJ's "to_std_logic" function to include a
statement like:

output_logic <=3D '1' when (input_boolean =3D true) else '0';

Just something to keep in mind.

MB

Article: 152692
Subject: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
From: Brian Davis <brimdavis@aol.com>
Date: Sun, 2 Oct 2011 16:29:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
>
> > IIRC, PrimoPDF worked for me a few years back to print to a pdf.
>
> I will try this if I can't find something else. I'd like to be able
> to edit the images in something easier, like a JPEG. My backup is to
> print onto paper and rescan.

Looking around the 16.5 menus, I spotted the following command:
  File->Capture Canvas Image
that can save the current board view to a JPEG file.

Brian

Article: 152693
Subject: Re: How do they handle shorts during the dynamic reconfiguration?
From: saardrimer@gmail.com
Date: Mon, 3 Oct 2011 02:49:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
> ISE 13.2 says "The design is empty.  No processing will be done"

To generate an empty bitstream, open 'fpga_editor', save an empty design (.ncd) and then run 'bitgen' on it.

Article: 152694
Subject: most stable version of ISE ?
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 03 Oct 2011 11:24:42 +0100
Links: << >>  << T >>  << A >>
I've seen lots of messages a while ago about how ISE is going downhill...
Which version of ISE would people recommend for fairly  simple VHDL projects using Spartan-3 and
Spartan-6? 
I'm currently developing with an old S3A prototype board, with a view to change to S6 for the next
iteration. 
I've used ISE 10.1 in the past with no issues, but would prefer to upgrade now to ease any pain
changing from S3 to S6.


Article: 152695
Subject: Re: most stable version of ISE ?
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Mon, 03 Oct 2011 09:14:50 -0500
Links: << >>  << T >>  << A >>
Cant say I have ever had a problem with ISE. I use 13.2 with a Virtex 5
device. I guess if you are going to use S6 then you would need to use a
newer version.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152696
Subject: Re: VHDL problem
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Mon, 03 Oct 2011 09:16:57 -0500
Links: << >>  << T >>  << A >>
The trouble I am having is that I have been using Verilog for a number of
years but now need to use VHDL. As Verilog lets you do whatever you like, I
have been finding VHDL quite hard going. But I am slowly beginning to get
the hang of it.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152697
Subject: Re: most stable version of ISE ?
From: John Adair <g1@enterpoint.co.uk>
Date: Mon, 3 Oct 2011 07:53:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
It really depends what you are doing which is best. ISE12.4 was very
good but had some changes particularly in IP starting to move to AXI
bus interface. Prior to that 12.2 was also good. We are now running
13.2 a lot currently and many things are fixed, or much better, in the
IP side.

Generally the change from PLB busses to AXI has meant a lot of change
recently and that's never good for stability but that should get
better with more releases. I expect 13.3 will be better again but wait
and see.

John Adair
Enterpoint Ltd. - Home of Raggedstone2. The Spartan-6 PCIe Development
Board.

On Oct 3, 11:24=A0am, Mike Harrison <m...@whitewing.co.uk> wrote:
> I've seen lots of messages a while ago about how ISE is going downhill...
> Which version of ISE would people recommend for fairly =A0simple VHDL pro=
jects using Spartan-3 and
> Spartan-6?
> I'm currently developing with an old S3A prototype board, with a view to =
change to S6 for the next
> iteration.
> I've used ISE 10.1 in the past with no issues, but would prefer to upgrad=
e now to ease any pain
> changing from S3 to S6.


Article: 152698
Subject: ISE 13.2 CPLD Schematic projects
From: Anders.Montonen@kapsi.spam.stop.fi.invalid
Date: Mon, 3 Oct 2011 15:43:38 +0000 (UTC)
Links: << >>  << T >>  << A >>
Could someone please try the following:

In ISE 13.2, open one of the 9572XL schematic example projects (jc2_sch,
jc2_sver or jc2_svhd) and run the Floorplan IO - Pre-Synthesis process.

Does the design in the floorplanner resemble the schematic *at all*?

-a

Article: 152699
Subject: Re: most stable version of ISE ?
From: Gabor <gabor@szakacs.invalid>
Date: Mon, 03 Oct 2011 13:51:36 -0400
Links: << >>  << T >>  << A >>
John Adair wrote:
> It really depends what you are doing which is best. ISE12.4 was very
> good but had some changes particularly in IP starting to move to AXI
> bus interface. Prior to that 12.2 was also good. We are now running
> 13.2 a lot currently and many things are fixed, or much better, in the
> IP side.
> 
> Generally the change from PLB busses to AXI has meant a lot of change
> recently and that's never good for stability but that should get
> better with more releases. I expect 13.3 will be better again but wait
> and see.
> 
> John Adair
> Enterpoint Ltd. - Home of Raggedstone2. The Spartan-6 PCIe Development
> Board.
> 
> On Oct 3, 11:24 am, Mike Harrison <m...@whitewing.co.uk> wrote:
>> I've seen lots of messages a while ago about how ISE is going downhill...
>> Which version of ISE would people recommend for fairly  simple VHDL projects using Spartan-3 and
>> Spartan-6?
>> I'm currently developing with an old S3A prototype board, with a view to change to S6 for the next
>> iteration.
>> I've used ISE 10.1 in the past with no issues, but would prefer to upgrade now to ease any pain
>> changing from S3 to S6.
> 

I think the bus changes would affect EDK projects more than the
"VHDL projects" noted in the OP.  However I would think that 12.4
should be a minimum revision for the Spartan 6 if you want to use
MIG and get the design to meet timing at the high end of its
performance range.  If you use ISIM for simulation, there have
also been improvements in release 12.x, but I don't use newer
versions so I can't comment on ISIM there.  Modelsim XE is
no longer available with the newer versions, so if you want to
use ModelSim you may need to buy a seat of PE.  I found that
ISIM is easy enough to get used to, and a full seat of ISIM is
at least as good as ModelSim XE, (but still far off from ModelSim PE).
It's hard to say which version of ISE is most "stable" because
they all have quirks, so once you learn to work around them
all version become stable enough to get the job done.

One thing to watch for in versions 12.x and newer is the "new
parsers" for V6 and S6 HDL design.  While these have the ability
to generate significantly smaller and faster results, they have
some bugs to be worked out still.  Version 11.5 still uses the
old parsers for V6 and S6.  If you find you have issues with
some structures in the new parsers, you can always try to go
back to 11.5 for a sanity check.  One would hope that future
releases will fix most of these bugs.  In the meantime you may
need to do post-translate simulation to make sure the synthesis
didn't break the design.

-- Gabor



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