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On 23/04/2013 21:13, Kevin Neilson wrote: > Why is Modelsim so expensive? It is a mature product Mature product? you do know that simulators are constantly being enhanced with new language features, standards and debug capabilities. The last thing I would call a simulator (or any maintained EDA product) is mature. > and yet it segfaults on me all the time. Then either you are very unlucky, have a unreliable PC or have a "nack" for writing disastrous code, sorry but I have been using Modelsim since version 4.7 and yes it does occasional crash but no more than any other EDA tool I use. > Constantly. Often, when it ought to give me warnings or errors (such as when there is a port > width mismatch) it just core dumps instead, Port mismatches very rarely result in a core dump, if it does then contact Mentor support. Modelsim create a stack dump in vsim_stacktrace.vstf when it crashes, include this in your Service Request. I also find that using the command line "vsim -c" has a better chance of giving me a verror code. leaving me to comment out lines one at a time until > I figure out why it's crashing. single stepping might be quicker. Using a different version (like 10.0f which was released after 10.2a) might also allow you to continue to work while engineering looks at your core dump. That's my rant. It's still pretty decent, but ought to be > cheaper if it's going to coredump like freeware. I agree, EDA tools are too expensive but then again the user group is pretty small and as I mentioned earlier standards are being created and updated all the time which cost money. Now why is Vivado-HLS crashing again on my code....... Hans www.ht-lab.comArticle: 155126
What is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA ? Are there any 44 pin FPGAs ? hamiltonArticle: 155127
On 4/24/2013 9:37 AM, hamilton wrote: > What is the lowest cost and/or the smallest CPU in an FPGA. > > Can a CPU with reasonable code space fit into a 44 pin FPGA ? > > Are there any 44 pin FPGAs ? > > hamilton Lol, that is a humorous transistion. You might want to start with the last question. There might be some parts from Lattice in the iCE40 series that are in packages with that pin count. I know they have some small ones, but mostly they are *very* fine pitch BGA/LGA type parts. Why the concern with the pin count? Usually people need a minimum, not a max. They may have size concerns, but that is not closely tied to pin count. I prefer parts with large pin pitch (0.5 mm minimum) to ease board design issues. So I often have to live with 100 pin parts and larger. If you need a tiny part, you can get some very small parts, but they will be larger pin counts that 44 pins in most brands. As to the CPU, take your pick. The J1 seems to be a pretty good design with 16 bit instructions that can map to multiple Forth primitives. Bernd Paysan has a b16 with 5 bit instructions which is fully fleshed out and usable. I think he has two flavors, a larger and a smaller implementation. There are others too, but I don't have them on the tip of my tongue. -- RickArticle: 155128
David Brown <david.brown@removethis.hesbynett.no> writes: > needed, I don't think there are FPGA's big enough on the market. Had It's possible to build build a clos style crossbar out of smaller FPGA's, but you "waste" a lot of serdes links for switch expansion, e.g. in the figure below each switch element could be a 4x4 FPGA which is interconnected to form a 8x8 switch: http://upload.wikimedia.org/wikipedia/commons/c/c9/Benesnetwork.png //Petter -- .sig removed by request.Article: 155129
Kevin Neilson <kevin.neilson@xilinx.com> writes: > The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any > way to infer them? Probably not. They're not that useful otherwise, > unless you want to instantiate the primitive (not really), use CoreGen > (no), and simulate using a unisim (who's got the time?). In Vivado you can script IP generation. You might be able to generate a FIFO on the fly prior to the actual synthesis. Check the Vivado documentation. > I always thought it'd be nice if Synplify could infer the It might also be possible to script the Synplify SYNCore FIFO Wizard from TCL even though I never tried. Synplify Premier has support for DesignWare where you can "infer" (or more like parametrized instantiation) complex components. However, I don't know if the DW_fifo_2c_df will map into the Xilinx block-RAM FIFO's. > Systemverilog push_front and pop_back queue commands as a FIFO and > then use its own SynCore tool to make a FIFO from that. I might have > to wait another 7-8 years for that one. :-) I guess most Synthesis tools would tell you that the queues are only supported for simulation. //Petter -- .sig removed by request.Article: 155130
On 4/24/2013 10:10 AM, rickman wrote: > On 4/24/2013 9:37 AM, hamilton wrote: >> What is the lowest cost and/or the smallest CPU in an FPGA. >> >> Can a CPU with reasonable code space fit into a 44 pin FPGA ? >> >> Are there any 44 pin FPGAs ? >> >> hamilton > > Lol, that is a humorous transistion. Ok, my goal. I need a uP and some logic, but I would like to do it with one part. 208 pins just won't fit into my package. Thanks hamiltonArticle: 155131
On 25/04/13 06:19, hamilton wrote: > On 4/24/2013 10:10 AM, rickman wrote: >> On 4/24/2013 9:37 AM, hamilton wrote: >>> What is the lowest cost and/or the smallest CPU in an FPGA. >>> >>> Can a CPU with reasonable code space fit into a 44 pin FPGA ? >>> >>> Are there any 44 pin FPGAs ? >>> >>> hamilton >> >> Lol, that is a humorous transistion. > > Ok, my goal. > > I need a uP and some logic, but I would like to do it with one part. Consider looking at this from a different direction. You say you need "some" logic, which implies that you don't need a lot. Are you sure an FPGA is necessary? There are lots of microcontrollers around with advanced peripherals that can negate the need for some logic. And since many of these micros are very fast, you can perhaps do the "logic" tasks in software. Then there are the "hybrid" devices such as the PSOC or XMOS that could perhaps do the job. You might also be better off with a dedicated microcontroller and a small flash PLD. Before we know what sort of microcontroller power you need, and what sort of logic you need, you can't get good help. Be specific about what you are trying to do, and people can give better advice - at the moment it is like going into a library and asking for a book with 8 chapters and a green cover. > > 208 pins just won't fit into my package. > Do you mean you don't have the physical space on your board? Do you have other restrictions on the package types you can use, the density, number of layers, etc.? After all, a 44-pin PLCC package takes about as much space as a modern 800-ball BGA - so number of pins is meaningless on its own. And have you considered everything else around the planned FPGA, such as power supplies for multiple rails, oscillators, flash chips for the configuration, etc.? These can quickly take up more space than the FPGA itself. > Thanks > > hamilton >Article: 155132
hamilton wrote: > What is the lowest cost and/or the smallest CPU in an FPGA. > > Can a CPU with reasonable code space fit into a 44 pin FPGA ? > > Are there any 44 pin FPGAs ? 6502: 3150 transistors, 6800: 4100 transistors, 8080: 4500 transistors So yes, you certainly ought to be able to get them inside an FPGA. But that leads onto the more important point: what toolchain are you going to use to program the processor? You may decide that is the tail that should wag the dog.Article: 155133
Of course it depends on your exact requirements, but nowadays your are ofte= n better of with a small Cortex-Mx (e.g. NXP LPC or Freescale Kinetis) + sm= all FPGA (or CPLD) (e.g. Altera MAX V or Lattice iCE40/MachXO2 have small p= ackages and integrated config-memory). The uCs are highly integrated, having flash, ADC, clock oscillator, brown-o= ut-detection, etc. integrated. With the FPGA only approach, you often need = separate parts for this. If you want to go with the FPGA only approach (e.g. if you need no ADC and = only have small code memory requirements), you can check out our ERIC5 soft= core CPU which is extremely small: http://www.entner-electronics.com/tl/index.php/eric5.html BTW, if you are using Altera parts, you might also be interested in our EEB= laster ;-) http://www.entner-electronics.com/tl/index.php/eeblaster.html (EUR 49,-) Regards, ThomasArticle: 155134
On Wednesday, April 24, 2013 8:37:46 AM UTC-5, hamilton wrote: > What is the lowest cost and/or the smallest CPU in an FPGA. > > > > Can a CPU with reasonable code space fit into a 44 pin FPGA ? > > > > Are there any 44 pin FPGAs ? > You can get a mico8 core to fit in a lattice Mach XO2-640 in a 100 pin lqfp, not a huge amount of code space, although how much depends on how you split up the block ram resources.Article: 155135
>Why is Modelsim so expensive? It is a mature product and yet it segfaults = >on me all the time. Constantly. Often, when it ought to give me warnings = >or errors (such as when there is a port width mismatch) it just core dumps = >instead, leaving me to comment out lines one at a time until I figure out w= >hy it's crashing. That's my rant. It's still pretty decent, but ought to = >be cheaper if it's going to coredump like freeware. > What version are you running? Which OS? How much memory has your PC? Which language are you writing in? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155136
On Wednesday, April 24, 2013 3:54:36 AM UTC-4, HT-Lab wrote: > > On 23/04/2013 21:13, Kevin Neilson wrote: Why is Modelsim so expensive? > > It is a mature product Mature product?=20 > you do know that simulators are constantly being enhanced with new langua= ge > features, standards and debug capabilities. The last thing I would call a > simulator (or any maintained EDA product) is mature. If that's your definition, then virtually no product would ever be 'mature'= . > > and yet it segfaults on me all the time. > Then either you are very unlucky, have a unreliable PC or have a "nack" f= or > writing disastrous code, sorry but I have been using Modelsim since versi= on=20 > 4.7 and yes it does occasional crash but no more than any other EDA tool = I=20 > use. Don't blame the user. I've seen the same behavior with every single 10.x r= elease. At which point I'll write up a service request, Mentor will reprod= uce it and many times I'll have to revert back to version 6.4 which for me = at least was the last really stable release. Kevin JenningsArticle: 155137
KJ <kkjennings@sbcglobal.net> wrote: > Don't blame the user. I've seen the same behavior with every single 10.x > release. At which point I'll write up a service request, Mentor will > reproduce it and many times I'll have to revert back to version 6.4 which > for me at least was the last really stable release. On the subject of Modelsim, how does it relate to Questa SV/AFV? I've read various things that refer to Questa as if it's Modelsim renamed, but others that suggest they're different simulators (ie there's a non-trivial overhead in switching from one to the other). I realise there's other things called 'Questa', just to make this more confusing. Currently we're on Modelsim 6.5c and have Questa 10.1d available (but not installed) - I'm wondering how transparent the upgrade path would be. TheoArticle: 155138
I am working on a channel emulator which is based on a FPGA development board and a custom based RF board connected to the FPGA board via daughter card connection (240 pins). I was using WARP 2 (Hard PowerPC Processor in the FPGA) till now, but am looking for a new FPGA board as WARP 2 is discontinued because Xilinx has stopped the manufacture of SystemAce. Below are my requirements. 1. A hard processor (Preferably a PowerPC). 2. 240 I/O pin from the development board. 3. USB, Serial and Ethernet ports. 4. SD Card slot. 5. Clock support. Can someone suggest me some options ? I checked Xilinx website and found some FPGA based on Microblaze, but I am not sure if it can give me enough throughput to run my computational intensive application. One more problem with using Microblaze is that, my application uses many shared libraries like Boost, MySql and I would have to cross compile them for Microblaze which would be difficult as its not a well know architecture for microprocessors. I understand Microblaze is well know in the world of FPGA, but its not very well know in the application domain like ARM, PowerPC, x86 etc, please correct me if I am wrong. If I go for V6/V7 FPGA of Xilinx, the development boards have few I/O pins (100 - 160) and I need at least 250 pins. What are my other options ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155139
Am Freitag, 26. April 2013 00:36:57 UTC+2 schrieb studywireless: > I am working on a channel emulator which is based on a FPGA development > > board and a custom based RF board connected to the FPGA board via daughter > > card connection (240 pins). I was using WARP 2 (Hard PowerPC Processor in > > the FPGA) till now, but am looking for a new FPGA board as WARP 2 is > > discontinued because Xilinx has stopped the manufacture of SystemAce. Below > > are my requirements. > > > > 1. A hard processor (Preferably a PowerPC). > > 2. 240 I/O pin from the development board. > > 3. USB, Serial and Ethernet ports. > > 4. SD Card slot. > > 5. Clock support. > > > > Can someone suggest me some options ? I checked Xilinx website and found > > some FPGA based on Microblaze, but I am not sure if it can give me enough > > throughput to run my computational intensive application. One more problem > > with using Microblaze is that, my application uses many shared libraries > > like Boost, MySql and I would have to cross compile them for Microblaze > > which would be difficult as its not a well know architecture for > > microprocessors. I understand Microblaze is well know in the world of FPGA, > > but its not very well know in the application domain like ARM, PowerPC, x86 > > etc, please correct me if I am wrong. > > > > If I go for V6/V7 FPGA of Xilinx, the development boards have few I/O pins > > (100 - 160) and I need at least 250 pins. What are my other options ? > > > > > > > > --------------------------------------- > > Posted through http://www.FPGARelated.com Hi, maybe the Xiliny Zynq 7000 Series is what you are loking for. Dual Core ARM processor + FPGA fabric. Have a nice synthesis EilertArticle: 155140
Is it at all practical for home-builders on a very limited budget to develop DSP type functions, such as filters and the like, on FPGAs? Reading around, I get the impression that experimenters that do it have access to high powered tools, through their work or some other way. Tools such as Matlab allow you to enter filter parameters, and out comes the VHDL, but Matlab with all the associated toolboxes is a tad pricey for the home brewer. Handcoding a FIR filter looks like an impossibly hard task, or is that just me?Article: 155141
Make that 'DSP' "Bruce Varley" <bv@NoSpam.com> wrote in message news:... > Is it at all practical for home-builders on a very limited budget to > develop DSP type functions, such as filters and the like, on FPGAs? > Reading around, I get the impression that experimenters that do it have > access to high powered tools, through their work or some other way. Tools > such as Matlab allow you to enter filter parameters, and out comes the > VHDL, but Matlab with all the associated toolboxes is a tad pricey for the > home brewer. > > Handcoding a FIR filter looks like an impossibly hard task, or is that > just me? >Article: 155142
On Fri, 26 Apr 2013 17:35:33 +0800, Bruce Varley wrote: > Is it at all practical for home-builders on a very limited budget to > develop DSP type functions, such as filters and the like, on FPGAs? > Reading around, I get the impression that experimenters that do it have > access to high powered tools, through their work or some other way. > Tools such as Matlab allow you to enter filter parameters, and out comes > the VHDL, but Matlab with all the associated toolboxes is a tad pricey > for the home brewer. > > Handcoding a FIR filter looks like an impossibly hard task, or is that > just me? An FIR filter has a very simple and regular structure, and hand coding a basic one is a very easy project. As a first step, create one with no more taps than your target FPGA has multipliers. (Hint : use the "Transpose Form") Later you can learn tricks such as KCM (constant coefficient multipliers) and other ways to economise on hardware (many taps will have very small coefficients so their multiplications can reduce to a few additions). Creating the filter coefficients is a bit more involved but you can use a little mathematical knowledge instead of the expensive tools. For example, the "window method" is as follows: 1) Decide the frequency response you want. 2) Convert that to an impulse response via Discrete Fourier Transform (DFT or Fast FT:FFT) or from knowledge of common results (perfect LPF = rectangle in frequency domain = sin(t)/t in time domain) 3) Shorten that impulse response to something finite, and with no. of time steps <= no. of available filter taps. This degrades the freq response in different ways according to the method used; hence there are different methods. Simplest is the Window Method with variants that shallow the filter slope or degrade the stopband attenuation : Hamming window, Hanning, or Blackman windows are common with about 40dB, 45 dB or 75dB stopband attenuation respectively. For a better but more compute intensive approach, the Remez Exchange Algorithm is available. Thirty years ago you had to type ten pages of Fortran from a listing in a book, and it took 5 hours on a Z80, but I bet you can quickly find it in a more convenient form now. 4) Scale the coefficients into fixed point (ie scaled integer) form and enter them in a VHDL constant array. 5) Plug said array of coefficients into the filter you coded earlier. The above is not QUITE enough info to DIY but I think it gives you enough outline and search terms to get you going. Step 2 or 3 are where Matlab (or the open source Octave or your own Python or Ada* program) can help most. * Ada has fixed-point built in, as easy to use as floating point. Sweet... Other DSP algorithms are also amenable to hand coding treatment so don't be put off trying them. IMO you'll ultimately do a better job through knowing the internals better than you could if you just "plug and play" with Matlab. - BrianArticle: 155143
Bruce Varley <bv@nospam.com> wrote: > Is it at all practical for home-builders on a very limited budget to develop > DSP type functions, such as filters and the like, on FPGAs? Reading around, > I get the impression that experimenters that do it have access to high > powered tools, through their work or some other way. Tools such as Matlab > allow you to enter filter parameters, and out comes the VHDL, but Matlab > with all the associated toolboxes is a tad pricey for the home brewer. > Handcoding a FIR filter looks like an impossibly hard task, > or is that just me? In most cases, writing the VHDL to process the filter isn't the hard part, but getting the data in and out of the FPGA appropriately is. Usually it is done in an FPGA for speed reasons, and the interfacing to get data in and out at high speed takes work. Otherwise, for actual processing, look at the systolic array architecture. -- glenArticle: 155144
Bruce Varley wrote: > Is it at all practical for home-builders on a very limited budget to develop > DSP type functions, such as filters and the like, on FPGAs? Reading around, > I get the impression that experimenters that do it have access to high > powered tools, through their work or some other way. Tools such as Matlab > allow you to enter filter parameters, and out comes the VHDL, but Matlab > with all the associated toolboxes is a tad pricey for the home brewer. > > Handcoding a FIR filter looks like an impossibly hard task, or is that just > me? If your objective is to learn about DSP and FPGAs, then it is *better* to hand-code everything. The alternative is to merely fill in a few parameters and press a few buttons - after which all you know is how to fill in parameters and press a button. Analogy: those people that have written a few assembler programs and looked at the output of a compiler have a much more useful understanding of what a computer is doing. Once you know the basics, you are in a much better position to use the automated tools to best advantage.Article: 155145
On Fri, 26 Apr 2013 17:35:33 +0800 "Bruce Varley" <bv@NoSpam.com> wrote: > Is it at all practical for home-builders on a very limited budget to develop > DSP type functions, such as filters and the like, on FPGAs? Reading around, > I get the impression that experimenters that do it have access to high > powered tools, through their work or some other way. Tools such as Matlab > allow you to enter filter parameters, and out comes the VHDL, but Matlab > with all the associated toolboxes is a tad pricey for the home brewer. > > Handcoding a FIR filter looks like an impossibly hard task, or is that just > me? > > For actual filter design, the tools are a godsend. No one sits around doing Remez exchanges and DFTs by hand. GNU Octave does most of what Matlab (basic) does, and is free. Now you've got your filter coefficients, expressed in pure mathematical form. Start writing code; the machine generated stuff is crap anyhow and I know practically no one who uses it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 155146
>>
>> Posted through http://www.FPGARelated.com
>
>Hi,
>maybe the Xiliny Zynq 7000 Series is what you are loking for.
>Dual Core ARM processor + FPGA fabric.
>
>Have a nice synthesis
> Eilert
>
Hi Eilert,
The problem with Xilinx Zynq are
1. Its relatively new and I am not sure if Xilinx can ship the board for us
as other customers are waiting for it. So its going to take some time when
Xilinx can start shipping to small customers like us (Its just my guess).
2. As the board is new, the software/tool support will be lagging the
hardware. It will take some time before things stabilize.
3. It has 68 differential I/O, so that gives me 136 I/O pins, but we need
more I/O pins.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 155147On Friday, 23 September 2011 01:20:18 UTC+5:30, jleslie48 wrote: > the xilinx says it has 500,000 gates, > > > > the altera says it has > > 22,320 Logic elements (LEs) > > 594 Embedded memory (Kbits) > > 66 Embedded 18 x 18 multipliers > > 4 General-purpose PLLs > > > > so are these two fpga's comparable in size/ computing power/ ability > > to support the same VHDL or what? hi, here is the answer for your question. this reply doesnot support pictures to post so please go to the below link to view the differences between cyclone IV,spartan 3e(xc3s500e),spartan 3e(xc3s1600e),virtex-5(top1). http://tinypic.com/view.php?pic=69ow3a&s=5 i'll prefer de0-nano board will be the best board among these all,it is portable,handy,smart,and featured in many ways among all those, thanks subhrajitArticle: 155148
On Friday, 23 September 2011 01:20:18 UTC+5:30, jleslie48 wrote: > the xilinx says it has 500,000 gates, > > > > the altera says it has > > 22,320 Logic elements (LEs) > > 594 Embedded memory (Kbits) > > 66 Embedded 18 x 18 multipliers > > 4 General-purpose PLLs > > > > so are these two fpga's comparable in size/ computing power/ ability > > to support the same VHDL or what? hi, here is the answer for your question. this reply doesnot support pictures to post so please go to the below link to view the differences between cyclone IV,spartan 3e(xc3s500e),spartan 3e(xc3s1600e),virtex-5(top1). http://oi44.tinypic.com/69ow3a.jpg i'll prefer de0-nano board will be the best board among these all,it is portable,handy,smart,and featured in many ways among all those, thanks subhrajitArticle: 155149
> > Ok, my goal. > I need a uP and some logic, but I would like to do it with one part. > 208 pins just won't fit into my package. That's both very broad, and vague. How much uP and how much Logic ? You can get 'some logic' as small as QFN32, (Xilinx, Lattice) but if you really want both in one package, look at Cypress PSoC series. I think the new PSoC4 comes in 44 pins, and fits "a uP and some logic"
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Compare FPGA features and resources
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