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Kevin Neilson wrote: > Super! Mann zieht die Stuetzpunkte mit der Maus! That is a nice applet, but it's parametric, > so it seems a little different than my application. I have a function of only one variable. The class Spline.java is a spline of only one variable. Test.java uses it twice, for the x and y coordinate of the points. Your example for x=-1,0,1,2 could be implemented by creating a Spline object and initializing it with the y-samples. Then call fn, with 0, 1, 2, 3 and use t for interpolating between two points. -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 155201
hi, Can I link libraries to a project using the Nios II IDE tools? I am using v9.0 and I want to link the OpenCV libraries to my project. it is related with cygwin or NiosII compiler? pleaze i need your help.thanks in advance. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155202
The XMODZ IP collection provides fast hardware implementations for the modulo computation on integers. The collection comprises of two distinct IP modules, modk for modulo by a fixed integer constant and modv for modulo by an integer variable. Modulo reduction is widely used in cryptographically-secure systems, for fast pseudo-random number generation and is suitable for RNS (Residue Number System) applications. XMODZ can be used as a ROYALTY-FREE component for use in your projects. Interesting features and characteristics of XMODZ include: - highly-parameterized synchronous architecture - register-pipelined operation with single-cycle throughput - scalable architecture supporting any data bitwidth - 198-230 MHz achieved clock rates for both cores on Xilinx Virtex-6. The XMODZ IPs comprise of the following deliverables: - Documentation in ASCII text, PDF, HTML formats - Vendor-independent VHDL code for both modk and modv - Self-checking testbenches - Configurable multi-precision integer reference C models for test data generation using the public domain "free GMP" library (GMP API- compatible) - Various helper scripts for simulation (GHDL, Modelsim) and synthesis. SPECIAL OFFER! -------------- Any user that will register and download MPRFGEN within 2013 is eligible to ALL of the following: - free updates for the entire lifetime of the product - free email support. Pricing information and sample downloads: http://www.nkavvadias.com/eshop Best regards, Nikolaos Kavvadias <nikos@nkavvadias.com> Research Scientist Lamia, Fthiotis, Greece http://www.nkavvadias.com http://www.perfeda.grArticle: 155203
On 6/3/2013 10:53 PM, Nikolaos Kavvadias wrote: > Nikolaos Kavvadias Thank you, Mr. Nikolaos Kavvadias, for the SPAM! I'll remember that next time my company evaluates IP vendors. JJSArticle: 155204
Hi John, > Thank you, Mr. Nikolaos Kavvadias, for the SPAM! > > I'll remember that next time my company evaluates IP vendors. I think that such kind of announcements (straight, informative and to the point) are far from spam. Personally, I find myself reading such "ANN"s, most of the time. I didn't intend to make you feel offended, just to let people know what kind of IP is available as a standalone offering. If you have any technical questions, observations or suggestions I will be glad to answer them. Kind regards, Nikolaos Kavvadias http://www.nkavvadias.com http://www.perfeda.gr > > JJSArticle: 155205
> Thank you, Mr. Nikolaos Kavvadias, for the SPAM! >=20 Nowadays, I think we should be happy for every bit of traffic we get here a= t comp.arch.fpga ;-) On-topic: I am not sure if your IP allows for arbitrary Zs (e.g. x MOD 253) or just s= pecial ones. About a year ago I had to do mod 3 and mod 7 operations on about 12b wide o= perands. After thinking almost a complete day, I came up with a solution th= at was extremely fast and small (I think just about 20 LEs for each case). = But my approach would not work for every modulo. Regards, Thomas www.entner-electronics.comArticle: 155206
Hi Thomas, > Nowadays, I think we should be happy for every bit of traffic we get here= at comp.arch.fpga ;-) I feel this way too ^_^ > On-topic: > I am not sure if your IP allows for arbitrary Zs (e.g. x MOD 253) or just= special ones. The modv IP (x mod by an independent variable, z) allows you to use any z. The modk IP has to be fixed at compile/elaboration time to a specific constant K. However, you can change the value of K (it is a generic) and therefore modk can be configured to support any positive integer constant. > About a year ago I had to do mod 3 and mod 7 operations on about 12b wide= operands. After thinking almost a complete day, I came up with a solution = that was extremely fast and small (I think just about 20 LEs for each case)= . But my approach would not work for every modulo. Yes, you are right. mod 3, 7, 10, 12 are some of the most popular constants. A general circuit description has the benefit of removing all this redesigning burden from you. Thomas, have you read the product brief and the documentation? Here are corresponding links to both: http://perfeda.gr/data/documents/xmodz-pb.pdf http://perfeda.gr/data/documents/xmodz-README.pdf I also think that is possible to provide Modelsim (or GHDL on Linux) compiled files (not the HDL itself) for evaluation (for free). And/or to supply a synthesis report for your specific cases, just for reference purposes. Best regards Nikolaos Kavvadias > > Regards, > > Thomaswww.entner-electronics.comArticle: 155207
Hi Thomas, this is a summary of synthesis reports for XMODZ on your suggested configurations. The results have been obtained with Xilinx XST/ISE 12.3 for a small Virtex-6 device (XC6VLX75T). "REG" designs have pipeline registers at each stage, "COMB" designs only have registers at the output. (This table is best viewed with a monospace font). +--------+------+----------+------------+------------+------------ +-------------+ | Design | Mode | Latency | Throughput | Min. clk per| LUTs | Regs | | | | | | | | | +--------+------+----------+------------+------------+------------ +-------------+ | modv | REG | 14 | 1 | 3.5 ns | 174 | 235 | +--------+------+----------+------------+------------+------------ +-------------+ | modv | COMB | 1 | 1 | 32 ns | 154 | 13 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=3 | REG | 12 | 1 | 2.53 ns | 111 | 98 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=3 | COMB | 1 | 1 | 5.76 ns | 36 | 13 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=7 | REG | 11 | 1 | 2.53 ns | 112 | 94 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=7 | COMB | 1 | 1 | 21.86 ns | 88 | 13 | +--------+------+----------+------------+------------+------------ +-------------+ Best regards Nikolaos KavvadiasArticle: 155208
Could I use the Precision RTL with the LatticeECP3 Versa development kit? LatticeSemi does provide a one year evaluation license (old version of the Diamond Design Suite) for this board. Any experience using this PCI-e based development board with non- Lattice software? ThanksArticle: 155209
Could I use the Precision RTL with the LatticeECP3 Versa development kit? LatticeSemi does provide a one year evaluation license (old version of the Diamond Design Suite) for this board. Any experience using this PCI-e based development board with non- Lattice software? ThanksArticle: 155210
hi, I have a custom designed board with spartan 2 (XC2S150) with some input data and clk line connected to a peripheral device, the clk level is 3.3V and FPGA IO standard(not defined in .ucf file so is the default) is LVTTL and VCCIO is 3.3 and VREF of FPGA is not connected to any voltage. my problem is, sometimes reading data from peripheral is erroneous and after some test I'm sure that the GND level of peripheral and FPGA is changing so that some clk edges are missed in FPGA which result in the data corruption. inorder to resolve this problem, I connected the two board with a good ground wire and after that there was fewer data loss but not 100% correct. another thing that I wanted to do is changing input IO Level from LVTTL to LVCMOS2.5, but I'm not sure if it is possible regarding that the VCCIO is connected to 3.3V? how should I know that the level of FPGA is working at LVCMOS2.5? is this presumtion going to fix my problem? tnx in advance for any helpful comment, Neda Baheri --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155211
"nba83" wrote in message news:4MGdnZrcOs1zsS7MnZ2dnUVZ_vidnZ2d@giganews.com... >I have a custom designed board with spartan 2 (XC2S150) with some input >data and clk line connected to a peripheral device, the clk level is 3.3V >and FPGA IO standard(not defined in .ucf file so is the default) is LVTTL >and VCCIO is 3.3 and VREF of FPGA is not connected to any voltage. >my problem is, sometimes reading data from peripheral is erroneous and >after some test I'm sure that the GND level of peripheral and FPGA is >changing so that some clk edges are missed in FPGA which result in the data >corruption. inorder to resolve this problem, I connected the two board with >a good ground wire and after that there was fewer data loss but not 100% >correct. another thing that I wanted to do is changing input IO Level from >LVTTL to LVCMOS2.5, but I'm not sure if it is possible regarding that the >VCCIO is connected to 3.3V? how should I know that the level of FPGA is >working at LVCMOS2.5? >is this presumtion going to fix my problem? I doubt it; but to change input IO threshold to LVCMOS25 you must reduce VDDIO to 2.5V. What is the phase relationship between the clock and data? Do you have adequate setup and hold times? Are you using the same clock for all the logic inside the FPGA or is there another clock? Are you handling the clock domain crossing correctly? What is the rise time of the clock? FPGAs are very fast. If the rise time is slow and there is any noise superimposed, the FPGA can actually clock more than once on a single edge. Improving the grounding might well have reduced the amount of superimposed noise. A better way to handle this is to sample the clock and data using a faster internal clock and detect edges, rather than using the external clock as a clock directly. Ideally you want the sampling interval to be about the same as the rise time so you only get one or two samples falling on each edge.Article: 155212
On 6/8/2013 9:09 AM, nba83 wrote: > hi, > I have a custom designed board with spartan 2 (XC2S150) with some input > data and clk line connected to a peripheral device, the clk level is 3.3V > and FPGA IO standard(not defined in .ucf file so is the default) is LVTTL > and VCCIO is 3.3 and VREF of FPGA is not connected to any voltage. > my problem is, sometimes reading data from peripheral is erroneous and > after some test I'm sure that the GND level of peripheral and FPGA is > changing so that some clk edges are missed in FPGA which result in the data > corruption. inorder to resolve this problem, I connected the two board with > a good ground wire and after that there was fewer data loss but not 100% > correct. another thing that I wanted to do is changing input IO Level from > LVTTL to LVCMOS2.5, but I'm not sure if it is possible regarding that the > VCCIO is connected to 3.3V? how should I know that the level of FPGA is > working at LVCMOS2.5? > is this presumtion going to fix my problem? > tnx in advance for any helpful comment, If you have ground problems, they won't be fixed by changing the voltage level to 2.5 volts... unless the chip on the other end is driving with 2.5 volts? Look at your signals with a dual channel scope to see the wave shape to make sure there is no point where the rising or falling edges of the clock are glitching creating an extra clock edge and observe the setup and hold time of the data with respect to the clock. What is the peripheral device? Are you using the correct edge of the clock? -- RickArticle: 155213
On 08/06/2013 14:09, nba83 wrote: > hi, I have a custom designed board with spartan 2 (XC2S150) with some > input data and clk line connected to a peripheral device, the clk > level is 3.3V and FPGA IO standard(not defined in .ucf file so is the > default) is LVTTL and VCCIO is 3.3 and VREF of FPGA is not connected > to any voltage. my problem is, sometimes reading data from peripheral > is erroneous and after some test I'm sure that the GND level of > peripheral and FPGA is changing so that some clk edges are missed in > FPGA which result in the data corruption. inorder to resolve this > problem, I connected the two board with a good ground wire and after > that there was fewer data loss but not 100% correct. another thing > that I wanted to do is changing input IO Level from LVTTL to > LVCMOS2.5, but I'm not sure if it is possible regarding that the > VCCIO is connected to 3.3V? how should I know that the level of FPGA > is working at LVCMOS2.5? is this presumtion going to fix my problem? > tnx in advance for any helpful comment, Neda Baheri How are the signals connected between the two boards? The distance between them? And the clock frequency? I would stick to 3.3V unless there is good reason to do otherwise. It's a long time since I looked at Spartan 2s, but what is the significance of Vref when using the LVTTL IO standard? -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 155214
rickman <gnuarm@gmail.com> wrote: > What is the peripheral device? Are you using the correct edge of the > clock? Are there sufficient timing constraints set up so the tools can check they're obeying the timing requirements of the peripheral? TheoArticle: 155215
Hi, Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04. I am trying to simulate GTX wrapper (generated from xilinx coregen) in questasim. Steps followed by me : 1.Compliled the all xilinx library using "compxlibgui" in questasim. 2.Then copy the modelsim.in into the working directory of project. 3.launched the vsim with the "-L" switch for libraries and with -novopt I am facing the following error while simulation: .... # Refreshing /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo # Refreshing /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1. # Time: 0 fs Iteration: 0 Instance: /LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd Line: 54 # FATAL ERROR while loading design # Error loading design Error loading design I am able to simulate the same project in the ISIM. Please replay me the solution of this issue. Thanks, Rahul --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155216
Am Dienstag, 11. Juni 2013 12:39:32 UTC+2 schrieb rahulkhikher: > Hi, > > > > > > Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04. > > > > > > I am trying to simulate GTX wrapper (generated from xilinx coregen) in > > questasim. Steps followed by me : > > > > 1.Compliled the all xilinx library using "compxlibgui" in questasim. > > > > 2.Then copy the modelsim.in into the working directory of project. > > > > 3.launched the vsim with the "-L" switch for libraries and with -novopt > > > > > > > > I am facing the following error while simulation: > > > > .... > > > > # Refreshing > > /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo > > # Refreshing > > /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo > > > > Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1. > > # Time: 0 fs Iteration: 0 Instance: > > /LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i > > File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd > > Line: 54 > > # FATAL ERROR while loading design > > # Error loading design > > Error loading design > > > > > > > > I am able to simulate the same project in the ISIM. > > > > > > Please replay me the solution of this issue. > > > > > > > > Thanks, > > > > Rahul > > > > > > > > > > --------------------------------------- > > Posted through http://www.FPGARelated.com Hi Rahul, do as the error message says: Check the file GTXE1.vhd (or the instantiating TB) for a generic AC_CAP_DIS. The range of that generic is 0 to 1, and the actual setting is reported to be 1095521093. Maybe some number gets misinterpreted for some reason. (Are you just using VHDL or are there other languages involved (verilog, Systemverilog)? If you don't find anything reasonable, it might also be a simple bug. Have a nice simulation EilertArticle: 155217
On Thursday, 31 March 2011 22:42:03 UTC+5:30, Nico Coesel wrote: > I've run into a bit of a problem. A camera module I would like to use > has a MIPI CSI-2 interface. The SoC I want to connect to only has a > parallel camera interface. How difficult would it be to use an FPGA in > between? Or are there already MIPI to parallel converters? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=.) > -------------------------------------------------------------- Sorry for deviating from the topic!! Can somebody please tell, what is the settle count term that is used in MIPI? How does it influence the camera system, and what are the values that should be configured for this settle count? ThanksArticle: 155218
[snipped] Somewhat strange. 1095521093 is a prime number. Neither 1095521092 nor 1095521094 are simple powers of 2. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155219
rahulkhikher wrote: > Hi, > > > Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04. > > > I am trying to simulate GTX wrapper (generated from xilinx coregen) in > questasim. Steps followed by me : > > 1.Compliled the all xilinx library using "compxlibgui" in questasim. > > 2.Then copy the modelsim.in into the working directory of project. > > 3.launched the vsim with the "-L" switch for libraries and with -novopt > > > > I am facing the following error while simulation: > > .... > > # Refreshing > /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo > # Refreshing > /home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo > > Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1. > # Time: 0 fs Iteration: 0 Instance: > /LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i > File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd > Line: 54 > # FATAL ERROR while loading design > # Error loading design > Error loading design > > > > I am able to simulate the same project in the ISIM. > > > Please replay me the solution of this issue. > > > > Thanks, > > Rahul > > > > > --------------------------------------- > Posted through http://www.FPGARelated.com It looks like Questa is not properly decrypting the secureIP from the Xilinx library. Have you checked with Xilinx to see if your version of Questa supports their secureIP libraries? The malformed generic could just be a symptom of improper decryption of the source. -- GaborArticle: 155220
I have a general purpose soft processor core that I developed in verilog. = The processor is unusual in that it uses four indexed LIFO stacks with expl= icit stack pointer controls in the opcode. It is 32 bit, 2 operand, fully = pipelined, 8 threads, and produces an aggregate 200 MIPs in bargain basemen= t Altera Cyclone 3 and 4 speed grade 8 parts while consuming ~1800 LEs. Th= e design is relatively simple (as these things go) yet powerful enough to d= o real work. I wrote a fairly extensive paper describing the processor, and am about to = post it and my code over at opencores.org, but was thinking the paper and t= he concepts might be good enough for a more formal publication. Any sugges= tions on who might be interested in publishing it?Article: 155221
The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants), namely: - HWLU, a mixed-level structural/RTL architecture, - IXGENB, a behavioral-level and - IXGENR, a high-performance, pure RTL description of a more generalized form of the architecture. Hardware looping architectures have potential uses for data-intensive processing in embedded systems. The implemented architectures are able to execute perfect loop nests without any cycle overhead for updating the iteration vector. Actually, successive last iterations of nested loops are collapsed in a single cycle. LOOPGEN can be used as a ROYALTY-FREE component for use in your projects. Interesting features and characteristics of LOOPGEN include: - three different architectural variants - support for any number of loops and datapath bitwidth - single-cycle iteration vector update - 201-243 MHz achieved clock rates on Xilinx Virtex-6. The LOOPGEN IPs comprise of the following deliverables: - Documentation in ASCII text, PDF, HTML formats - Vendor-independent VHDL code for all architectural variants - Configurable testbench - HDL code generators for the HWLU and IXGENR architectures - Various helper scripts for simulation (GHDL, Modelsim) and synthesis. SPECIAL OFFER! -------------- All users that will register and download LOOPGEN within 2013 are eligible to the following: - FREE updates for the entire lifetime of the product - FREE email support. Pricing information and sample downloads: http://www.nkavvadias.com/eshop Best regards, Nikolaos Kavvadias <nikos@nkavvadias.com> Hardware and EDA tools developer, Research Scientist Lamia, Fthiotis, Greece http://www.nkavvadias.com http://www.perfeda.grArticle: 155222
Hi, I was in a similar position about 5 years ago. My own processor is the ByoRISC, a RISC-like extensible custom processor supporting multiple- input, multiple-output custom instructions. > I have a general purpose soft processor core that I developed in verilog.= =A0The processor is unusual in that it uses four indexed LIFO stacks with = explicit stack pointer controls in the opcode. =A0It is 32 bit, 2 operand, = fully pipelined, 8 threads, and produces an aggregate 200 MIPs in bargain b= asement Altera Cyclone 3 and 4 speed grade 8 parts while consuming ~1800 LE= s. =A0The design is relatively simple (as these things go) yet powerful eno= ugh to do real work. This reads like a "fourstack" architecture on steroids. It seems good! How do you compare with more classic RISC-like soft-cores like MicroBlaze, Nios-II, LEON, etc? There is also a classic book on stack-based computers, you really need to go through this and reference it in your publication. > I wrote a fairly extensive paper describing the processor, and am about t= o post it and my code over at opencores.org, but was thinking the paper and= the concepts might be good enough for a more formal publication. =A0Any su= ggestions on who might be interested in publishing it? I had chosen to publish to VLSI-SoC 2008 (due to proximity, that year it was held in Greece). It is an OK conference, however, not indexed well by DBLP and the likes. Anyway, here is a link to my submitted version of the paper: http://www.nkavvadias.com/publications/kavvadias_vlsisoc08.pdf The paper was really well accepted at the conference venue. I had received some of my best reviews. However, I didn't had the chance to present the paper in person, because I was in really deep-S in the army and couldn't get a three- day special leave for the conference. (I joined the army at 31, so I was s'thing like an elderly private :). For instance, I was about the same age as all the majors in the camp. Only colonels and people among permanent staff where older. On the contrary, I had a hard-time to publish an extended/long version of the paper as a journal paper. All three publishers were arguing about the existence of the conference paper, and that due to this fact, no journal paper version was necessary (even with ~40% material additions). My suggestion is to: a) go for the journal paper (e.g. IEEE Trans. on VLSI or ACM TECS if you have s'thing really modern) b) otherwise submit to an FPGA or architecture conference. It depends on where you live, there are numerous European and worldwide conferences with processor-related topics (FPGA-based architectures, GPUs, ASIPs, novel architectures, manycores, etc). In all cases you may have to adapt your material (e.g. due to page limits) to the conventions of the publisher. BTW another more recent example is the paper on the iDEA DSP soft-core processor: http://www.ntu.edu.sg/home/sfahmy/files/papers/fpt2012-cheah.pdf This looks like a lean, mean architecture well-opted for contemporary FPGAs. Hope these help. Best regards, Nikolaos Kavvadias http://www.nkavvadias.comArticle: 155223
>I have a general purpose soft processor core that I developed in verilog. = >The processor is unusual in that it uses four indexed LIFO stacks with expl= >icit stack pointer controls in the opcode. It is 32 bit, 2 operand, fully = >pipelined, 8 threads, and produces an aggregate 200 MIPs in bargain basemen= >t Altera Cyclone 3 and 4 speed grade 8 parts while consuming ~1800 LEs. Th= >e design is relatively simple (as these things go) yet powerful enough to d= >o real work. > >I wrote a fairly extensive paper describing the processor, and am about to = >post it and my code over at opencores.org, but was thinking the paper and t= >he concepts might be good enough for a more formal publication. Any sugges= >tions on who might be interested in publishing it? > Do you also have an assembler, C++ compiler and debugger for this beast? You should have a reference design running on a FPGA board if you want to attract a following. Ideally it should also run linux. Why can't you do both. Post the code to opencores.org and then write a paper about it and publish. John --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155224
Thank you for your reply Nikolaos! > This reads like a "fourstack" architecture on steroids. It seems > good! "A Four Stack Processor" by Bernd Paysan? I ran across that paper several = years ago (thanks!). Very interesting, but with multiple ALUs, access to d= ata below the LIFO tops, TLBs, security, etc. it is much more complex than = my processor. It looks like a real bear to program and manage at the lowes= t level. > How do you compare with more classic RISC-like soft-cores like > MicroBlaze, Nios-II, LEON, etc? The target audience for my processor is an FPGA developer who needs to impl= ement complex functionality that tolerates latency but requires determinist= ic timing. Hand coding with no toolchain (verilog initial statement boot c= ode). Simple enough to keep the processor model and current state in one's= head (with room to spare). Small enough to fit in the smallest of FPGAs (= with room to spare). Not meant at all to run a full-blown OS, but not a tr= ivial processor. > There is also a classic book on stack-based computers, you really need > to go through this and reference it in your publication. "Stack Computers: The New Wave" by Philip J. Koopman, Jr.? Also ran across= that many years ago (thanks!). The main thrust of it seems to be the advo= cating of single data stack, single return stack, zero operand machines, wh= ich I feel (nothing personal) are crap. Easy to design and implement (I've= made several while under the spell) but impossible to program in an effici= ent manner (gobs of real time wasted on stack thrash, the minimization of w= hich leads directly to unreadable procedural coding practices, which leads = to catastrophic stack faults). > On the contrary, I had a hard-time to publish an extended/long version > of the paper as a journal paper. All three publishers were arguing > about the existence of the conference paper, and that due to this > fact, no journal paper version was necessary (even with ~40% material > additions). Hmm. The last thing I want is to have my hands tied when I'm trying to giv= e something away for free. But my paper would likely benefit from external= editorial input. > My suggestion is to: > a) go for the journal paper (e.g. IEEE Trans. on VLSI or ACM TECS if > you have s'thing really modern) My processor incorporates what I believe are a couple of new innovations (b= ut who ever really knows?) that I'd like to get out there if possible. And= I wouldn' mind a bit of personal recognition if only for my efforts. IEEE is probably out. I fundamentally disagree with the hoarding of tecnic= al papers behind a greedy paywall. > BTW another more recent example is the paper on the iDEA DSP soft-core > processor: > http://www.ntu.edu.sg/home/sfahmy/files/papers/fpt2012-cheah.pdf Wow, very nice paper describing a very nice design, thanks!
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