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"Kevin Neilson" <kevin.neilson@xilinx.com> wrote in message news:2aa27460-910a-4af2-980e-08f7b63e9a57@googlegroups.com... > Does anybody know how big a BRAM or DSP48 is in terms of CLBs? (In a > Virtex 5/6/7 part.) I was wondering, in terms of die size, whether it's > better to use a multiplier or, say, four 36-bit fabric adders? I would have thought it is more a question of what you have available - go for the fastest solution if both are going spare!Article: 155176
I would not evaluate them based on area, since you do not have the freedom = to exchange one for the other in silicon. For an arbitrary design, I would use the ratio of multipliers to CLBs on th= e FPGA device. If the FPGA device has a hundred multipliers and and 10,000 = CLBs, then a multiplier is worth 100 CLBs on that device.=20 The information is available on Xilinx's website to evaluate the ratios. For your specific design, when contemplating an optimization or additional = functionality, I would use the ratio of available (remaining) multipliers &= CLBs. If the virgin ratio is 1:100, but the remaining ratio is 1:1000, it = would indicate that multipliers are a little more precious than CLBs for yo= ur design on that device than perhaps for other designs on that device. AndyArticle: 155177
Sean Durkin wrote: > Hi Bodo, > > Bodo wrote: >> Hello, >> I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I >> have some "problems" >> during generation of the simulation models from the MIG-tool. Only the >> top-level of the DDR2-memory-controller >> is generated in VHDL, the instantiated moduls are generated in Verilog. >> This is a problem, because I don't have a mixed-language simulator. >> Are there any experiences using the DDR2-controller of the new 7-series >> from XILINX? > > I'm currently doing a DDR3-design for Artix-7. The controller code > itself is also always provided as Verilog, only the top level is VHDL. > Besides, when using Vivado, the entire process of generating an example > design is broken when you select VHDL for generation. > > To me it seems like the guy(s) doing the controller design is/are > working with Verilog only. > Kind of makes sense not to develop versions in two languages in > parallel, but it used to be different... I did a DDR2-design on Virtex-4 > with an older release of MIG (I believe it was 1.2 or so), and they > provided VHDL-code for everything back then (which was good since it > needed to be modified quite heavily). > VHDL for everything? Even the memory models? I haven't seen any DDR2 memory models in VHDL. That would make you need a mixed language simulator license even if the full controller model was in VHDL. > The only thign you could do is uses Xilinx' simulation tool, that comes > with mixed-language support by default. > > Greetings, > Sean -- GaborArticle: 155178
On 22/05/2013 19:51, GaborSzakacs wrote: > Sean Durkin wrote: >> Hi Bodo, >> >> Bodo wrote: >>> Hello, >>> I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I >>> have some "problems" >>> during generation of the simulation models from the MIG-tool. Only the >>> top-level of the DDR2-memory-controller >>> is generated in VHDL, the instantiated moduls are generated in Verilog. >>> This is a problem, because I don't have a mixed-language simulator. >>> Are there any experiences using the DDR2-controller of the new 7-series >>> from XILINX? >> >> I'm currently doing a DDR3-design for Artix-7. The controller code >> itself is also always provided as Verilog, only the top level is VHDL. >> Besides, when using Vivado, the entire process of generating an example >> design is broken when you select VHDL for generation. >> >> To me it seems like the guy(s) doing the controller design is/are >> working with Verilog only. >> Kind of makes sense not to develop versions in two languages in >> parallel, but it used to be different... I did a DDR2-design on Virtex-4 >> with an older release of MIG (I believe it was 1.2 or so), and they >> provided VHDL-code for everything back then (which was good since it >> needed to be modified quite heavily). >> > > VHDL for everything? Yes, I believe that most DDRx memory controllers (and other hard-ip) are written in encrypted (System)Verilog which a VHDL user could use using the SecureIP (Modelsim and Aldec?) license feature. I suspect that with their own "dual language out of the box ISIM simulator" Xilinx might have forgotten the other simulator users. Even the memory models? Yes, VHDL DDRx memory models are available from Hynix and RASSP. Unfortunately AFAIK most companies tend to use Micron which are all in Verilog. A friend of mine who works for a big avionics company asked Micron to provide some VHDL models but they never came back to him (no surprise I guess). It is not that expensive for a company the size of Micron to provide models in all 3 RTL languages. So perhaps now is a good time to promote Hynix memory models, they are twice as succulent... I haven't seen any > DDR2 memory models in VHDL. That would make you need a mixed > language simulator license even if the full controller model > was in VHDL. > >> The only thign you could do is uses Xilinx' simulation tool, that comes >> with mixed-language support by default. Or complain to your simulator vendor that in 2013 simulators should be dual language out of the box for exactly this reason. All synthesis tools are now dual language so why not simulators. Hans www.ht-lab.com >> >> Greetings, >> Sean >Article: 155179
>Does anybody know how big a BRAM or DSP48 is in terms of CLBs? (In a Virtex 5/6/7 part.) I was wondering, in terms of die size, whether it's better to use a multiplier or, say, four 36-bit fabric adders? > What else are you going to use the multipliers for? The BRAMs and DSP blocks are on the die whether you use them or not. The 'trick' is to not run out of them or CLBs when fitting your design. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155180
"Leland C. Scott" <kc8ldo@arrl.net> writes: > Does anybody have any experience using the kits below? > > http://www.dallaslogic.com/prod_niomite.htm > > http://www.dallaslogic.com/prod_quicgate.htm I don't but are you really interested in a Cyclone II device? Arrow has some small and cheap boards, I have one of the early BeMicro boards which cost about $50. > Also I think I'll need a JTAG cable to program the chip. The one from Altera > is rather expensive. How ever there is one that claims to be compatible. And > for a whole lot less money. Rather amusingly, the cheapest way to get a USB Blaster has been the MAX II Development Kit from Altera. Other boards usually have just USB. Still, worth considering I suppose.Article: 155181
On 22/05/2013 14:20, RCIngham wrote: >> How long it will take to test the linting tool depends entirely on the > number and complexity of the rules you are trying to enforce. >> >> If you have half a dozen simple rules, a couple of weeks is probably > plenty of time. If you have a hundred rules, many of which are rather > complex, two months might not be enough time. >> >> What code language are you wanting to lint, VHDL or Verilog? >> >> What kind of policies are you trying to enforce? Hazardous, frequently > misused or mistake-prone usage? Maintainability guidelines (e.g. unused > declarations)? Local style guide? >> >> Andy > > VHDL. > > All of the above for preference. We have many rules. > Precise number subject to next week's document review. > Why do you want to write tests for a linting tool, is this a DO-254 requirement? There is no question that a static/dynamic linting tool will have a positive impact on your development, it all comes down to your EDA budget and not on the tools usefulness. I would get some evaluation licenses and simply run them on all your previous designs. All linting tools are push-button with a standard set of rules (DO-254, RMM, Best Design Practise, Xilinx, Altera etc) so it shouldn't take too long to get some results. I am sure that analysing these results will highlight some interesting coding issues (and the usual bunch of false positives). It is a bit like running Code Coverage for the first time on your design. Then during the project work on creating/improving your own ruleset. If you are doing an FPGA design then I would probably go for Mentor's DesignChecker or Aldec's Alint rather than Spyglass which is mainly an ASIC tool and hence might be limited in their VHDL support. Good luck, Hans www.ht-lab.comArticle: 155182
Yes, I see the point that since the number of CLBs and DSP48s isn't variabl= e, like it would be on an ASIC, I should just see how much I have left of e= ach. I guess I was thinking more in terms of a rule of thumb for reusable = IP that I might want to use in different designs on different parts, like "= If you're multiplying by more than a 4-bit number, a DSP48 is better." But= then it still depends on that particular design. A similar question would relate to power consumption. How many CLBs equals= 1 DSP48?Article: 155183
Anssi Saari <as@sci.fi> wrote: > > Also I think I'll need a JTAG cable to program the chip. The one from > > Altera is rather expensive. How ever there is one that claims to be > > compatible. And for a whole lot less money. > > Rather amusingly, the cheapest way to get a USB Blaster has been the MAX > II Development Kit from Altera. Other boards usually have just > USB. Still, worth considering I suppose. The MAX II devkit is either a USB blaster or a MAX II configured by a switch, you can't choose both (in theory you could loop the MAX II into the blaster JTAG chain, but they don't do it) The USB Blaster 'clones' I think are copies of this: http://ixo-jtag.sourceforge.net/ or this: http://fpga4u.epfl.ch/wiki/FX2 One thing you don't get with clones is active serial or passive serial programming modes for which the official device has extra pins, you just get JTAG. Not that I imagine that's a major problem for most recent devices. TheoArticle: 155184
This isn't a question; I'm putting this here as a reference so I can find i=
t in the future. This is how to build a cubic interpolator circuit that ta=
kes four samples and interpolates a sample between the middle two.
Given four samples, y0, y1, y2, y3, sampled with period T=3D1 at (arbitrary=
) times t=3D{-1,0,1,2}, and given mu, where 0<mu<T, what is the cubic splin=
e interpolation formula to find ymu, the interpolated value of y that corre=
sponds to time t=3Dmu (and lies somewhere between the two middle samples)?
Answer, written in Horner's Method format:
ymu =3D 1/6*((((-y0+3y1-3y2+y3)mu + (3y0-6y1+3y2))mu + (-2y0-3y1+6y2-y3))mu=
+ 6y1)
Note: 1/6 =3D binary 0.001010101..., 6x =3D (x + x<<2)<<2
Abbreviated Derivation:
You are given four samples (t,y) =3D (-1,y0), (0,y1), (1,y2), (2,y2)
This is the cubic poly that contains those four points:
y =3D a*t^3 + b*t^2 + c*t + d
When you put the four points into this equations you have four equations in=
four unknowns. Solving yields
a =3D 1/6*(-y0+3y1-3y2+y3)
b =3D 1/6*(3y0-6y1+3y2)
c =3D 1/6*(-2y0-3y1+6y2-y3)
d =3D y1
Article: 155185Kevin Neilson <kevin.neilson@xilinx.com> wrote: > Yes, I see the point that since the number of CLBs and DSP48s isn't > variable, like it would be on an ASIC, I should just see how much > I have left of each. I believe some of the earlier families had versions available of about the same size, with and without DSP48 or other processors. Maybe also with/without BRAM and multipliers. Otherwise, you might be able to tell from a photograph of the chip or mask. DSP48, BRAM, and multipliers have to fit in rectangles in the array, unless they are all on the edge. -- glenArticle: 155186
I was able to make my own custom FPGA shield for an ARM Cortex M3 board (ar= duino footprint ofcourse!). I used the PapilioOne as reference for basic bo= ard design. There is no FT2232 on the board. I have been able to program the SRAM of the XC3S250E without any problem wi= th my Digilent Adept Tool (JTAG-SPI Full Speed Cable). But unfortunately fo= r me, my Serial Flash SPI based isn't working. I am using a M25P40 device w= hich is supposed to be Xilinx Impact Compatible. Any Solutions ? I have been trying to generate a PROM file for the SPI using Impact and the= n create a SVF file using my generated bit file (Indirect Programming) . Bu= t nothing happens. Any clues on what might i be doing wrong ? I am attaching the board sch and brd files. I have divided my FPGA shield i= nto two boards Top and Bottom, the top has the Break-out-board of the XC3s2= 50E and some peripherals. The bottom does all the power supply and provides= frequency to the top board and ofcourse attaches to the arduino footprint = at the bottom. All this because i made all these PCBs (except the break-out= -board) using the toner transfer method. I am attaching the sch and brd fil= es of the top board and also a couple of images of the whole thing.=20 http://db.tt/LHqQEv8U http://db.tt/gUiOOgcO http://db.tt/mmUkVWAW http://db.tt/BU8Rbic5 Thank youArticle: 155187
Anssi, No I'm not specifically interested in the Cyclone II device. That just happened to be what was on the board. The design I may get involved with, service and maybe maintenance issues, however I believe uses a Cyclone III device. The other kit, which looks better from a learning stand point, from http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.htmlhas the Cyclone IV device on it and currently lists for US $79. It includesthe programming dongle on board too, which otherwise would have been anextra cost.Regard;Leland C. Scott "We are not anti-immigrant, we arepro-immigrant. The government is moreconcerned about people makingcounterfeit Gucci handbags than peoplemaking counterfeit Social Security cards."MIKE CUTLER"Anssi Saari" <as@sci.fi> wrote in messagenews:vg3bo81kj9g.fsf@coffee.modeemi.fi...> "Leland C. Scott" <kc8ldo@arrl.net> writes:>>> Does anybody have any experience using the kits below?>>>> http://www.dallaslogic.com/prod_niomite.htm>>>> http://www.dallaslogic.com/prod_quicgate.htm>> I don't but are you really interested in a Cyclone II device? Arrow has> some small and cheap boards, I have one of the early BeMicro boards> which cost about $50.>>> Also I think I'll need a JTAG cable to program the chip. The one fromAltera>> is rather expensive. How ever there is one that claims to be compatible.And>> for a whole lot less money.>> Rather amusingly, the cheapest way to get a USB Blaster has been the MAX> II Development Kit from Altera. Other boards usually have just> USB. Still, worth considering I suppose.Article: 155188
Theo, I looked at the links you included. Seems like the one I was looking at can do more. The USB programming cable at http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html claims to be a "100 % compatible drop-in replacement for Altera USBBlaster programming cable", no drivers have to be installed other than the official USB Blaster ones included with the Altera software. I know they make the claim so that's why I was soliciting comments from anybody who has used the clone above just to see how compatible it really is. I may have to get one anyway for use on non-educational or development, meaning production hardware, boards at some point. Regards; Leland C. Scott "There is only one boss. The customer. And he can fire everybody in the company from the chairman on down, simply by spending his money somewhere else." -Sam Walton "Theo Markettos" <theom+news@chiark.greenend.org.uk> wrote in message news:kno*T46zu@news.chiark.greenend.org.uk... > Anssi Saari <as@sci.fi> wrote: >> > Also I think I'll need a JTAG cable to program the chip. The one from >> > Altera is rather expensive. How ever there is one that claims to be >> > compatible. And for a whole lot less money. >> >> Rather amusingly, the cheapest way to get a USB Blaster has been the MAX >> II Development Kit from Altera. Other boards usually have just >> USB. Still, worth considering I suppose. > > The MAX II devkit is either a USB blaster or a MAX II configured by a > switch, you can't choose both (in theory you could loop the MAX II into > the > blaster JTAG chain, but they don't do it) > > The USB Blaster 'clones' I think are copies of this: > http://ixo-jtag.sourceforge.net/ > or this: > http://fpga4u.epfl.ch/wiki/FX2 > > One thing you don't get with clones is active serial or passive serial > programming modes for which the official device has extra pins, you just > get > JTAG. Not that I imagine that's a major problem for most recent devices. > > TheoArticle: 155189
On 05/24/2013 05:52 AM, Leland C. Scott wrote: > Theo, > > I looked at the links you included. Seems like the one I was looking at can > do more. The USB programming cable at > > http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html > > claims to be a "100 % compatible drop-in replacement for Altera USBBlaster > programming cable", no drivers have to be installed other than the official > USB Blaster ones included with the Altera software. > > I know they make the claim so that's why I was soliciting comments from > anybody who has used the clone above just to see how compatible it really > is. I may have to get one anyway for use on non-educational or development, > meaning production hardware, boards at some point. > > Regards; > > Leland C. Scott > > "There is only one boss. The customer. > And he can fire everybody in the > company from the chairman on down, > simply by spending his money somewhere > else." > > -Sam Walton > I have no experience with this particular clone but, as others have mentioned, I guess they are all based on the same design. The Terasic Blaster has been working here without problems. PereArticle: 155190
On 24/05/13 03:04, Kevin Neilson wrote:
> This isn't a question; I'm putting this here as a reference so I can
> find it in the future. This is how to build a cubic interpolator
> circuit that takes four samples and interpolates a sample between the
> middle two.
>
> Given four samples, y0, y1, y2, y3, sampled with period T=1 at
> (arbitrary) times t={-1,0,1,2}, and given mu, where 0<mu<T, what is
> the cubic spline interpolation formula to find ymu, the interpolated
> value of y that corresponds to time t=mu (and lies somewhere between
> the two middle samples)?
>
> Answer, written in Horner's Method format:
>
> ymu = 1/6*((((-y0+3y1-3y2+y3)mu + (3y0-6y1+3y2))mu +
> (-2y0-3y1+6y2-y3))mu + 6y1)
>
> Note: 1/6 = binary 0.001010101..., 6x = (x + x<<2)<<2
>
> Abbreviated Derivation:
>
> You are given four samples (t,y) = (-1,y0), (0,y1), (1,y2), (2,y2)
>
> This is the cubic poly that contains those four points:
>
> y = a*t^3 + b*t^2 + c*t + d
>
> When you put the four points into this equations you have four
> equations in four unknowns. Solving yields
>
> a = 1/6*(-y0+3y1-3y2+y3)
> b = 1/6*(3y0-6y1+3y2)
> c = 1/6*(-2y0-3y1+6y2-y3)
> d = y1
>
This might seem a minor quibble, but that is not a cubic spline
interpolation - it is just a plain cubic curve fit and interpolation. A
cubic spline is made when you have more sample points and you put
together a step-wise cubic function consisting of multiple cubic parts
joined together. Implementing cubic splines involves quite a bit more
maths (it depends on the type of cubic spline - there are many) - making
an efficient FPGA implementation could be a fun way to spend a rainy day.
Article: 155191Leland C. Scott <kc8ldo@arrl.net> wrote: > Theo, > > I looked at the links you included. Seems like the one I was looking at can > do more. The USB programming cable at > > http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html > > claims to be a "100 % compatible drop-in replacement for Altera USBBlaster > programming cable", no drivers have to be installed other than the official > USB Blaster ones included with the Altera software. That applies to the clones too. The official Blaster is an FT245 USB-parallel chip followed by a CPLD. The clones either have a FT245 and replicate the CPLD, or replicate the CPLD and FT245 together in a microcontroller. The contents of the CPLD aren't public, but people have done sufficient reverse engineering of the basics to make it work. There are clones kicking around ebay for about $10, by the way. I'm sure I've seen ones which look the same as the cutedigi one, though I can't find any right now. But for example: http://cgi.ebay.com/200901000851 I haven't tried any of these, but the USB blaster is pretty simple so I wouldn't expect any problems. TheoArticle: 155192
David Brown wrote: > an efficient FPGA implementation could be a fun way to spend a rainy day. Should be easy, it's 10 lines in Java: http://www.frank-buss.de/spline.html -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 155193
Talking about clones, I also want to mention our EEBlaster: http://www.entner-electronics.com/tl/index.php/eeblaster.html I guess it is mainly interesting for Europeans (EUR 49,-, no prepayment req= uired for European companies). It is 100% compatible (except ancient 5V support) and also has the same spe= ed as the Altera Blaster (I think this is not the case with ultra-cheap mic= ro-controller only solutions). It has its completely own circuit, especially the voltage-level translators= are very robust. (As some might know, the Altera Blasters Rev.C were known= to die when the USB-Power and JTAG-Power was applied/removed in the wrong = sequence, there is also an official errata regarding this.) Regards, Thomas www.entner-electronics.comArticle: 155194
Thomas, So the Altera version has a known nasty bug the kills it from simply using the wrong power sequencing. That's nice to know before hand. Regards; Leland C. Scott "The TSA initial reaction has been to ban going to the restroom for the last hour of flying time because this is when the alleged terrorist went to the restroom and prepared his low-tech firecracker bomb. So, what does this really mean as a deterrent? What a joke, the terrorist simply goes to the restroom 1:15 minutes earlier to do the dirty deed." <thomas.entner99@gmail.com> wrote in message news:3977226a-db9c-4cd0-90fb-919770ae9cdf@googlegroups.com... Talking about clones, I also want to mention our EEBlaster: http://www.entner-electronics.com/tl/index.php/eeblaster.html I guess it is mainly interesting for Europeans (EUR 49,-, no prepayment required for European companies). It is 100% compatible (except ancient 5V support) and also has the same speed as the Altera Blaster (I think this is not the case with ultra-cheap micro-controller only solutions). It has its completely own circuit, especially the voltage-level translators are very robust. (As some might know, the Altera Blasters Rev.C were known to die when the USB-Power and JTAG-Power was applied/removed in the wrong sequence, there is also an official errata regarding this.) Regards, Thomas www.entner-electronics.comArticle: 155195
Theo, That's for the input. Regards; Leland C. Scott "Expecting the world to treat you fairly because you are a good person is like expecting the bull not to charge you because you are a vegetarian." Rabbi Harold Kushner "Theo Markettos" <theom+news@chiark.greenend.org.uk> wrote in message news:ino*gy9zu@news.chiark.greenend.org.uk... > Leland C. Scott <kc8ldo@arrl.net> wrote: >> Theo, >> >> I looked at the links you included. Seems like the one I was looking at >> can >> do more. The USB programming cable at >> >> http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html >> >> claims to be a "100 % compatible drop-in replacement for Altera >> USBBlaster >> programming cable", no drivers have to be installed other than the >> official >> USB Blaster ones included with the Altera software. > > That applies to the clones too. The official Blaster is an FT245 > USB-parallel chip followed by a CPLD. The clones either have a FT245 and > replicate the CPLD, or replicate the CPLD and FT245 together in a > microcontroller. The contents of the CPLD aren't public, but people have > done sufficient reverse engineering of the basics to make it work. > > There are clones kicking around ebay for about $10, by the way. I'm sure > I've seen ones which look the same as the cutedigi one, though I can't > find > any right now. But for example: > http://cgi.ebay.com/200901000851 > > I haven't tried any of these, but the USB blaster is pretty simple so I > wouldn't expect any problems. > > TheoArticle: 155196
GaborSzakacs wrote: > VHDL for everything? Even the memory models? I haven't seen any > DDR2 memory models in VHDL. That would make you need a mixed > language simulator license even if the full controller model > was in VHDL. Back then I used Samsung chips, and they provided precompiled (ModelSim) models for one of their DRAM chips (luckily, the one I was using, or one close enough). They even recompiled for me since I was using a newer ModelSim release than the one they had models for and the "refresh" option didn't work. <rant> But that was the one and only time I had Samsung do anything good for me. They proved uncooperative in absolutely every aspect before and after that, so I've banned everything Samsung from all my designs for the past 10 years (and convinced most of my colleagues to do the same). Another one of those companies that just don't care if you buy less than a million units a year... </rant> For my current design, I fortunately have a dual-language simulator license, so that's not an issue. Greetings, SeanArticle: 155197
On 24 May 2013 13:07:52 +0100 (BST) Theo Markettos <theom+news@chiark.greenend.org.uk> wrote: > That applies to the clones too. The official Blaster is an FT245 > USB-parallel chip followed by a CPLD. The clones either have a FT245 and > replicate the CPLD, or replicate the CPLD and FT245 together in a > microcontroller. The contents of the CPLD aren't public, but people have > done sufficient reverse engineering of the basics to make it work. > > There are clones kicking around ebay for about $10, by the way. I'm sure > I've seen ones which look the same as the cutedigi one, though I can't find > any right now. But for example: > http://cgi.ebay.com/200901000851 > > I haven't tried any of these, but the USB blaster is pretty simple so I > wouldn't expect any problems. > > Theo I've used them, they work like a charm. I actually bought a few so that I don't have to worry when one gets lost; at that price they're basically disposable. They do take about a month to show up, at least to the States. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 155198
Super! Mann zieht die Stuetzpunkte mit der Maus! That is a nice applet, but it's parametric, so it seems a little different than my application. I have a function of only one variable. -KevinArticle: 155199
Thanks; that is a good clarification. I just need to interpolate a point g= iven four surrounding points so I guess I don't need the whole spline imple= mentation. There is a wealth of information on the web about interpolation= but it's difficult to find the simple extracted formula I have above. I s= uppose most implementations are, like you say, not well-designed for FPGAs.
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