Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 152450

Article: 152450
Subject: Re: extracting D from 1 / D*D
From: Jonathan Bromley <spam@oxfordbromley.plus.com>
Date: Tue, 23 Aug 2011 18:38:23 +0100
Links: << >>  << T >>  << A >>
On Thu, 18 Aug 2011 17:21:39 -0700 (PDT), Kolja Sulimma wrote:

>Y*(D+1)*(D+1) - Y*D*D = 2*Y*D + 1
>and
>2*Y*(D+1) - 2*Y*D = 2*Y
>
>This means that you can scan all values of D using two additions per
>try:
>YDD_next = YDD + 2YD
>2YD_next = 2YD + 2Y
>
>Note that this version uses no multipliers.
>
>resulting in
>48 LUTs and 64k clock cycles (parallel)
>or
>6 LUTs and 2M clock cycles (bit serial)

Very nice use of second differences.

I believe there is a successive-approximation variant of this
which will calculate an N-bit result in N cycles without
multipliers.  But it requires some ingenious juggling with
shifts, and the margin of this post, etc, etc (meaning:
I'm not smart enough to write down the algorithm nicely).
I haven't yet done a LUT count.  It will be a little larger
than Kolja's numbers, but not massively bigger (I think).
Bert, we can discuss offline if you wish.

cheers
-- 
Jonathan
replace spam with jonathan in the published email address.

Article: 152451
Subject: FPGA based PCIe Gen3 Endpoint question
From: Test01 <cpandya@yahoo.com>
Date: Tue, 23 Aug 2011 11:37:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
I need to use the FPGA as PCIe Gen3 endpoint on one side and SPI ROM
interface on the other side.  Normally in x86 PC architecture, the
southbridge SPI rom interface integrated but I need to eliminate the
southbridge ASIC and replace it with FPGA for ease in configuration
and programmability.  Here is the topology



X86 CPU ---> PCIe Gen3 Bus ---> FPGA EP ---> SPI Bus ----> SPI ROM



In this mode, the X86 CPU will generate a cycle right out of reset and
we will gurantee that the request reaches to FPGA Endpoint.  But I am
not sure if the FPGA endpoint will be able to claim the cycle.  As per
my understanding, the FPGA endpoint will claim the cycle only if the
BAR registers are set.  This requires PCI configuration that is not
run right at reset.  How to enable all the transactions FROM X86 cpu
to FPGA endpoint?

 Is there a design I can leverage where southbridge fucntionlity is
integrated in the FPGA?  If so, it will be very useful.



Thanks.



CP

Article: 152452
Subject: Regarding virtex II pro xilinx XC2VP30 FF896
From: "varun_agr" <VARUN_AGR@n_o_s_p_a_m.n_o_s_p_a_m.YAHOO.COM>
Date: Wed, 24 Aug 2011 05:03:46 -0500
Links: << >>  << T >>  << A >>
Sir
I want to know how much voltage(min and max)to I/O connectors of J5 AND J6
in  virtex II pro xilinx XC2VP30 FF896 board , can given.
Thanks
Varun  	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152453
Subject: Running Chipscope >=12.x on Linux.
From: wzab <wzab01@gmail.com>
Date: Wed, 24 Aug 2011 11:40:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
When I tried to use Chipscope on my Linux machine, I got, the
following error:

COMMAND: open_cable
INFO: Started ChipScope host (localhost:50001)
ERROR: Failed to open connection to server localhost:50001 (localhost/
127.0.0.1)
java.net.SocketException: Network is unreachable
ERROR: No server found at:localhost:50001 (localhost/127.0.0.1)
INFO: Try again after starting the server on machine localhost
in a command window and verify that the server opens port 50001,
without any error messages.
The command is: /opt/Xilinx/12.1/ISE_DS/ISE/bin/lin64/cse_server -port
50001

The solution was to modify the system settings by calling as root:

# /sbin/sysctl net.ipv6.bindv6only=0

This problem was also reported by someone else here:
http://forums.xilinx.com/t5/Design-Tools-Others/Chipscope-12-1-linux-connection-problem/m-p/148396
And I've found the solution here:
https://bugs.launchpad.net/ubuntu/+source/sun-java6/+bug/486215


Article: 152454
Subject: Re: What is the advantage of source-syncronization (in SDRAMs)?
From: valtih1978 <do@not.email.me>
Date: Thu, 25 Aug 2011 10:06:08 +0300
Links: << >>  << T >>  << A >>
On 20.08.2011 19:55, Ed McGettigan wrote:
> On Aug 20, 2:53 am, valtih1978<d...@not.email.me>  wrote:
>>   >  either
>>   >  through data training (testing data samples and seeing what timing
>>   >  works) or through a timing feedback pathway
>>
>> People always say that feedback pathway can be used but never explain
>> which way? I guess that you can give a pulse and catch response fronts
>> by tuning the DCM phase, thus measuring the equivalent delay to mem.
>> This looks simpler than feeding real SDRAM with test data and
>> interpreting responses. However, it is more risky also - computation is
>> less reliable than really working design. Also, I see that the external
>> feedback becomes a part of DCM FB path in PLB memory controller. Nobody
>> can explain the purpose of it!
>>
>>   >  In my experience, once the timing parameters have been determined,
>> they're usable on all instantiations of the same circuit board using
>> the same parts at the same speed.
>>
>> This contradicts to the first statement
>>
>>   >  relationship between DQS and the DDR2 controller clock is not
>> necessarily the same all the time.
>>
>> Thanks
>
> Back in the Virtex/Virtex-II families the DCM with an external
> feedback path was used with SDRAM memory to increase the maximum data
> rate.
>
> The original clock would come into a DCM that would feed an output
> buffer.  On the PCB the net would be routed from the FPGA to the SDRAM
> memory for 50% then split in two with one route continuing to the
> SDRAM and the other returning to the FPGA.  This would present the
> same clock at both FPGA pin and the SDRAM memory.   Inside the FPGA
> the clock feedback pin would be routed to the original DCM to remove
> all of the internal and PCB delay and compensate for any voltage and
> temperature variations.
>
> Ed McGettigan
> --
> Xilinx Inc.

Ok, this matches my reading of xilinx appnotes. However again, you 
describe the way to get the thing and the purpose of thing but not the 
way the thing should be used to achieve the purpose.

How do you make use of FPGA phase-aligned with distant SDRAM to struggle 
the variations? Jedec says that DQS must be in line with DQ and addr/cmd 
switching at clock fall edge. But, this must happen at the SDRAM side!

THat is, SDRAM has 3 domains: clock, addr/cmd and DQS data lanes. You 
explained only one thing, how to get known when clock reaches the remote 
SDRAM. But, what does it give to you if you do not know the delays of 
cmd and data lines?

Article: 152455
Subject: Re: Regarding virtex II pro xilinx XC2VP30 FF896
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Thu, 25 Aug 2011 09:46:41 +0000
Links: << >>  << T >>  << A >>
Varun sent:
|---------------------------------------------------------------------------|
|"I want to know how much voltage(min and max)to I/O connectors of J5 AND J6|
|in  virtex II pro xilinx XC2VP30 FF896 board , can given."                 |
|---------------------------------------------------------------------------|

Have you read the datasheet?

Article: 152456
Subject: Re: What is the advantage of source-syncronization (in SDRAMs)?
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 25 Aug 2011 07:35:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 25, 12:06=A0am, valtih1978 <d...@not.email.me> wrote:
> On 20.08.2011 19:55, Ed McGettigan wrote:
>
>
>
>
>
> > On Aug 20, 2:53 am, valtih1978<d...@not.email.me> =A0wrote:
> >> =A0 > =A0either
> >> =A0 > =A0through data training (testing data samples and seeing what t=
iming
> >> =A0 > =A0works) or through a timing feedback pathway
>
> >> People always say that feedback pathway can be used but never explain
> >> which way? I guess that you can give a pulse and catch response fronts
> >> by tuning the DCM phase, thus measuring the equivalent delay to mem.
> >> This looks simpler than feeding real SDRAM with test data and
> >> interpreting responses. However, it is more risky also - computation i=
s
> >> less reliable than really working design. Also, I see that the externa=
l
> >> feedback becomes a part of DCM FB path in PLB memory controller. Nobod=
y
> >> can explain the purpose of it!
>
> >> =A0 > =A0In my experience, once the timing parameters have been determ=
ined,
> >> they're usable on all instantiations of the same circuit board using
> >> the same parts at the same speed.
>
> >> This contradicts to the first statement
>
> >> =A0 > =A0relationship between DQS and the DDR2 controller clock is not
> >> necessarily the same all the time.
>
> >> Thanks
>
> > Back in the Virtex/Virtex-II families the DCM with an external
> > feedback path was used with SDRAM memory to increase the maximum data
> > rate.
>
> > The original clock would come into a DCM that would feed an output
> > buffer. =A0On the PCB the net would be routed from the FPGA to the SDRA=
M
> > memory for 50% then split in two with one route continuing to the
> > SDRAM and the other returning to the FPGA. =A0This would present the
> > same clock at both FPGA pin and the SDRAM memory. =A0 Inside the FPGA
> > the clock feedback pin would be routed to the original DCM to remove
> > all of the internal and PCB delay and compensate for any voltage and
> > temperature variations.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Ok, this matches my reading of xilinx appnotes. However again, you
> describe the way to get the thing and the purpose of thing but not the
> way the thing should be used to achieve the purpose.
>
> How do you make use of FPGA phase-aligned with distant SDRAM to struggle
> the variations? Jedec says that DQS must be in line with DQ and addr/cmd
> switching at clock fall edge. But, this must happen at the SDRAM side!
>
> THat is, SDRAM has 3 domains: clock, addr/cmd and DQS data lanes. You
> explained only one thing, how to get known when clock reaches the remote
> SDRAM. But, what does it give to you if you do not know the delays of
> cmd and data lines?- Hide quoted text -
>
> - Show quoted text -

The external DCM feedback was used for the clocks only it was not (and
can't be) used for the DQS.  The second DCM aligns to the external
clock feedback that is now the same for both the FPGA and the DDR-
SDRAM and a 90 degree phase shift is used to shift the DQS outputs
from the DQ outputs.

This is clearly shown in Figure 8 of XAPP608.

Ed McGettigan
--
Xilinx Inc.





Article: 152457
Subject: Re: 5V FCT TO Cyclone II
From: "majsta" <imajstorovic@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com>
Date: Thu, 25 Aug 2011 12:10:48 -0500
Links: << >>  << T >>  << A >>
Ok but i ll stay with this design, I dont know I just cant change design
now, and many peolpe told me that it can work with txs0108e. Thank you for
your time. Also I want to ask is there are any examples of Mc68000 and
sdram controller in VHDL combinations.	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152458
Subject: meta assembler
From: "dscolson@rcn.com" <dscolson@rcn.com>
Date: Thu, 25 Aug 2011 14:22:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
Are there any commercially available meta assemblers like metalasm for
programmable state machines in FPGAs?

Thanks
Dave

Article: 152459
Subject: The smallest EDA tool
From: Guosheng Wu <micbot.com@gmail.com>
Date: Thu, 25 Aug 2011 16:33:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Robei is the world smallest EDA tool (less than 5Mbits) for Verilog
based EDA software. It integrates modern graphical user interface and
a tiny cross platform Verilog simulator. The biggest advantage of this
software is that it is totally free for personal, education and
research use.

Although Robei is very tiny, it has almost all the functionalities of
a EDA software. Robei has modern GUI, Verilog compiler, property
editor, code viewer and waveform viewer. The modern user interface of
Robei provides visualization of FPGA design and simplified it by
playing with reusable models and ports. The Toolbox is designed to
contain huge of model libraries, and no matter where is your models.
Property designer offers the most convenient method for viewing and
changing values in code. All these parts are designed to be as simple
as possible for designer. As long as you familiar with Verilog
language, you can manage it in 15 minutes.

With this tool, you can design your hardware visually in both RTL
level and behavior level, and view the simulation result through
waveform. It is a tiny, fast software for hardware prototyping and
verification.

For more information: http://robei.com/

Article: 152460
Subject: Re: extracting D from 1 / D*D
From: Bert_Paris <do_not_spam@me.com>
Date: Fri, 26 Aug 2011 09:41:29 +0200
Links: << >>  << T >>  << A >>
Hello all !

Sorry, I had to stay away from the forum for a few days.
*Thanks* a lot to all contributors for all their ideas.

I haven't made my mind yet since the sensor still
needs some validation, but there is a lot of food
for thougt here :-)

For the record, "many" means 100 clock cycles would
be fast enough, more (1000 !) clock cycles would still
be possible. That's why in theory, very compact
implementations are possible.
Large accumulators are possible since they can be
pipelined / multi-cycled in this context.
The "best" implementation is a compact enough one
that is easy enough to code :-)

I'll let you know if the project is going to use
this sensor, and which implementation I used.

Bert.



Article: 152461
Subject: Re: What is the advantage of source-syncronization (in SDRAMs)?
From: Mawa_fugo <ccon67@netscape.net>
Date: Fri, 26 Aug 2011 12:09:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 20, 11:55=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Aug 20, 2:53=A0am, valtih1978 <d...@not.email.me> wrote:
>
>
>
> > =A0> either
> > =A0> through data training (testing data samples and seeing what timing
> > =A0> works) or through a timing feedback pathway
>
> > People always say that feedback pathway can be used but never explain
> > which way? I guess that you can give a pulse and catch response fronts
> > by tuning the DCM phase, thus measuring the equivalent delay to mem.
> > This looks simpler than feeding real SDRAM with test data and
> > interpreting responses. However, it is more risky also - computation is
> > less reliable than really working design. Also, I see that the external
> > feedback becomes a part of DCM FB path in PLB memory controller. Nobody
> > can explain the purpose of it!
>
> > =A0> In my experience, once the timing parameters have been determined,
> > they're usable on all instantiations of the same circuit board using
> > the same parts at the same speed.
>
> > This contradicts to the first statement
>
> > =A0> relationship between DQS and the DDR2 controller clock is not
> > necessarily the same all the time.
>
> > Thanks
>
> Back in the Virtex/Virtex-II families the DCM with an external
> feedback path was used with SDRAM memory to increase the maximum data
> rate.
>
> The original clock would come into a DCM that would feed an output
> buffer. =A0On the PCB the net would be routed from the FPGA to the SDRAM
> memory for 50% then split in two with one route continuing to the
> SDRAM and the other returning to the FPGA. =A0This would present the
> same clock at both FPGA pin and the SDRAM memory. =A0 Inside the FPGA
> the clock feedback pin would be routed to the original DCM to remove
> all of the internal and PCB delay and compensate for any voltage and
> temperature variations.
>
> Ed McGettigan
> --
> Xilinx Inc.

yup, so the SDRAM will appear as an on chip block.... even though it
locates few inches away...

Article: 152462
Subject: ISE and detecting flowthrus
From: "fpga_me" <linuxfreak87@n_o_s_p_a_m.gmail.com>
Date: Fri, 26 Aug 2011 15:47:00 -0500
Links: << >>  << T >>  << A >>
Hi All,

When doing multi-FPGA designs, what are some of the techniques that you use
to detect if you have mistakenly pin multiplexed a flowthru net? I am
specifically interested in the way which ISE can be used.

Thanks
 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152463
Subject: Re: ISE and detecting flowthrus
From: gtwrek@sonic.net (Mark Curry)
Date: 26 Aug 2011 21:13:21 GMT
Links: << >>  << T >>  << A >>
In article <_sKdnTJNj4LZm8XTnZ2dnUVZ_qOdnZ2d@giganews.com>,
fpga_me <linuxfreak87@n_o_s_p_a_m.gmail.com> wrote:
>Hi All,
>
>When doing multi-FPGA designs, what are some of the techniques that you use
>to detect if you have mistakenly pin multiplexed a flowthru net? I am
>specifically interested in the way which ISE can be used.

You're going to have to give a few more details.  I can think of a few
different cases where the term "pin multiplexed" might be used, and even
then I wouldn't like the term because of it's vagueness.   

Same for "flowthru net".  What's that?  You made a point of indicating "multi-FPGA"
implying flowthru intra-, or inter-FPGA?  And I really don't have a clue as to what 
sort of problems you're trying to avoid/detect with the ISE tools.

--Mark


Article: 152464
Subject: Re: ISE and detecting flowthrus
From: "fpga_me" <linuxfreak87@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Fri, 26 Aug 2011 22:16:36 -0500
Links: << >>  << T >>  << A >>
Hi Mark,

I probably used the word "flowthru" a little loosely. Essentially a
flowthru would be a net that does not qualify to be pin multiplexed. Adding
multiplexing logic in its path would lead to incorrect operation. Nets
which are multi-cycle in nature are examples of signals that can be added
to pin multiplexing logic when partitioning a design across multiple
FPGAs.

>In article <_sKdnTJNj4LZm8XTnZ2dnUVZ_qOdnZ2d@giganews.com>,
>fpga_me <linuxfreak87@n_o_s_p_a_m.gmail.com> wrote:
>>Hi All,
>>
>>When doing multi-FPGA designs, what are some of the techniques that you
use
>>to detect if you have mistakenly pin multiplexed a flowthru net? I am
>>specifically interested in the way which ISE can be used.
>
>You're going to have to give a few more details.  I can think of a few
>different cases where the term "pin multiplexed" might be used, and even
>then I wouldn't like the term because of it's vagueness.   
>
>Same for "flowthru net".  What's that?  You made a point of indicating
"multi-FPGA"
>implying flowthru intra-, or inter-FPGA?  And I really don't have a clue
as to what 
>sort of problems you're trying to avoid/detect with the ISE tools.
>
>--Mark
>
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152465
Subject: cheating Arria FPGA i/o count
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 27 Aug 2011 15:58:29 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm designing a pretty horrible board (33 page schematic!) that will
use an Altera Arria II GX in the 572BGA package. There are 240 pure
I/O pins in this package, and 12 dedicated clock pins. I'm getting
close to using up all the i/o pins, and starting to do silly things to
save a pin here and there. Don't blame me, blame customer feature
creep!

So, is it possible to use clock pins as general-purpose inputs? The
documentation doesn't say so, but it does imply somewhere that clock
nets can be used for non-clock functions like async resets, so there
should be some not-too-disgusting way to used them as slow static
inputs.

Pity they didn't dual-purpose the clock pins. It's not often you need
12 clocks.

Any thoughts/experience here?

Thanks

John



Article: 152466
Subject: Re: Bitstream compression
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 27 Aug 2011 16:12:57 -0700
Links: << >>  << T >>  << A >>
On Fri, 29 Jul 2011 09:21:45 -0500, Vladimir Vassilevsky
<nospam@nowhere.com> wrote:

>
>
>Rob Gaddi wrote:
>
>> On 7/28/2011 5:15 PM, Vladimir Vassilevsky wrote:
>>> Rob Gaddi wrote:
>>>
>>>> So my experience with the native bitstream compression algorithms
>>>> provided by the FPGA vendors has been that they don't actually achieve
>>>> all that much compression.
>>>
>>> It won't be generally possible to beat vendor provided basic compression
>>> more then by a factor of ~1.5 or so. The gain of 1.5 times wouldn't
>>> really improve anything.
>>>
>> Native size is 
>> 11,875,104 bits (~1.5MB).  Bitstream compresson gives me 1.35MB.  7-Zip 
>> gives me 395kB.
>
>Interesting.
>
>I tried to compress JBCs from heavily used Altera Cyclone, got only 
>about x1.5 of compression.
>
>As for compression algorithm, something like a bit oriented LZSS or LZW 
>would be easy to implement. The decompression part is trivial. If you 
>don't care about speed, the compression part is very simple, too. I 
>don't know if the further sophistication of the algorithm would do much 
>of a difference.
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com

I've done a very simple byte-oriented RLL thing on Xilinx chips and
got config files that were 20 to 40% as big as the original binaries.
Even a pretty-full chip has long runs of 0x00 and 0xFF bytes in the
bitstream. The uP code to decompress this and bang the FPGA is pretty
simple. In serial bit-bang mode, decompressing and configuring is
faster than uncompressed, because spitting out a long string of
identical bits can be done as a fast special case... just wiggle the
config clock!

John


Article: 152467
Subject: Re: cheating Arria FPGA i/o count
From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Date: Sat, 27 Aug 2011 16:24:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 28 Aug., 00:58, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> Hi,
>
> I'm designing a pretty horrible board (33 page schematic!) that will
> use an Altera Arria II GX in the 572BGA package. There are 240 pure
> I/O pins in this package, and 12 dedicated clock pins. I'm getting
> close to using up all the i/o pins, and starting to do silly things to
> save a pin here and there. Don't blame me, blame customer feature
> creep!
>
> So, is it possible to use clock pins as general-purpose inputs? The
> documentation doesn't say so, but it does imply somewhere that clock
> nets can be used for non-clock functions like async resets, so there
> should be some not-too-disgusting way to used them as slow static
> inputs.
>
> Pity they didn't dual-purpose the clock pins. It's not often you need
> 12 clocks.
>
> Any thoughts/experience here?
>
> Thanks
>
> John

never used altera, but I'd think it is in here somewhere:

www.altera.com/download/board-layout-test/schematic-review-ws/worksheets/Arria_GX_Schematic_Review_Worksheet.doc

-Lasse

Article: 152468
Subject: Re: cheating Arria FPGA i/o count
From: "Martin Riddle" <martin_rid@verizon.net>
Date: Sat, 27 Aug 2011 19:34:38 -0400
Links: << >>  << T >>  << A >>


"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
message news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com...
> Hi,
>
> I'm designing a pretty horrible board (33 page schematic!) that will
> use an Altera Arria II GX in the 572BGA package. There are 240 pure
> I/O pins in this package, and 12 dedicated clock pins. I'm getting
> close to using up all the i/o pins, and starting to do silly things to
> save a pin here and there. Don't blame me, blame customer feature
> creep!
>
> So, is it possible to use clock pins as general-purpose inputs? The
> documentation doesn't say so, but it does imply somewhere that clock
> nets can be used for non-clock functions like async resets, so there
> should be some not-too-disgusting way to used them as slow static
> inputs.
>
> Pity they didn't dual-purpose the clock pins. It's not often you need
> 12 clocks.
>
> Any thoughts/experience here?
>
> Thanks
>
> John
>
>

I don’t see why not, dedicated clocks mean that propagation time is 
minimized across the chip.
But Quartus may balk at the idea.
see <http://www.altera.com/literature/lit-dpcg.jsp>

Some pins could be used as I/O , some can't.

Cheers
 



Article: 152469
Subject: Re: cheating Arria FPGA i/o count
From: davew <david.wooff@gmail.com>
Date: Sat, 27 Aug 2011 16:43:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 27, 11:58=A0pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> Hi,
>
> I'm designing a pretty horrible board (33 page schematic!) that will
> use an Altera Arria II GX in the 572BGA package. There are 240 pure
> I/O pins in this package, and 12 dedicated clock pins. I'm getting
> close to using up all the i/o pins, and starting to do silly things to
> save a pin here and there. Don't blame me, blame customer feature
> creep!
>
> So, is it possible to use clock pins as general-purpose inputs? The
> documentation doesn't say so, but it does imply somewhere that clock
> nets can be used for non-clock functions like async resets, so there
> should be some not-too-disgusting way to used them as slow static
> inputs.
>
> Pity they didn't dual-purpose the clock pins. It's not often you need
> 12 clocks.
>
> Any thoughts/experience here?
>
> Thanks
>
> John

Just did a test design using an Arria II GX and assigned an input pin
to a dedicated clock input and it compiled OK.

Article: 152470
Subject: Re: cheating Arria FPGA i/o count
From: davew <david.wooff@gmail.com>
Date: Sat, 27 Aug 2011 16:47:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 28, 12:43=A0am, davew <david.wo...@gmail.com> wrote:
> On Aug 27, 11:58=A0pm, John Larkin
>
>
>
>
>
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> > Hi,
>
> > I'm designing a pretty horrible board (33 page schematic!) that will
> > use an Altera Arria II GX in the 572BGA package. There are 240 pure
> > I/O pins in this package, and 12 dedicated clock pins. I'm getting
> > close to using up all the i/o pins, and starting to do silly things to
> > save a pin here and there. Don't blame me, blame customer feature
> > creep!
>
> > So, is it possible to use clock pins as general-purpose inputs? The
> > documentation doesn't say so, but it does imply somewhere that clock
> > nets can be used for non-clock functions like async resets, so there
> > should be some not-too-disgusting way to used them as slow static
> > inputs.
>
> > Pity they didn't dual-purpose the clock pins. It's not often you need
> > 12 clocks.
>
> > Any thoughts/experience here?
>
> > Thanks
>
> > John
>
> Just did a test design using an Arria II GX and assigned an input pin
> to a dedicated clock input and it compiled OK.

If you're not sure, assign the pin and run the I/O Assignment
Analysis.  This validates all your I/O assignments without having to
compile any code.

Article: 152471
Subject: Re: cheating Arria FPGA i/o count
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 27 Aug 2011 17:00:51 -0700
Links: << >>  << T >>  << A >>
On Sat, 27 Aug 2011 16:43:03 -0700 (PDT), davew
<david.wooff@gmail.com> wrote:

>On Aug 27, 11:58 pm, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> Hi,
>>
>> I'm designing a pretty horrible board (33 page schematic!) that will
>> use an Altera Arria II GX in the 572BGA package. There are 240 pure
>> I/O pins in this package, and 12 dedicated clock pins. I'm getting
>> close to using up all the i/o pins, and starting to do silly things to
>> save a pin here and there. Don't blame me, blame customer feature
>> creep!
>>
>> So, is it possible to use clock pins as general-purpose inputs? The
>> documentation doesn't say so, but it does imply somewhere that clock
>> nets can be used for non-clock functions like async resets, so there
>> should be some not-too-disgusting way to used them as slow static
>> inputs.
>>
>> Pity they didn't dual-purpose the clock pins. It's not often you need
>> 12 clocks.
>>
>> Any thoughts/experience here?
>>
>> Thanks
>>
>> John
>
>Just did a test design using an Arria II GX and assigned an input pin
>to a dedicated clock input and it compiled OK.

Cool! I'll have one of my FPGA guys try it, maybe on a real eval board
(I don't drive the FPGA software myself.)

This very weekend, I'll assume it works and get on with my life.

Thanks

John





Article: 152472
Subject: Re: cheating Arria FPGA i/o count
From: "krw@att.bizzzzzzzzzzzz" <krw@att.bizzzzzzzzzzzz>
Date: Sat, 27 Aug 2011 23:46:32 -0500
Links: << >>  << T >>  << A >>
On Sat, 27 Aug 2011 22:44:14 -0700, Robert Baer <robertbaer@localnet.com>
wrote:

>davew wrote:
>> On Aug 27, 11:58 pm, John Larkin
>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>>> Hi,
>>>
>>> I'm designing a pretty horrible board (33 page schematic!) that will
>>> use an Altera Arria II GX in the 572BGA package. There are 240 pure
>>> I/O pins in this package, and 12 dedicated clock pins. I'm getting
>>> close to using up all the i/o pins, and starting to do silly things to
>>> save a pin here and there. Don't blame me, blame customer feature
>>> creep!
>>>
>>> So, is it possible to use clock pins as general-purpose inputs? The
>>> documentation doesn't say so, but it does imply somewhere that clock
>>> nets can be used for non-clock functions like async resets, so there
>>> should be some not-too-disgusting way to used them as slow static
>>> inputs.
>>>
>>> Pity they didn't dual-purpose the clock pins. It's not often you need
>>> 12 clocks.
>>>
>>> Any thoughts/experience here?
>>>
>>> Thanks
>>>
>>> John
>> 
>> Just did a test design using an Arria II GX and assigned an input pin
>> to a dedicated clock input and it compiled OK.
>   Just because a program compiles does not mean it will work...

It does mean the I/O assignment meets the chip's specs, which is all that was
asked.

Article: 152473
Subject: Re: cheating Arria FPGA i/o count
From: Robert Baer <robertbaer@localnet.com>
Date: Sat, 27 Aug 2011 22:44:14 -0700
Links: << >>  << T >>  << A >>
davew wrote:
> On Aug 27, 11:58 pm, John Larkin
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> Hi,
>>
>> I'm designing a pretty horrible board (33 page schematic!) that will
>> use an Altera Arria II GX in the 572BGA package. There are 240 pure
>> I/O pins in this package, and 12 dedicated clock pins. I'm getting
>> close to using up all the i/o pins, and starting to do silly things to
>> save a pin here and there. Don't blame me, blame customer feature
>> creep!
>>
>> So, is it possible to use clock pins as general-purpose inputs? The
>> documentation doesn't say so, but it does imply somewhere that clock
>> nets can be used for non-clock functions like async resets, so there
>> should be some not-too-disgusting way to used them as slow static
>> inputs.
>>
>> Pity they didn't dual-purpose the clock pins. It's not often you need
>> 12 clocks.
>>
>> Any thoughts/experience here?
>>
>> Thanks
>>
>> John
> 
> Just did a test design using an Arria II GX and assigned an input pin
> to a dedicated clock input and it compiled OK.
   Just because a program compiles does not mean it will work...

Article: 152474
Subject: Re: cheating Arria FPGA i/o count
From: "TTman" <pcw1.cad@ntlworld.com>
Date: Sun, 28 Aug 2011 08:11:22 +0100
Links: << >>  << T >>  << A >>

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com...
> Hi,
>
> I'm designing a pretty horrible board (33 page schematic!) that will
> use an Altera Arria II GX in the 572BGA package. There are 240 pure
> I/O pins in this package, and 12 dedicated clock pins. I'm getting
> close to using up all the i/o pins, and starting to do silly things to
> save a pin here and there. Don't blame me, blame customer feature
> creep!
>
> So, is it possible to use clock pins as general-purpose inputs? The
> documentation doesn't say so, but it does imply somewhere that clock
> nets can be used for non-clock functions like async resets, so there
> should be some not-too-disgusting way to used them as slow static
> inputs.
>
> Pity they didn't dual-purpose the clock pins. It's not often you need
> 12 clocks.
>
> Any thoughts/experience here?
>
> Thanks
>
> John
>
>
Does PS boot mode save a pin or two ?.. 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search