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Hi Jo, You can download and use the free web-pack kits for Xilinx and Altera (and maybe Actel and Lattice have free kits). In these kits you can map your VHDL/Verilog code to the selected FPGA device. The disadvantages of the kits are that they do not support all (especially larger) devices and I am not sure if you can program your device (but in that case you need also a development board). But they are a very good starting point. The VHDL/Verilog code can be entered in a text-editor. The kits have maybe a graphical editor but I have no experience with them. I am also not aware of a free graphical editor. Succes, Devas On 10/21/2011 12:41, thunder wrote: > Hello > > I am very new to FPGA's (background being ASIC design). > > I would like to map some designs onto FPGA's as a starting point. I > want to experiment with the complete FPGA flow, starting with writing > the design in VHDL/Verilog and getting it programmed onto a target > FPGA (it doesn't matter which FPGA for the time being). > > I was looking for free/cheap FPGA developement s/w what i could run on > my home PC and better understand the process of mapping a design to an > FPGA target. > > > Any pointers for SW or developement tools would be appreciated. > > Thanks > > JOArticle: 152776
On Oct 21, 12:02=A0pm, devas <geve...@gmail.com> wrote: > Hi Jo, > > You can download and use the free web-pack kits for Xilinx and Altera > (and maybe Actel and Lattice have free kits). In these kits you can map > your VHDL/Verilog code to the selected FPGA device. The disadvantages of > the kits are that they do not support all (especially larger) devices > and I am not sure if you can program your device (but in that case you > need also a development board). But they are a very good starting point. > > The VHDL/Verilog code can be entered in a text-editor. The kits have > maybe a graphical editor but I have no experience with them. I am also > not aware of a free graphical editor. > > Succes, > > Devas > > On 10/21/2011 12:41, thunder wrote: > > > > > > > > > Hello > > > I am very new to FPGA's (background being ASIC design). > > > I would like to map some designs onto FPGA's as a starting point. I > > want to experiment with the complete FPGA flow, starting with writing > > the design in VHDL/Verilog and getting it programmed onto a target > > FPGA (it doesn't matter which FPGA for the time being). > > > I was looking for free/cheap FPGA developement s/w what i could run on > > my home PC and better understand the process of mapping a design to an > > FPGA target. > > > Any pointers for SW or developement tools would be appreciated. > > > Thanks > > > JO Hi Devas THank you for the pointer. Best regards JOArticle: 152777
thunder wrote: > On Oct 21, 12:02 pm, devas <geve...@gmail.com> wrote: >> Hi Jo, >> >> You can download and use the free web-pack kits for Xilinx and Altera >> (and maybe Actel and Lattice have free kits). In these kits you can map >> your VHDL/Verilog code to the selected FPGA device. The disadvantages of >> the kits are that they do not support all (especially larger) devices >> and I am not sure if you can program your device (but in that case you >> need also a development board). But they are a very good starting point. >> >> The VHDL/Verilog code can be entered in a text-editor. The kits have >> maybe a graphical editor but I have no experience with them. I am also >> not aware of a free graphical editor. >> >> Succes, >> >> Devas >> >> On 10/21/2011 12:41, thunder wrote: >> >> >> >> >> >> >> >>> Hello >>> I am very new to FPGA's (background being ASIC design). >>> I would like to map some designs onto FPGA's as a starting point. I >>> want to experiment with the complete FPGA flow, starting with writing >>> the design in VHDL/Verilog and getting it programmed onto a target >>> FPGA (it doesn't matter which FPGA for the time being). >>> I was looking for free/cheap FPGA developement s/w what i could run on >>> my home PC and better understand the process of mapping a design to an >>> FPGA target. >>> Any pointers for SW or developement tools would be appreciated. >>> Thanks >>> JO > > Hi Devas > > THank you for the pointer. > > Best regards > > JO Just an additional note. Many home computers run Windows 7 or other "home" editions, and may have limited support from the FPGA software. I'd suggest looking at the OS support matrix at the FPGA manufacturer web-sites to see if your system is sufficient. Windows XP Pro and RedHat Linux are supported for most if not all of these tools. -- GaborArticle: 152778
Thats really sad news. Although predominantly an Altera user I have really appreciated Peter's input to comp.arch.fpga over the years, one of the gentlemen of our industry. Nial.Article: 152779
> Anyway, I am considering to take the "Comprehensive Verilog" and > "Essentials and Design for Performance" classes by Doulos at Xilinx in Dec. > Just wondering if people think these are worthwhile? I started my FPGA development with a comprehensive VHDL course when working at Nortel 15 years ago! I think the Doulos courses are considered well structured. I found the tutor to be good at explaning concepts and he knew his stuff enough to answer any of our questions at the time. If your employer's paying for it it's a no-brainer. On language choice I'm a 99% VHDL user but I believe there are a few verilog constructs that can bite you if you don't remember what you're doing. If you're dipping in and out of FPGA development with long breaks between it might be better to concentrate on VHDL which forces you to do it right? As others have said a few macros will cut the amount of typing down drastically. Nial.Article: 152780
Gabor <gabor@szakacs.invalid> wrote: >thunder wrote: >> On Oct 21, 12:02 pm, devas <geve...@gmail.com> wrote: >>> Hi Jo, >>> >>> You can download and use the free web-pack kits for Xilinx and Altera >>> (and maybe Actel and Lattice have free kits). In these kits you can map >>> your VHDL/Verilog code to the selected FPGA device. The disadvantages of >>> the kits are that they do not support all (especially larger) devices >>> and I am not sure if you can program your device (but in that case you >>> need also a development board). But they are a very good starting point. >>> >>> The VHDL/Verilog code can be entered in a text-editor. The kits have >>> maybe a graphical editor but I have no experience with them. I am also >>> not aware of a free graphical editor. What do you mean by graphical editor? >> JO > >Just an additional note. Many home computers run Windows 7 or other >"home" editions, and may have limited support from the FPGA software. >I'd suggest looking at the OS support matrix at the FPGA manufacturer >web-sites to see if your system is sufficient. Windows XP Pro and >RedHat Linux are supported for most if not all of these tools. I second that. Nowadays I do FPGA development on a Linux machine. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152781
On Fri, 21 Oct 2011 13:02:41 +0200, devas wrote: (top posting fixed) > On 10/21/2011 12:41, thunder wrote: >> Hello >> >> I am very new to FPGA's (background being ASIC design). ---- snip ---- > Hi Jo, > ---- snip ---- > and I am not sure if you can program your device (but in that case you > need also a development board). But they are a very good starting point. ---- snip ---- The Xilinx web-kit includes download software, but you need hardware, of course. There are some basic hardware development kits available for reasonable prices ($150 range, IIRC). You won't end up with the biggest or fastest parts, but it'll be an FPGA. -- www.wescottdesign.comArticle: 152782
Very sad indeed. Si monumentum requiris... there can't be many in our industry for whom that would be more appropriate. Peter not only leaves behind a fine body of written work, but also the traces of his infectious, generous enthusiasm and expertise in the minds of a generation (no, surely two generations) of engineers. Thanks for letting us know. -- Jonathan BromleyArticle: 152783
On Oct 20, 6:21=A0am, Syd Rumpo <use...@neonica.co.uk> wrote: > On 20/10/2011 06:33, Suhaib Fahmy wrote: > > > Those who've been on this newsgroup for any period of time will > > remember Peter Alfke, the Xilinx legend, and his infectious > > enthusiasm. He was a great help as I got into FPGA design 8 years ago, > > as I embarked on the academic track. I met him at a number of > > conferences, and he was just as wonderful in person. He gave some real > > life to the newsgroup and has been sorely missed since he stopped > > posting. > > > A tweet that carried the news:https://twitter.com/xilinxtraining/status= /126857481812066304 > > > Our condolences to his family and friends; he will be sorely missed. > > > Suhaib. > > He helped me more than once, and was the main reason for my choosing > Xilinx. RIP. > > -- > Syd He is the genius in this group. I still remember his "Six Easy Pieces" R.I.PArticle: 152784
On 10/20/2011 12:33 AM, Suhaib Fahmy wrote: > Those who've been on this newsgroup for any period of time will > remember Peter Alfke, the Xilinx legend, and his infectious > enthusiasm. He was a great help as I got into FPGA design 8 years ago, > as I embarked on the academic track. I met him at a number of > conferences, and he was just as wonderful in person. He gave some real > life to the newsgroup and has been sorely missed since he stopped > posting. > > A tweet that carried the news: https://twitter.com/xilinxtraining/status/126857481812066304 > > Our condolences to his family and friends; he will be sorely missed. > > Suhaib. MAN! This has been a BAD YEAR! First, Jim Williams, then Bob Pease, and now Peter! Sad news indeed! JonArticle: 152785
On 21/10/2011 23:00, Jon Elson wrote:
> On 10/20/2011 12:33 AM, Suhaib Fahmy wrote:
..
>
> MAN! This has been a BAD YEAR! First, Jim Williams, then Bob Pease, and
> now Peter! Sad news indeed!
printf("And lets not forget Dennis Richie who passed away a few weeks
ago, one of the all time great computer scientist.\n");
Hans.
www.ht-lab.com
>
> Jon
Article: 152786Nial Stewart wrote: >> Anyway, I am considering to take the "Comprehensive Verilog" and >> "Essentials and Design for Performance" classes by Doulos at Xilinx in Dec. >> Just wondering if people think these are worthwhile? > > I started my FPGA development with a comprehensive VHDL course when working > at Nortel 15 years ago! > > I think the Doulos courses are considered well structured. I found the tutor to be > good at explaning concepts and he knew his stuff enough to answer any of > our questions at the time. > > If your employer's paying for it it's a no-brainer. Yes it is! The kind of no-brainer I like. > > On language choice I'm a 99% VHDL user but I believe there are a few > verilog constructs that can bite you if you don't remember what you're > doing. If you're dipping in and out of FPGA development with long breaks > between it might be better to concentrate on VHDL which forces you to > do it right? Well perhaps what I'll do is have my employer pay for "Comprehensive VHDL" at a later time. It does look like I'll be doing quite a bit of Verilog for a while, and some of the most biting concepts have already begun to reach unforgettable status. > As others have said a few macros will cut the amount of typing down > drastically. > > > Nial. Thanks for the input. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 152787
HT-Lab wrote:
> On 21/10/2011 23:00, Jon Elson wrote:
>> On 10/20/2011 12:33 AM, Suhaib Fahmy wrote:
> ..
>>
>> MAN! This has been a BAD YEAR! First, Jim Williams, then Bob Pease, and
>> now Peter! Sad news indeed!
>
> printf("And lets not forget Dennis Richie who passed away a few weeks
> ago, one of the all time great computer scientist.\n");
I hate to speak ill of the dead, but I've never been a great
fan of the C language or Unix. Yes, it works, it certainly
is a hacker's paradise, but there is so much unstructured
stuff in there that it is STILL causing troubles for people
40 year later! On the other hand, a HELL of a lot of work
is done in C, and Linux is a great gift to the computing
community, even with the lasting warts from Unix. So, it
is kind of a love/hate relationship there.
So, I don't put DMR and BWK in the same league as Jim
Williams and Bob Pease. Not sure if Peter really is in their
league, I'm probably unaware of a HELL of a lot of stuff that he did.
Jon
Article: 152788Nico Coesel wrote: >> >>Just an additional note. Many home computers run Windows 7 or other >>"home" editions, and may have limited support from the FPGA software. >>I'd suggest looking at the OS support matrix at the FPGA manufacturer >>web-sites to see if your system is sufficient. Windows XP Pro and >>RedHat Linux are supported for most if not all of these tools. > > I second that. Nowadays I do FPGA development on a Linux machine. > Note that the WebPack does not support 64-bit OS's. I think this is due to US export regulations. (At least this was true last time I checked.) JonArticle: 152789
Jon Elson <elson@pico-systems.com> wrote: >Nico Coesel wrote: > > >>> >>>Just an additional note. Many home computers run Windows 7 or other >>>"home" editions, and may have limited support from the FPGA software. >>>I'd suggest looking at the OS support matrix at the FPGA manufacturer >>>web-sites to see if your system is sufficient. Windows XP Pro and >>>RedHat Linux are supported for most if not all of these tools. >> >> I second that. Nowadays I do FPGA development on a Linux machine. >> >Note that the WebPack does not support 64-bit OS's. I think this is >due to US export regulations. (At least this was true last time >I checked.) I'll stick to 32 bit for the following years. Unlike Windows Linux has an excellent solution to use more than 4GB without needing a 64bit OS. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152790
On Sat, 22 Oct 2011 23:52:45 -0500, Jon Elson wrote: > Nico Coesel wrote: > >> > Note that the WebPack does not support 64-bit OS's. I think this is due > to US export regulations. (At least this was true last time I checked.) Not officially... But if your 64-bit OS has the correct 32-bit compatibility libraries installed, Webpack will run just fine. You just have to modify the install script, where it detects the 64-bit OS and exits, to comment out the exit... Then it will install and just work without further problems. Tested with Webpack 10.1 to 13.1 inclusive, on OpenSuse 11.0 to 11.4. (I adopted OpenSuse because 11.0 offered to install the 32-bit libs and simply worked, and I haven't looked back). Will probably work with most other recent Linuxes (you may have to find/install a few libraries). - BrianArticle: 152791
Jon Elson <elson@pico-systems.com> writes: > Note that the WebPack does not support 64-bit OS's. I think this is > due to US export regulations. (At least this was true last time > I checked.) I doubt that, at least Altera includes 64-bit binaries with their free stuff.Article: 152792
On Sat, 22 Oct 2011 08:29:15 -0700, "Mr.CRC" wrote: >Nial Stewart wrote: >>> Anyway, I am considering to take the "Comprehensive Verilog" and >>> "Essentials and Design for Performance" classes by Doulos at Xilinx in Dec. >>> Just wondering if people think these are worthwhile? [...] >It does look like I'll be doing quite a bit of Verilog for a while, and >some of the most biting concepts have already begun to reach >unforgettable status. So let's get the disclosure out of the way: I worked for Doulos until a couple of years ago, parted in a friendly way, and still have occasional contact with them (but no financial links at all). I'd absolutely echo all Nial said. Certainly Doulos (in common with other reputable training providers) take real care to provide a good experience for delegates, and offer good after-course support too. Their Verilog course is mature, stable and well-maintained, and they don't employ script-reading droids to do the presentation - you'll get someone who really knows their stuff and will be happy to answer your specific questions. The improvement in your own productivity that a good class can provide will far, far outweigh the cost of the class and of your lost time in attending it. HOWEVER... I would also mention that, as a professional with a real job to do, you should take a class like that only if you will have the chance to use its content immediately when you have completed the class. Even two weeks' interval between learning and using your new knowledge will really degrade the effectiveness of any class, no matter how good. But if you can start to use the class content immediately, then the excellent course notes and examples will be a good second-best to having a tutor/mentor sat next to you while you work. -- Jonathan BromleyArticle: 152793
In article <ddydnUM6upMAAD7TnZ2dnUVZ_vWdnZ2d@giganews.com>, elson@pico- systems.com says... > > Nico Coesel wrote: > > > >> > >>Just an additional note. Many home computers run Windows 7 or other > >>"home" editions, and may have limited support from the FPGA software. > >>I'd suggest looking at the OS support matrix at the FPGA manufacturer > >>web-sites to see if your system is sufficient. Windows XP Pro and > >>RedHat Linux are supported for most if not all of these tools. > > > > I second that. Nowadays I do FPGA development on a Linux machine. > > > Note that the WebPack does not support 64-bit OS's. I think this is > due to US export regulations. (At least this was true last time > I checked.) > > Jon I installed the Xilinx Web Pack Version 13.2 onto my Windows 7 Professional system with no issues what so ever. It's been running very well even through the recent Windows 7 Service Pack 1 installation. -- Michael Karas Carousel Design Solutions http://www.carousel-design.comArticle: 152794
In article <eKadnZv5ZpEeAzzTnZ2dnUVZ_umdnZ2d@web-ster.com>, tim@seemywebsite.com says... > > On Fri, 21 Oct 2011 13:02:41 +0200, devas wrote: > (top posting fixed) > > On 10/21/2011 12:41, thunder wrote: > >> Hello > >> > >> I am very new to FPGA's (background being ASIC design). > ---- snip ---- > > Hi Jo, > > > ---- snip ---- > > and I am not sure if you can program your device (but in that case you > > need also a development board). But they are a very good starting point. > ---- snip ---- > > The Xilinx web-kit includes download software, but you need hardware, of > course. There are some basic hardware development kits available for > reasonable prices ($150 range, IIRC). You won't end up with the biggest > or fastest parts, but it'll be an FPGA. I have acquired a number of these Spartan-3E boards for some FPGA prototyping work: http://www.ebay.com/itm/Xilinx-Spartan-3E-XC3S500E-PQG208-4M-FPGA- develop-board-/330622667940 The price is right and these are nice because you can simply add on the 96 pin connectors (32 x 3) in order to connect them up to your other development prototype hardware. I use the DIN 41612 type right angle connectors on the board and then use the corresponding mate on the prototype board. http://www.mouser.com/ProductDetail/AVX/208478096031029/? qs=sGAEpiMZZMvkWeVFEbAjO1%2fOh4Ta3l5B5KRtNT%252bhvxk%3d Also from eBay you can get these boards if you can live with a smaller FPGA and a potentially lower lower price: http://www.ebay.com/itm/Xilinx-Spartan-3E-FPGA-Development- Board-/110761828790?pt=LH_DefaultDomain_2&hash=item19c9eb61b6#ht_1455wt_ 1396 -- Michael Karas Carousel Design Solutions http://www.carousel-design.comArticle: 152795
On Oct 5, 1:58=A0pm, "sato" <achraf26@n_o_s_p_a_m.gmail.com> wrote: > I am new to the world of Altera and FPGA . Really hope to get some helps > from this forum. > > Thanks in advance! > > My case is: > I have MCSOP running in my stratix III DSP board . > > The outputs of the processing part of this system are displayed in the > screen . > I need the data until a base station from where I will transfer the data = to > the internet.So how do I transfer (in realtime) the data until the base > station from the FPGA with wireless conection ? > > Is there a solution to add wireless module to my DSP board and configure > with my PC in ad-hoc mode to capture this data ? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com What throughput do you need? What range? There are many different wireless modules. However if you want to connect to standard PC, then you probably need either Bluetooth (you may easily hook it to your FPGA board via USART- like interface, but the throughput is low) or WiFi (it may be quite difficult to connect it to FPGA, unless you have an embedded CPU). To connect standard WiFi card you'll need USB host interface in your FPGA system or you'll need to emulate other bus master (PCMCIA?, PCIe?). The WiFi module, which may be relatively easily connected to FPGA: http://www.cutedigi.com/product_info.php?products_id=3D4273 -- HTH & Regards, WojtekArticle: 152796
Co-sponsored by IEEE NCA Consultants Network, Baltimore Consultants Network, Society on Social Implications of Technology, Baltimore and NoVA/Wash. Computer Society, and Region 2 PACE Committee Congress has enacted sweeping patent reform that is adverse to small inventors and entrepreneurs. How will this affect you? Let=92s explore what the future holds with our panel of experts. Lunch and networking reception are included. Student members may bring a guest at no additional cost. Door prizes! Additional details at the link below. When: Saturday, November 5 10am-2pm Where: Loyola University Graduate Centers Room 260 8890 McGaw Road Columbia, MD 21045 USA Cost: $10 IEEE members (advance), $20 general Web Page: www.ieee-consultants.org Registration: http://meetings.vtools.ieee.org/meeting_view/list_meeting/877= 1 Panelists: Dr. Lee Hollaar, Dr. Amelia Morani We are still looking for a panelist who is a consultant able to speak regarding the impact of this new law. Anyone available in the area?Article: 152797
On Oct 15, 7:33=A0pm, Jon Elson <el...@pico-systems.com> wrote: > glen herrmannsfeldt wrote: > > Also, the resistor, into the transmission line load impedance, > > should round off the sharp edge a little bit, but not too much, > > reducing the effects of a too-fast transition. > > That is what I was hoping to do, round off the edge so that loads, > and the board itself pretty much absorbs the reflection. > > > If the bus is TTL levels, then half of 5V, or even half of 4V > > will meet the Vhigh level. > > Everything is CMOS, but may have "TTL" input thresholds.> A small series = termination resisitor is a lot better than > > none at all. > > Well, it SEEMS to have solved the problem. =A0I will probably > do some more testing to be sure it is solid. > > Jon There is more than one way to skin a cat. IF your FPGA has a clock on board that is significantly faster than the serial clock (> 2x) you can sample the serial clock and detect the edges in this faster clock domain. This is pretty robust against the sort of double clocking you are seeing since the problem is not noise per se, but reflections which have a defined timing relationship with the clock edge. I used this in a design for a customer, not for the noise advantages, but as part of a digital PLL design and the customer realized the lack of sensitivity to reflections and expressed his approval. RickArticle: 152798
On Oct 24, 8:59=A0pm, rickman <gnu...@gmail.com> wrote: > Co-sponsored by > IEEE NCA Consultants Network, > Baltimore Consultants Network, > Society on Social Implications of Technology, > Baltimore and NoVA/Wash. Computer Society, > and Region 2 PACE Committee > > Congress has enacted sweeping patent reform that is adverse to small > inventors and entrepreneurs. How will this affect you? Let=92s explore > what the future holds with our panel of experts. Lunch and networking > reception are included. Student members may bring a guest at no > additional cost. Door prizes! Additional details at the link below. > > When: Saturday, November 5 10am-2pm > > Where: Loyola University Graduate Centers Room 260 > 8890 McGaw Road Columbia, MD 21045 USA > > Cost: $10 IEEE members (advance), $20 general > > Web Page:www.ieee-consultants.org > > Registration:http://meetings.vtools.ieee.org/meeting_view/list_meeting/87= 71 > > Panelists: Dr. Lee Hollaar, Dr. Amelia Morani > > We are still looking for a panelist who is a consultant able to speak > regarding the impact of this new law. =A0Anyone available in the area? In what have congress changed the law?Article: 152799
On 10/24/2011 03:06 PM, rickman wrote: > > > There is more than one way to skin a cat. IF your FPGA has a clock on > board that is significantly faster than the serial clock (> 2x) you > can sample the serial clock and detect the edges in this faster clock > domain. This is pretty robust against the sort of double clocking you > are seeing since the problem is not noise per se, but reflections > which have a defined timing relationship with the clock edge. > > I used this in a design for a customer, not for the noise advantages, > but as part of a digital PLL design and the customer realized the lack > of sensitivity to reflections and expressed his approval. Yes, this is where it gets really messy. This is a mixed-signal system with VERY sensitive preamps. Any digital signals clocking while the analog section is open for signals would likely be a problem. So, there is NO continuous clock available. I know what I was forced to do broke all the digital rules, but it was necessary to make the analog part work. Jon
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