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> > MachXO2 has SPI and i2c ports.built in. > > You really need to state some numbers, 'a bit slow' is not good > enough. > > =A0Specify how fast it needs to be and how much data needs to be sent > each way, and over what distance. About speed and data. Lets say about 640 bytes 10-50 times per second from PC to devices. More than this would always be better. Opposite direction is not critical. And distance, 3 feet minimum, more is better. I can test it with less, but it is not of much when ready. >The FT2232H and Ethernet are available as small modules, (one is even >free on the MaxhXO2 boards..) so start with those, and pull them into >the logic only if you really need to. This seems wise So speed of virtual serial port like FTchip is not limited to same way as physical RS232 port?Article: 153451
On Feb 28, 8:02=A0am, LM <sala.n...@mail.com> wrote: > > >The FT2232H and Ethernet are available as small modules, (one is even > >free on the MaxhXO2 boards..) so start with those, and pull them into > >the logic only if you really need to. > > This seems wise > So speed of virtual serial port like FTchip is not limited to same way > as physical RS232 port? As in set by a legacy 1.8432MHz/16 Motherboard clock, no. The FT2232H uses 120MHz and divides by 10, and a N/8 fraction It can do 12MBd/6MBd and fractions below 6MBd, and 12MBd sustained with largish packets ( >~ 600 bytes from memory), over the high speed USB link. (and faster in other modes, but serial is simple)Article: 153452
First of all, although not related to your query but in general a good
practice, you need to sync your signals in the FPGA. Like the signals RXD
and RXDV although in sync with the RXCLK, you need to flop them in the
system, then use it wherever you want to.
Now, few things:
1- why aren't you using the RXDV signal as a write signal to DPRAM and RXD
as input?
2- Also, what you can do is, you can use a Coregen FIFO in your design
instead of DPRAM. For DPRAM, you may require a controller, for FIFO you
won't. So, just to test your logic, you can use FIFO instead. Then start
reading when RXDV goes low.
>>
>>---------------------------------------
>>Posted through http://www.FPGARelated.com
>>
>
>hi
>tnx for your suggestion, i am working on the fpga program as you
suggested,
>but my problem still exist,i used chipscope to debug the problem, the
data
>is received fine to fpga but it seemed that the data is not write and
read
>back from dual port ram, here is the code. i don't know what's the
problem
>and how should i proceed? thanks in advanced for help
>
>i read the data received from lan in this process and write in DPRAM,
>generate a strob to transmit process to start sending data at the falling
>edge of RXDV, and capturing the end of packet transmition for reseting
>write address:
>
> always @(posedge RTL_RXCLK)
> begin
>
> /// Reading Data from RXD pin and save it in dpram
> if(RTL_RXDV)
> begin
> write_address2 <= write_address2+1;
> Ram_Data_In <= RTL_RXD;
> Ram_Write_Enable<=1;
> end
> else
> Ram_Write_Enable<=0;
>
> ///Set Receive Packet Strob to transmit section
> pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
> if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
> begin
> loopback_data<=1;
> PacketReceived <= PacketReceived +1;
>
> end
> /// reset Receive Packet Strob
> if(loopback_data)
> begin
> DelayCcLpbackData <= DelayCcLpbackData + 1;
> if(DelayCcLpbackData>=50)
> begin
> loopback_data<=0;
> DelayCcLpbackData<=0;
> end
> end
>
> /// capture End ot Trasmission
> preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
> if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
> begin
> write_address2<=0;
>
> end
> end
> //////
>
> always @(posedge RTL_TXCLK )
> begin
> /// Capture Rising edge of Receive packet Strob generated by
>receive process
> pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
> if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
> begin
> StartSendingData<=1;
> end
>
> // start transmitting data
> if(StartSendingData)
> begin
> read_address2<=read_address2+1;
> rgRTL_TXD<=Ram_Data_Out;
> rgRTL_TXE <=1;
> re_en<=1;
> if(read_address2>write_address2)
> begin
> read_address2<=0;
> re_en<=0;
> rgRTL_TXE <=0;
>
>
>End_Sending_Strobe <= 1;
> StartSendingData<=0;
> end
> end
>
> //////////////
> if(End_Sending_Strobe)
> begin
> DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
> if(DelayCcResetSendStrobe>=50)
> begin
> DelayCcResetSendStrobe <= 0;
> End_Sending_Strobe <= 0;
> end
> end
>
> end
>
>
>
> duall_ram2 duall_ram2_in2
> (
> .CLCK_re(RTL_TXCLK),
> .CLCK_wr(RTL_RXCLK),
> .DIN(Ram_Data_In),
> .Re(re_en),
> .RE_ADDRESS(read_address2),
> .We(Ram_Write_Enable),
> .wr_address(write_address2),
> .dout(Ram_Data_Out)
> );
>
>and the module for DPRAM is :
>entity duall_ram2 is
> Port ( DIN : in std_logic_vector(3 downto 0);
> RE_ADDRESS : in std_logic_vector(10 downto 0);
> wr_address :in std_logic_vector(10 downto 0);
> CLCK_wr : in std_logic;
> CLCK_re : in std_logic;
> We : in std_logic;
> Re : in std_logic;
> dout : out std_logic_vector(3 downto 0));
>end duall_ram2 ;
>
>architecture Behavioral of duall_ram2 is
>type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
>signal rom: my_data;
>begin
>
>process (clck_wr)--write
>begin
> if (clck_wr'event and clck_wr = '0') then
> if (we = '1') then
> rom(conv_integer(WR_address)) <= din;
>
> end if;
> end if;
>end process;
>
>process (clck_re)--read
>begin
> if (clck_re'event and clck_re = '0') then ---e
> if (Re = '1') then
> dout<=rom(conv_integer(RE_address));
> end if;
>
> end if;
>end process;
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 153453
Thank you for your useful comments :), my problem was solved . it was due
to writing clk in dpram, this clk was 100mhz and I expected that the data
was surely written in memory before the next rxclk which was 25MHZ, I
changed writing clk to RXCLK and the problem was solved.
But a question, as it seemed to me that syncing signal are important(cause
my problem was exactly due that) how should I do that??
I don't know how to sync RXD and RXDV?
tnx in advanced for help
Neda Baheri
>First of all, although not related to your query but in general a good
>practice, you need to sync your signals in the FPGA. Like the signals RXD
>and RXDV although in sync with the RXCLK, you need to flop them in the
>system, then use it wherever you want to.
>Now, few things:
>1- why aren't you using the RXDV signal as a write signal to DPRAM and
RXD
>as input?
>
>2- Also, what you can do is, you can use a Coregen FIFO in your design
>instead of DPRAM. For DPRAM, you may require a controller, for FIFO you
>won't. So, just to test your logic, you can use FIFO instead. Then start
>reading when RXDV goes low.
>
>
>
>
>
>>>
>>>---------------------------------------
>>>Posted through http://www.FPGARelated.com
>>>
>>
>>hi
>>tnx for your suggestion, i am working on the fpga program as you
>suggested,
>>but my problem still exist,i used chipscope to debug the problem, the
>data
>>is received fine to fpga but it seemed that the data is not write and
>read
>>back from dual port ram, here is the code. i don't know what's the
>problem
>>and how should i proceed? thanks in advanced for help
>>
>>i read the data received from lan in this process and write in DPRAM,
>>generate a strob to transmit process to start sending data at the
falling
>>edge of RXDV, and capturing the end of packet transmition for reseting
>>write address:
>>
>> always @(posedge RTL_RXCLK)
>> begin
>>
>> /// Reading Data from RXD pin and save it in dpram
>> if(RTL_RXDV)
>> begin
>> write_address2 <= write_address2+1;
>> Ram_Data_In <= RTL_RXD;
>> Ram_Write_Enable<=1;
>> end
>> else
>> Ram_Write_Enable<=0;
>>
>> ///Set Receive Packet Strob to transmit section
>> pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
>> if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
>> begin
>> loopback_data<=1;
>> PacketReceived <= PacketReceived +1;
>>
>> end
>> /// reset Receive Packet Strob
>> if(loopback_data)
>> begin
>> DelayCcLpbackData <= DelayCcLpbackData + 1;
>> if(DelayCcLpbackData>=50)
>> begin
>> loopback_data<=0;
>> DelayCcLpbackData<=0;
>> end
>> end
>>
>> /// capture End ot Trasmission
>> preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
>> if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
>> begin
>> write_address2<=0;
>>
>> end
>> end
>> //////
>>
>> always @(posedge RTL_TXCLK )
>> begin
>> /// Capture Rising edge of Receive packet Strob generated by
>>receive process
>> pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
>> if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
>> begin
>> StartSendingData<=1;
>> end
>>
>> // start transmitting data
>> if(StartSendingData)
>> begin
>> read_address2<=read_address2+1;
>> rgRTL_TXD<=Ram_Data_Out;
>> rgRTL_TXE <=1;
>> re_en<=1;
>> if(read_address2>write_address2)
>> begin
>> read_address2<=0;
>> re_en<=0;
>> rgRTL_TXE <=0;
>>
>>
>>End_Sending_Strobe <= 1;
>> StartSendingData<=0;
>> end
>> end
>>
>> //////////////
>> if(End_Sending_Strobe)
>> begin
>> DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
>> if(DelayCcResetSendStrobe>=50)
>> begin
>> DelayCcResetSendStrobe <= 0;
>> End_Sending_Strobe <= 0;
>> end
>> end
>>
>> end
>>
>>
>>
>> duall_ram2 duall_ram2_in2
>> (
>> .CLCK_re(RTL_TXCLK),
>> .CLCK_wr(RTL_RXCLK),
>> .DIN(Ram_Data_In),
>> .Re(re_en),
>> .RE_ADDRESS(read_address2),
>> .We(Ram_Write_Enable),
>> .wr_address(write_address2),
>> .dout(Ram_Data_Out)
>> );
>>
>>and the module for DPRAM is :
>>entity duall_ram2 is
>> Port ( DIN : in std_logic_vector(3 downto 0);
>> RE_ADDRESS : in std_logic_vector(10 downto 0);
>> wr_address :in std_logic_vector(10 downto 0);
>> CLCK_wr : in std_logic;
>> CLCK_re : in std_logic;
>> We : in std_logic;
>> Re : in std_logic;
>> dout : out std_logic_vector(3 downto 0));
>>end duall_ram2 ;
>>
>>architecture Behavioral of duall_ram2 is
>>type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
>>signal rom: my_data;
>>begin
>>
>>process (clck_wr)--write
>>begin
>> if (clck_wr'event and clck_wr = '0') then
>> if (we = '1') then
>> rom(conv_integer(WR_address)) <= din;
>>
>> end if;
>> end if;
>>end process;
>>
>>process (clck_re)--read
>>begin
>> if (clck_re'event and clck_re = '0') then ---e
>> if (Re = '1') then
>> dout<=rom(conv_integer(RE_address));
>> end if;
>>
>> end if;
>>end process;
>>
>>---------------------------------------
>>Posted through http://www.FPGARelated.com
>>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 153454Hi, I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen is supposed to work but the LTM manual does not mention it. Are there others? A seven inch screen is preferred. Thanks, GaryArticle: 153455
I've got a strange one. Someone's asked me to reprogram an old MACH131SP device, dating from about '95-98. Are any of you still doing this? Any advice? I don't yet know if they have sources (presumably Abel?) or a bitstream. I've got lots of old Lattice software, dating from about 95-2000 - an ispExpert box (floppies probably lost), and a couple of ispDS+ Abel boxes, with lots of floppies, but possibly only supporting pLSI 1K, 2K, and 3K families. I can't find any old JTAG adapters, but I can presumably get access with a current Xilinx Platform Cable USB II. Any thoughts? BTW, I haven't been here for a few years - is this still a good place for FPGAs? What about Stackoverflow/etc? Thanks - EvanArticle: 153456
Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate their designs to a newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are: - these designs where originally created for the 4000 series using schematic capture (XNF format) then moved to Virtex and finally to Spartan 2. Newer parts where written in VHDL though. - The designs contain some async logic (especially the part talking to an MCU using an addres/data bus) and locally divided clocks. - I'm worried at some point extra gates where added to increase the delay. This will break in a much faster FPGA. - The design contains bi-directional busses in several places. My approach would be to convert the XNF parts to VHDL (does someone sell software to do that?) and then check for anomalies due to changes in the FPGA architecture. This could be a huge task. The XNF parts represent several years worth of work. Any suggestions on how to tackle such a project? -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 153457
EML <nospam@nospam.com> writes: > I've got a strange one. Someone's asked me to reprogram an old > MACH131SP device, dating from about '95-98. Are any of you still doing > this? Any advice? I don't yet know if they have sources (presumably > Abel?) or a bitstream. > > I've got lots of old Lattice software, dating from about 95-2000 - an > ispExpert box (floppies probably lost), and a couple of ispDS+ Abel > boxes, with lots of floppies, but possibly only supporting pLSI 1K, > 2K, and 3K families. > > I can't find any old JTAG adapters, but I can presumably get access > with a current Xilinx Platform Cable USB II. If you can find parallel port, there's probably the wiring diagram for a PP to JTAG cable - I know I used a Vantis cable to program some oldish Lattice chips using ispLever Classic recently. > > Any thoughts? BTW, I haven't been here for a few years - is this still > a good place for FPGAs? What about Stackoverflow/etc? There's still people here :) Electronics.stackexchange also covers FPGAs some of the time: http://electronics.stackexchange.com/questions/tagged/fpga and there's a "logic design" proposal on stackexchange also: http://area51.stackexchange.com/proposals/20632/logic-design?referrer=ZolqNc0edhvG1iedac--IA2 Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 153458
Hi, I have an FPGA design that works from JTAG, and now I want to burn a serial flash chip so it will configure itself at powerup. The mode pins should be right for serial self-load, and we'll be using a standard serial flash chip, an M25P16. We have a B&K USB flash burner. I've read the Altera lit and it's not entirely clear to me, so I'd appreciate some help. What Altera file format should I use to burn the serial flash chip? RBF? RPD? Should I tell the programmer to swap ends on bytes or words? Thanks John -- John Larkin, President Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulationArticle: 153459
Martin Thompson wrote: > EML <nospam@nospam.com> writes: > >> I've got a strange one. Someone's asked me to reprogram an old >> MACH131SP device, dating from about '95-98. Are any of you still doing >> this? Any advice? I don't yet know if they have sources (presumably >> Abel?) or a bitstream. >> >> I've got lots of old Lattice software, dating from about 95-2000 - an >> ispExpert box (floppies probably lost), and a couple of ispDS+ Abel >> boxes, with lots of floppies, but possibly only supporting pLSI 1K, >> 2K, and 3K families. >> >> I can't find any old JTAG adapters, but I can presumably get access >> with a current Xilinx Platform Cable USB II. > > If you can find parallel port, there's probably the wiring diagram for a > PP to JTAG cable - I know I used a Vantis cable to program some oldish > Lattice chips using ispLever Classic recently. > >> Any thoughts? BTW, I haven't been here for a few years - is this still >> a good place for FPGAs? What about Stackoverflow/etc? > > There's still people here :) > > Electronics.stackexchange also covers FPGAs some of the time: > > http://electronics.stackexchange.com/questions/tagged/fpga > > and there's a "logic design" proposal on stackexchange also: > > http://area51.stackexchange.com/proposals/20632/logic-design?referrer=ZolqNc0edhvG1iedac--IA2 > > Cheers, > Martin > Lattice also has user forums, but I don't see a lot of activity there. The last time I used a MACH131 or similar part, it was in a PLCC package and I programmed it on a programming platform, probably from Data I/O. You should still be able to do it with a newer box like the BP1400 or whatever the latest BP-Micro programming system is. The data file for these parts was in JEDEC format if I remember correctly. -- GaborArticle: 153460
Nico Coesel wrote: > Because the Xilinx Spartan2 is going to be discontinued in the near > future one of my customers asked me to migrate their designs to a > newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are: > > - these designs where originally created for the 4000 series using > schematic capture (XNF format) then moved to Virtex and finally to > Spartan 2. Newer parts where written in VHDL though. > > - The designs contain some async logic (especially the part talking to > an MCU using an addres/data bus) and locally divided clocks. > > - I'm worried at some point extra gates where added to increase the > delay. This will break in a much faster FPGA. > > - The design contains bi-directional busses in several places. > > My approach would be to convert the XNF parts to VHDL (does someone > sell software to do that?) and then check for anomalies due to changes > in the FPGA architecture. This could be a huge task. The XNF parts > represent several years worth of work. > > Any suggestions on how to tackle such a project? > What was the schematic capture used for the schematics? I believe that XNF is just the netlist format derived from the schematics. I had older projects from this era using both Alliance tools with ViewDraw schematics, and Foundation tools with Aldec schematics. I know that at least the ViewDraw tools were capable of outputing a VHDL structural netlist, perhaps the Aldec tools did, too. If you don't still have an active copy of the original tools, I believe newer versions of Mentor tools can still import older Viewdraw schematics, and Aldec tools can still import the old Xilinx Foundation schematics. It's up to you whether the tool cost is worth more than the re-engineering. In the end, if I were doing this, I'd try to understand what the schematic sections were doing and hand convert them to a modern HDL (behavioral). Then you'd have a better chance of being able to maintain the design down the road. On another note, all of the parts you mentioned were 5V tolerant. I'm not sure what sort of micro's you're interfacing, but if you still have 5V logic in the system any newer parts will need level translators, too. -- GaborArticle: 153461
"John Larkin" <jlarkin@highlandtechnology.com> wrote in message news:3v42l7t4eij7lq6hqj0ui6vmepg744fsup@4ax.com... > > > Hi, > > I have an FPGA design that works from JTAG, and now I want to burn a > serial flash chip so it will configure itself at powerup. The mode > pins should be right for serial self-load, and we'll be using a > standard serial flash chip, an M25P16. We have a B&K USB flash burner. > > I've read the Altera lit and it's not entirely clear to me, so I'd > appreciate some help. > > What Altera file format should I use to burn the serial flash chip? > RBF? RPD? Should I tell the programmer to swap ends on bytes or words? > > Thanks > > John > Why don't you use the Altera EPCS16 or whatever will support your size device? Connect up to the FPGA with a download socket, configure the MSEL pins as per your IO block volts - use AS mode. Use a Terasic USB Blaster, the quartus programmer and the POF file and your good to go. - see the device programming section in the Cyclone III manual. AndyArticle: 153462
On Fri, 2 Mar 2012 19:20:48 -0000, "Andy Bartlett" <andyb@nospamming.net> wrote: > >"John Larkin" <jlarkin@highlandtechnology.com> wrote in message >news:3v42l7t4eij7lq6hqj0ui6vmepg744fsup@4ax.com... >> >> >> Hi, >> >> I have an FPGA design that works from JTAG, and now I want to burn a >> serial flash chip so it will configure itself at powerup. The mode >> pins should be right for serial self-load, and we'll be using a >> standard serial flash chip, an M25P16. We have a B&K USB flash burner. >> >> I've read the Altera lit and it's not entirely clear to me, so I'd >> appreciate some help. >> >> What Altera file format should I use to burn the serial flash chip? >> RBF? RPD? Should I tell the programmer to swap ends on bytes or words? >> >> Thanks >> >> John >> > >Why don't you use the Altera EPCS16 or whatever will support your size >device? Connect up to the FPGA with a download socket, configure the MSEL >pins as per your IO block volts - use AS mode. Use a Terasic USB Blaster, >the quartus programmer and the POF file and your good to go. We want our production people to do this the way they do everything else: program the plugin flash chip at their device programming station, plug it into the board, test and ship. So we want to formally release a file that can be burned into the flash chip on a production basis. > >- see the device programming section in the Cyclone III manual. > I have, and it's not all clear to me. I was hoping that someone here could help, so that I didn't have to try different file formats and byte swaps until I got it to configure. Thanks -- John Larkin, President Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulationArticle: 153463
Gabor <gabor@szakacs.invalid> wrote: >Nico Coesel wrote: >> Because the Xilinx Spartan2 is going to be discontinued in the near >> future one of my customers asked me to migrate their designs to a >> newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are: >> >> - these designs where originally created for the 4000 series using >> schematic capture (XNF format) then moved to Virtex and finally to >> Spartan 2. Newer parts where written in VHDL though. >> >> - The designs contain some async logic (especially the part talking to >> an MCU using an addres/data bus) and locally divided clocks. >> >> - I'm worried at some point extra gates where added to increase the >> delay. This will break in a much faster FPGA. >> >> - The design contains bi-directional busses in several places. >> >> My approach would be to convert the XNF parts to VHDL (does someone >> sell software to do that?) and then check for anomalies due to changes >> in the FPGA architecture. This could be a huge task. The XNF parts >> represent several years worth of work. >> >> Any suggestions on how to tackle such a project? >> > >What was the schematic capture used for the schematics? I believe that Orcad 9.0. That was the last version of Orcad for which the XNF netlist DLL worked. >It's up to you whether the tool cost is worth more than the >re-engineering. In the end, if I were doing this, I'd try to >understand what the schematic sections were doing and hand >convert them to a modern HDL (behavioral). Then you'd have a >better chance of being able to maintain the design down the road. True but there is *years* worth of schematics. Some of the stuff is not trivial either (think signal processing). A few years ago they called me in to fix a VHDL problem and at that point they had converted the XNF files into NGC or NGD files in order to use newer Xilinx tools. I doubt its possible to take an NGC/NGD file to another FPGA family. Still, functional verification is going to be a tough job. >On another note, all of the parts you mentioned were 5V tolerant. >I'm not sure what sort of micro's you're interfacing, but if you still >have 5V logic in the system any newer parts will need level >translators, too. For now I consider that an insignificant problem compared to the FPGA designs :-) -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 153464
On Mar 2, 5:09=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Gabor <ga...@szakacs.invalid> wrote: > >Nico Coesel wrote: > >> Because the Xilinx Spartan2 is going to be discontinued in the near > >> future one of my customers asked me to migrate their designs to a > >> newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are: > > >> - these designs where originally created for the 4000 series using > >> schematic capture (XNF format) then moved to Virtex and finally to > >> Spartan 2. Newer parts where written in VHDL though. > > >> - The designs contain some async logic (especially the part talking to > >> an MCU using an addres/data bus) and locally divided clocks. > > >> - I'm worried at some point extra gates where added to increase the > >> delay. This will break in a much faster FPGA. > > >> - The design contains bi-directional busses in several places. > > >> My approach would be to convert the XNF parts to VHDL (does someone > >> sell software to do that?) and then check for anomalies due to changes > >> in the FPGA architecture. This could be a huge task. The XNF parts > >> represent several years worth of work. > > >> Any suggestions on how to tackle such a project? > > >What was the schematic capture used for the schematics? =A0I believe tha= t > > Orcad 9.0. That was the last version of Orcad for which the XNF > netlist DLL worked. > > >It's up to you whether the tool cost is worth more than the > >re-engineering. =A0In the end, if I were doing this, I'd try to > >understand what the schematic sections were doing and hand > >convert them to a modern HDL (behavioral). =A0Then you'd have a > >better chance of being able to maintain the design down the road. > > True but there is *years* worth of schematics. Some of the stuff is > not trivial either (think signal processing). A few years ago they > called me in to fix a VHDL problem and at that point they had > converted the XNF files into NGC or NGD files in order to use newer > Xilinx tools. I doubt its possible to take an NGC/NGD file to another > FPGA family. > > Still, functional verification is going to be a tough job. > > >On another note, all of the parts you mentioned were 5V tolerant. > >I'm not sure what sort of micro's you're interfacing, but if you still > >have 5V logic in the system any newer parts will need level > >translators, too. > > For now I consider that an insignificant problem compared to the FPGA > designs :-) > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- I'm sorry, but I generally measure schematics in pages or symbols rather than time. "Years" of design time does not necessarily mean that it would take a similar time to copy, translate, or re-design given the existing knowledge base. Signal processing in particular very often represents a number of regular structures like filters for which you have many more options for implementation now. In fact you could end up with very inefficient use of newer devices if you don't rework a lot of the design to use the available DSP functions that were not available on Spartan 2 or earlier devices. You'll probably need to re-work the bidirectional buses (I assume you mean internal?) since newer parts have not internal tri-state drivers. So in the end there's probably not a real simple method to run your old project through some tools to come up with a working design on a new platform. Regards, GaborArticle: 153465
On Mar 2, 9:40=A0pm, John Larkin <jlar...@highlandtechnology.com> wrote: > On Fri, 2 Mar 2012 19:20:48 -0000, "Andy Bartlett" > > <an...@nospamming.net> wrote: > > >"John Larkin" <jlar...@highlandtechnology.com> wrote in message > >news:3v42l7t4eij7lq6hqj0ui6vmepg744fsup@4ax.com... > > >> Hi, > > >> I have an FPGA design that works from JTAG, and now I want to burn a > >> serial flash chip so it will configure itself at powerup. The mode > >> pins should be right for serial self-load, and we'll be using a > >> standard serial flash chip, an M25P16. We have a B&K USB flash burner. > > >> I've read the Altera lit and it's not entirely clear to me, so I'd > >> appreciate some help. > > >> What Altera file format should I use to burn the serial flash chip? > >> RBF? RPD? Should I tell the programmer to swap ends on bytes or words? > > >> Thanks > > >> John > > >Why don't you use the Altera EPCS16 or whatever will support your size > >device? Connect up to the FPGA with a download socket, configure the MSE= L > >pins as per your IO block volts - use AS mode. Use a Terasic USB Blaster= , > >the quartus programmer and the POF file and your good to go. > > We want our production people to do this the way they do everything > else: program the plugin flash chip at their device programming > station, plug it into the board, test and ship. So we want to formally > release a file that can be burned into the flash chip on a production > basis. > > > > >- see the device programming section in the Cyclone III manual. > > I have, and it's not all clear to me. I was hoping that someone here > could help, so that I didn't have to try different file formats and > byte swaps until I got it to configure. > > Thanks > > -- > > John Larkin, President > Highland Technology, Inc > > jlarkin at highlandtechnology dot comhttp://www.highlandtechnology.com > > Precision electronic instrumentation > Picosecond-resolution Digital Delay and Pulse generators > Custom laser controllers > Photonics and fiberoptic TTL data links > VME thermocouple, LVDT, synchro =A0 acquisition and simulation One possible way is to use sof2flash utility supplied with Nios2 SDK. I generates .flash file in Motorola S3 format. Then, if you want, you can convert to intel hex or to plain binary with standard objcopy utility. But programming the way you chose is certainly not the fastest. One of faster ways is: 1, Create small FPGA design that contains only nios2 processor and Altera's epcs component. 2. Load it to your Cyclon with quartus programmer. 3. Burn flash with nios2-flash-programmer utility.Article: 153466
On Fri, 02 Mar 2012 10:39:34 -0800, John Larkin <jlarkin@highlandtechnology.com> wrote: > > >Hi, > >I have an FPGA design that works from JTAG, and now I want to burn a >serial flash chip so it will configure itself at powerup. The mode >pins should be right for serial self-load, and we'll be using a >standard serial flash chip, an M25P16. We have a B&K USB flash burner. > >I've read the Altera lit and it's not entirely clear to me, so I'd >appreciate some help. > >What Altera file format should I use to burn the serial flash chip? >RBF? RPD? Should I tell the programmer to swap ends on bytes or words? > >Thanks > >John OK, I got it to work: Get the THING.RBF file from the Altera software. Bit-swap all the bytes and save as THING.ROM. Program that into an M25P16 serial flash chip on the B&K USB programmer. Plug that in. I wrote a little Windows command-line bit swapper program if anybody wants it. -- John Larkin, President Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulationArticle: 153467
Gabor <gabor@alacron.com> wrote: (snip) > I'm sorry, but I generally measure schematics in pages or symbols > rather than time. "Years" of design time does not necessarily mean > that it would take a similar time to copy, translate, or re-design > given the existing knowledge base. It could even take longer, but one would hope not. > Signal processing in particular very often represents a > number of regular structures like filters for which > you have many more options for implementation now. In fact you > could end up with very inefficient use of newer devices if you don't > rework a lot of the design to use the available DSP functions that > were not available on Spartan 2 or earlier devices. The CLB changed pretty significantly from XC4000 to Spartan, especially in the carry logic. That may or may not matter to a specific design. > You'll probably need to re-work the bidirectional buses > (I assume you mean internal?) since newer parts have not > internal tri-state drivers. As I understand it, the tools will simulate tri-state lines. Depending on the design, they may do better or worse than a person would redesigning the same logic. > So in the end there's probably not a real simple method to run > your old project through some tools to come up with a working > design on a new platform. Even the smallest of the newer families is pretty large, so it might be that one can throw more logic to the problem for the same result. Likely, though, that one can get the existing design to run faster, or otherwise better, adapting to the new family. -- glenArticle: 153468
John Larkin <jlarkin@highlandtechnology.com> writes: > What Altera file format should I use to burn the serial flash chip? > RBF? RPD? Should I tell the programmer to swap ends on bytes or words? My experience on the last part is, you may just have to experiment to find out. We used a 16-bit parallel flash in byte mode once and had a CPLD read the flash in byte mode and push the data to the FPGA (Virtex 4 from Xilinx). The problem was, there was just no information on the flash data sheet about the byte order in byte mode. So we experimented and figured out which way the data should be in the flash, writing the flash with the on board software at that point. And of course when we wanted to write the flash with a programmer, things were the opposite of the software situation... Byte swap was explicitly done in software, but somehow the flash programmer needed byte swap off to create the same flash contents.Article: 153469
My design worked for about 3 hours and now gives me this error. I just can't understand what is wrong with it now. I didn't do anything wrong. !Error: JTAG chain problem detected !Error: The TDI connection to the first detected device EP2C8 might be shorted to VCC or is an open circuit !Error: The TCK and TMS connections to the device before the first detected device EP2C8 might have a problem !Info: Detected 1 device(s) !Info: Device 1: EP2C8 device is EP2C8Q208C8 TDI pulled high with 10Kohm resistor also TMS TCK pulled down with same resistor value Pin 2 on JTAG header connected to GND Pins 4 and 6 connected to VCC 3.3V Pin 10 connected to GND TDO connected directly to cyclone II MSEL 0 and 1 to GND nCE to GND also on board is used EPCS4SI8 but I disconnect that one but problem remains. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153470
Hi all, I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there are several different area types LUT, FF, BRAM, DSP. Is there way look at a uniform cost model which combines all of then. 1. Some early version of ISE had equivalent gate count number for an VHDL implementation. But it's not available anymore. 2. Slices seems to be the common unit of comparison. This is consists of LUT and FF. But how about BRAM, DSP. Can I say estimate the BRAM cost like this? One 6input LUT(V6) = 64 x 1 bit RAM 1 Slice = 4 LUT = 256 x 1 bit RAM 1BRAM = 36kb => 144 slices For DSP, I wrote simple code with 25x18 multiplier and then 48 bit accumulator and set no dsp usage in synthesis to get the slice number as 154 slices. (This was done using a Virtex 6.) Is this a good estimate? Are they are any alternative ways to measure an uniform cost of FPGA implementation? Thanks in advance.:)Article: 153471
On Mar 6, 8:43=A0am, Shakes <shakith.ferna...@gmail.com> wrote: > Hi all, > > I have question on measuring FPGA area. Measuring area cost of the FPGA i= mplementation is tricky because there > are several different area types LUT, FF, BRAM, DSP. Is there way look > at a uniform cost model which combines all of then. > > 1. Some early version of ISE had equivalent gate count number for an > VHDL implementation. But it's not available anymore. > 2. Slices seems to be the common unit of comparison. This is consists > of LUT and FF. But how about BRAM, DSP. > Can I say estimate the BRAM cost like this? > One 6input LUT(V6) =3D 64 x 1 bit RAM > 1 Slice =3D 4 LUT =3D 256 x 1 bit RAM > 1BRAM =3D 36kb =3D> 144 slices > > For DSP, I wrote simple code with 25x18 multiplier and then 48 bit > accumulator and set no dsp usage in synthesis to get the slice number > as 154 slices. (This was done using a Virtex 6.) > > Is this a good estimate? > Are they are any alternative ways to measure an uniform cost of FPGA > implementation? > > Thanks in advance.:) I'm not clear on what you are trying to achieve. The point of including RAM and DSP on FPGAs is to reduce the area used as well as accelerate the speed of designs. So why would you want to count the slice usage of a design that you expect will be implemented using DSP blocks? Are you going to count the equivalent slices for a memory based design? What do you want this number for? RickArticle: 153472
Shakes <shakith.fernando@gmail.com> wrote: > I have question on measuring FPGA area. Measuring area cost > of the FPGA implementation is tricky because there > are several different area types LUT, FF, BRAM, DSP. Is there way look > at a uniform cost model which combines all of then. Useful measurments before BRAM and DSP were never very good, but now it is close to impossible. Why do you want such a measurment? The result might depend on why. > 1. Some early version of ISE had equivalent gate count number for an > VHDL implementation. But it's not available anymore. > 2. Slices seems to be the common unit of comparison. This is consists > of LUT and FF. But how about BRAM, DSP. But slices usually have more than one LUT and FF, and many are now using 6LUT instead of the previous 4LUT. > Can I say estimate the BRAM cost like this? Many designs don't use BRAM at all, others might not use FF, yet they are still on the chip. > One 6input LUT(V6) = 64 x 1 bit RAM > 1 Slice = 4 LUT = 256 x 1 bit RAM > 1BRAM = 36kb => 144 slices The traditional ASIC method was the equivalent in 2 input NAND, which is four transistors in CMOS. So the conversion was to take the number of transistors and divide by four. Not so bad. If you figure the average gates used in a LUT, convert with that. An FF might be about four gate equivalent. The usual SRAM cell is four transistors, plus one or two for gating, plus address decoding. So 1.5 to 2 gates/bit might be close. > For DSP, I wrote simple code with 25x18 multiplier and then 48 bit > accumulator and set no dsp usage in synthesis to get the slice number > as 154 slices. (This was done using a Virtex 6.) > Is this a good estimate? > Are they are any alternative ways to measure an uniform > cost of FPGA implementation? Not really. I have a design that is scalable, so I can vary the amount of logic in a chip. For a fairly wide range, the speed is almost inversely proportional to the amount of logic. That is likely true for other designs. That means that if you give a size, you also should give an appropriate speed. -- glenArticle: 153473
Shakes wrote: > Hi all, > > I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there > are several different area types LUT, FF, BRAM, DSP. Is there way look > at a uniform cost model which combines all of then. > > 1. Some early version of ISE had equivalent gate count number for an > VHDL implementation. But it's not available anymore. > 2. Slices seems to be the common unit of comparison. This is consists > of LUT and FF. But how about BRAM, DSP. > Can I say estimate the BRAM cost like this? > One 6input LUT(V6) = 64 x 1 bit RAM > 1 Slice = 4 LUT = 256 x 1 bit RAM > 1BRAM = 36kb => 144 slices > > For DSP, I wrote simple code with 25x18 multiplier and then 48 bit > accumulator and set no dsp usage in synthesis to get the slice number > as 154 slices. (This was done using a Virtex 6.) > > Is this a good estimate? > Are they are any alternative ways to measure an uniform cost of FPGA > implementation? > > Thanks in advance.:) Unless your design is intended to be implemented in an ASIC, it doesn't make a lot of sense to look for a uniform metric like gate count. In an FPGA, you get a limited number of each resource. At least for Xilinx tools, you also get a report showing the percentage of each resource used by your design. If you wanted to know how many of your designs fit in a given FPGA, or how much of the FPGA is left over for other stuff, then the percentage of each resource is the best way to look at it. If you insist on applying a single metric, then I would suggest considering each resource based on the number available. For example if your device has 14K LUTs and 140 block RAMs, then a block RAM would be worth 100 LUTs because that's the ratio of LUTs to BRAM in that device. Still, an end user of your design would need to know the individual numbers in order to get a useful estimate of the FPGA required based on used and remaining resources. -- GaborArticle: 153474
On Mar 6, 2:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote: > 2. Slices seems to be the common unit of comparison. Slices are often used, but they are a stupid way to compare area. The real comparison for logic area is LUTs. The number of slices will depend greatly on placement. In an FPGA that is mostly empty a circuit might spread out evenly and it might be that there is only one LUT placed into each slice. The same circuit mapped to the same number of LUTs might take up only half the number of slices if placed into a smaller FPGAs, because each slice gets two LUTs. The LUTs in a slice are greatly independent, so this is almost always possible, the tools just don't do it if it isn't necessary. The LUT count will remain the same in both cases, so that should be used for comparison. Kolja
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