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Messages from 153625

Article: 153625
Subject: Re: LX9 and internal reset - Do I need one?
From: Claude Sylvain <csylvain@electro-technica.com>
Date: Thu, 05 Apr 2012 17:54:54 -0400
Links: << >>  << T >>  << A >>

On 2012-04-04 20:03, Giuseppe Marullo wrote:

 >
 > I am slowly implementing my morse keyer using a Avnet LX9 board. BTW,
 > thanks all for your sugggestions, in the end I decided for this one
 > (Gabor, you won!).
 >
 > I stuffed a lot of things in the project (A serial LCD, several
 > PMODs,
 > like an encoder, a BF ampli and so on), I plan to add USB Host
 > functionality to save settings on a USB stick (HobbyTronics has some
 > *nice* gadgets!):
 >
 > http://www.hobbytronics.co.uk/prototyping/usb-host-board
 >
 > To cut a long story short, I think I will run out of pins (16 in
 > total!).
 >
 > I would like to know if I could save one pin for the reset.
 >
 > I actually have a active high pushbutton called user reset, and used
 > that to reset the board when I need it. This one is not one of the 16
 > user I/O I have.
 >
 > I don't think it will do the reset trick on power up, so I guess
 > everything will start inizialized to zero.
 >
 > My default state on each FSM is 0, so no big deal.
 >
 > I use that signal as reset, and so far everything is fine. I use
 > positive logic for reset, and the momentary switch is active high.
 >
 > Now, is it enough or should I need a dedicated reset pin that runs
 > high
 > at startup to be sure?
 >
 > In the testbench obviously I simulate the pressing of the button, but
 > in
 > a real case scenario, how would it behave if I would use one hot
 > encoded
 > FSM for example (no default 0 state then)?
 >

- I suggest you to built in the FPGA a so called "Power On Reset"
   circuit, followed by some "Reset Bridge" (one for each clock domain).

- As you certainly already know, when using an (internal) power on
   reset, the external reset pin can be optional.


Claude



--- Posted via news://freenews.netfront.net/ - Complaints to news@netfront.net ---

Article: 153626
Subject: Re: Mandelbrot set on Spartan3
From: Frank Buss <fb@frank-buss.de>
Date: Fri, 06 Apr 2012 08:17:41 +0200
Links: << >>  << T >>  << A >>
Thorsten Kiefer wrote:

> I cannot post the source, because I took most of the modules from a book.
> But I can post the main file, because this is my own work, and here
> the color calculation takes place. Do you think, people would be
> satisfied with the main.vhd file ?
> The main file shows how to use the modules from the book and how
> to use Xilinx' FP-IP-Cores.

You can ask the author of the book. Usually they post the source code
anyway on their webpages and allows to use and publish it for your own
projects, depending on the licence.

> I'm not sure if I can publish only parts of a project on the hosters
> you mentioned.

Use http://pastebin.com , or even better, write a webpage (or blog) and
explain how you did it. I would be interested in how easy it is to use
floating point numbers on a FPGA.

-- 
Frank Buss, http://www.frank-buss.de
electronics and more: http://www.youtube.com/user/frankbuss

Article: 153627
Subject: Re: Mandelbrot set on Spartan3
From: Thorsten Kiefer <thorstenkiefer@gmx.de>
Date: Fri, 06 Apr 2012 10:37:02 +0200
Links: << >>  << T >>  << A >>
Am 06.04.2012 08:17, schrieb Frank Buss:
> Thorsten Kiefer wrote:
>
>> I cannot post the source, because I took most of the modules from a book.
>> But I can post the main file, because this is my own work, and here
>> the color calculation takes place. Do you think, people would be
>> satisfied with the main.vhd file ?
>> The main file shows how to use the modules from the book and how
>> to use Xilinx' FP-IP-Cores.
>
> You can ask the author of the book. Usually they post the source code
> anyway on their webpages and allows to use and publish it for your own
> projects, depending on the licence.
>
>> I'm not sure if I can publish only parts of a project on the hosters
>> you mentioned.
>
> Use http://pastebin.com , or even better, write a webpage (or blog) and
> explain how you did it. I would be interested in how easy it is to use
> floating point numbers on a FPGA.
>

I'm a bit too lazy to explain it.
The code is not too complicated, and accessing the floating point cores
is very easy.

http://pastebin.com/x3NHdtqE


Article: 153628
Subject: Re: Digital Tachometer VHDL
From: j.m.granville@gmail.com
Date: Fri, 6 Apr 2012 15:39:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, March 26, 2012 12:25:21 AM UTC+12, tachometer wrote:
> Hi,
> The project asks me to count the Rotations/per Minute from a motor.
> It has to be in the range 19-98 RPM, the measurement time is 1.1s, and the
> display resolution is 0.1 .

Missing here is how many pulses per revolution ?

If it is one, how many pulses will you get in 1.1s, at 19 rpm ?
If it is >>1, how many PPR do you need to resolve 0.1rpm, in 1.1sec ?

Also google Reciprocal frequency counting.

You have been given a relatively low resolution of 0.1, which is only 99.9 FSV,
so a smart student will spot that only 999 entries in a table, to give RPM direct from any scaled time.

Does your target hardware support tables ? (ie initialized RAM )

Is the display 3x7 segment LED ?  [19-98 is fixed decimal] 

-jg

Article: 153629
Subject: Any people having experience with HWICAP?
From: chthon <jurgen.defurne@gmail.com>
Date: Sat, 7 Apr 2012 00:19:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear all,

As a lab project I need to check the possibilities of the HWICAP
interface in the context of setting up a SoC using MicroBlaze and
doing a partial reconfigure (in this case most probably through the
serial interface). I am doing this on an Atlys board.

I have a working SoC and the example C code runs, with affirmative
exit status on the HWICAP.

When I embed the SoC in a top level VHDL for ISE, everything runs
still OK.

However, when I add a small logic block, connected to the switches and
LED's of the board, the HWICAP does not
initialize anymore. The rest of the circuit does work, because I am
able to run the program. Adding more diagnostic code showed that the
HWICAP fails to initialize. When I disconnect the logic block,
everything runs fine again.

I wrote a bitstream decoder, and inspecting all the generated
bitstreams showed that the PERSIST is always off, so the problem is
not there either.

I have a topic on the Xilinx forums, I get referenced to the 'free SEU
Monitor IP core for S6' but when I search for it, I only get
references to that topic on the forum or the Xilinx SEM IP.

The next thing I will try is to create the two designs, with and
without logic block, and see if I can create a differential bitstream
and use that to load through the working HWICAP design.

Any other ideas and tips are welcome.

Regards,

Jurgen

Article: 153630
Subject: Watchdog reset for fpga designs
From: "nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com>
Date: Sat, 07 Apr 2012 02:28:23 -0500
Links: << >>  << T >>  << A >>
hi
i 'm designing a board with fpga spartan 3(Industrial series) . while
testing the board, specially when there is spike on any input pin of fpga,
fpga enters unknown sate and won't do its job correctly, but after reset it
continues working. is it a common design practice to have an external
watchdog timer to reset the fpga in fpga based boards in case it is in
unknown state, like watchdog timer in microcontrollers? I thought that
fpgas are more stable than microcontroller in response to noise, but in my
test design I experienced the same thing similar to microcontrollers.
are gates in fpga altered due to noise??
tnx in advanced for any comment	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153631
Subject: Re: Any people having experience with HWICAP?
From: chthon <jurgen.defurne@gmail.com>
Date: Sat, 7 Apr 2012 01:19:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 7, 9:19=A0am, chthon <jurgen.defu...@gmail.com> wrote:
> Dear all,
>
> As a lab project I need to check the possibilities of the HWICAP
> interface in the context of setting up a SoC using MicroBlaze and
> doing a partial reconfigure (in this case most probably through the
> serial interface). I am doing this on an Atlys board.
>
> I have a working SoC and the example C code runs, with affirmative
> exit status on the HWICAP.
>
> When I embed the SoC in a top level VHDL for ISE, everything runs
> still OK.
>
> However, when I add a small logic block, connected to the switches and
> LED's of the board, the HWICAP does not
> initialize anymore. The rest of the circuit does work, because I am
> able to run the program. Adding more diagnostic code showed that the
> HWICAP fails to initialize. When I disconnect the logic block,
> everything runs fine again.
>
> I wrote a bitstream decoder, and inspecting all the generated
> bitstreams showed that the PERSIST is always off, so the problem is
> not there either.
>
> I have a topic on the Xilinx forums, I get referenced to the 'free SEU
> Monitor IP core for S6' but when I search for it, I only get
> references to that topic on the forum or the Xilinx SEM IP.
>
> The next thing I will try is to create the two designs, with and
> without logic block, and see if I can create a differential bitstream
> and use that to load through the working HWICAP design.
>
> Any other ideas and tips are welcome.
>
> Regards,
>
> Jurgen

So, this way of working fails because of the following:

ERROR:Bitgen:339 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, is not compatible with partial bitstreams. For more
information, please reference Xilinx Answer Record 39999.
Error:Bitgen:157 - Bitgen will terminate because of the above errors.

Article: 153632
Subject: Re: Watchdog reset for fpga designs
From: "Andy Bartlett" <andyb@nospamming.net>
Date: Sat, 7 Apr 2012 09:52:04 +0100
Links: << >>  << T >>  << A >>

"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message 
news:F5udnToY5aAKceLSnZ2dnUVZ_rSdnZ2d@giganews.com...
> hi
> i 'm designing a board with fpga spartan 3(Industrial series) . while
> testing the board, specially when there is spike on any input pin of fpga,
> fpga enters unknown sate and won't do its job correctly, but after reset 
> it
> continues working. is it a common design practice to have an external
> watchdog timer to reset the fpga in fpga based boards in case it is in
> unknown state, like watchdog timer in microcontrollers? I thought that
> fpgas are more stable than microcontroller in response to noise, but in my
> test design I experienced the same thing similar to microcontrollers.
> are gates in fpga altered due to noise??
> tnx in advanced for any comment
>
> --------------------------------------- 
> Posted through http://www.FPGARelated.com

Never known an FPGA (Altera) to crash in over 25 years. Maybe your PSU volts 
are suspect.
I always enable the FPGA CRC checking which will cause the device to 
'reboot' from external memory if the internally calculated CRC ever differs 
from the CRC supplied during loading.
Maybe Xilinx do not have this feature?

Andy 



Article: 153633
Subject: Re: Any people having experience with HWICAP?
From: chthon <jurgen.defurne@gmail.com>
Date: Sat, 7 Apr 2012 05:56:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Saturday, April 7, 2012 9:19:51 AM UTC+2, chthon wrote:
> Dear all,
>=20
> As a lab project I need to check the possibilities of the HWICAP
> interface in the context of setting up a SoC using MicroBlaze and
> doing a partial reconfigure (in this case most probably through the
> serial interface). I am doing this on an Atlys board.
>=20
> I have a working SoC and the example C code runs, with affirmative
> exit status on the HWICAP.
>=20
> When I embed the SoC in a top level VHDL for ISE, everything runs
> still OK.
>=20
> However, when I add a small logic block, connected to the switches and
> LED's of the board, the HWICAP does not
> initialize anymore. The rest of the circuit does work, because I am
> able to run the program. Adding more diagnostic code showed that the
> HWICAP fails to initialize. When I disconnect the logic block,
> everything runs fine again.
>=20
> I wrote a bitstream decoder, and inspecting all the generated
> bitstreams showed that the PERSIST is always off, so the problem is
> not there either.
>=20
> I have a topic on the Xilinx forums, I get referenced to the 'free SEU
> Monitor IP core for S6' but when I search for it, I only get
> references to that topic on the forum or the Xilinx SEM IP.
>=20
> The next thing I will try is to create the two designs, with and
> without logic block, and see if I can create a differential bitstream
> and use that to load through the working HWICAP design.
>=20
> Any other ideas and tips are welcome.
>=20
> Regards,
>=20
> Jurgen

I did overcome one obstacle. By doing post-synthesis floorplan design and c=
onstraining my logic block onto another part of the FPGA, I succeeded into =
getting what I wanted: a working SoC, a working separate logic block, and H=
WICAP which works again. So, somewhere there must have been some interferen=
ce between this logic block and HWICAP circuitry.

Article: 153634
Subject: Re: Watchdog reset for fpga designs
From: Tim Wescott <tim@seemywebsite.please>
Date: Sat, 07 Apr 2012 13:24:41 -0500
Links: << >>  << T >>  << A >>
On Sat, 07 Apr 2012 02:28:23 -0500, nba83 wrote:

> hi
> i 'm designing a board with fpga spartan 3(Industrial series) . while
> testing the board, specially when there is spike on any input pin of
> fpga, fpga enters unknown sate and won't do its job correctly, but after
> reset it continues working. is it a common design practice to have an
> external watchdog timer to reset the fpga in fpga based boards in case
> it is in unknown state, like watchdog timer in microcontrollers? I
> thought that fpgas are more stable than microcontroller in response to
> noise, but in my test design I experienced the same thing similar to
> microcontrollers. are gates in fpga altered due to noise?? tnx in
> advanced for any comment
> 					
> --------------------------------------- Posted through
> http://www.FPGARelated.com

Define "spike" -- do you mean a runt pulse, or do you mean an overvoltage 
spike?

The FPGA designers that I work with personally are sensitive to their 
designs locking up or otherwise getting wedged in illegal states, and 
have a plethora of design measures to prevent that from happening.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Article: 153635
Subject: Re: CPU Design in Xilinx Spartan 3E
From: "tu" <tu_ind@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.in>
Date: Sun, 08 Apr 2012 13:47:17 -0500
Links: << >>  << T >>  << A >>

>
>http://www.bitlib.de/pub/mproz/mproz3_e.pdf
>http://www.bitlib.de/pub/mproz/mproz3.zip
>
>is an example for a simple SPARTAN-3E cpu using the internal memory
>as program memory and leds as output.
>
>
Thank you indeed, but i am unable to understand the led code and the
corresponding hardware.
could you please explain it. The board I have with me is Spartan-3E starter
kit from diligent, can i use the on board led?	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153636
Subject: Re: CPU Design in Xilinx Spartan 3E
From: "tu" <tu_ind@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.in>
Date: Sun, 08 Apr 2012 13:53:07 -0500
Links: << >>  << T >>  << A >>

>> Posted throughhttp://www.FPGARelated.com
>
>for a case of using normal cpu, there are some programming pins on
>that cpu to allow your cpu programmer to load the software into the
>cpu. in this case where you make a cpu out of fpga, you could assign
>some fpga pins as cpu programming pins, and let your cpu programmer
>"talk" to the cpu thru those pins.
>

I understand, you are talking about serial tx and rx pins, yes that can be
done, 
could you please tell me how can i do that? do i need to write the ucf file
for that, if you can explain it will be a great help for me. can you please
give an example. thank you	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153637
Subject: Re: What's a good book on FPGA CPU design?
From: "tu" <tu_ind@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.in>
Date: Sun, 08 Apr 2012 13:56:55 -0500
Links: << >>  << T >>  << A >>
>Pratip Mukherjee <pratipm@hotmail.com> wrote in message
news:<Xns9421CF58A715Fpratipmhotmailcom@204.127.199.17>...
>> Hi,
>> Is there a good book on FPGA CPU design which starts with a simple cpu,

>> like Xilinx PicoBlaze, and takes the user through different aspect of
cpu 
>> design like instruction set design, pipelining, etc., etc, at the same
time 
>> keeping the focus on actual implementaion in a FPGA and not on
theoritical 
>> discussions? Am I asking for too much?
>> Thanks.
>> 
>> Pratip Mukherjee.
>
>You can also check out my site
>
>http://www.c-nit.net/
>
>Sumit
>
the link is not wring, please provide the correct link.	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153638
Subject: Re: LX9 and internal reset - Do I need one?
From: Giuseppe Marullo <giuseppe.marullonospam@iname.com>
Date: Mon, 09 Apr 2012 00:00:41 +0200
Links: << >>  << T >>  << A >>
>
> - I suggest you to built in the FPGA a so called "Power On Reset"
> circuit, followed by some "Reset Bridge" (one for each clock domain).
>
> - As you certainly already know, when using an (internal) power on
> reset, the external reset pin can be optional.
Claude,
many thanks about your answer.

This is what I wrote to implement the automagic reset time:

reg [3:0] rst_buffer;

wire user_reset = ~rst_buffer[3]; // I need a active reset signal

always @(posedge user_clock or posedge user_button)

if (user_button == 1'b1)  // the pushbutton is high when pressed
   rst_buffer <= 4'b0;
else
   rst_buffer <= {rst_buffer[2:0], 1'b1};

User button is positive and async, probably I also need a debouncing cicuit.

I only have a clock domain.

 > - As you certainly already know, when using an (internal) power on
 > reset, the external reset pin can be optional.

I am still learning things, this is for hobby. I have the pushbuton 
already on the board, so ti does make sense to avoid using another pin 
just for this.

Giuseppe Marullo

Article: 153639
Subject: Best FPGA for algorithmic acceleration
From: Jordan Fix <jfix71@gmail.com>
Date: Sun, 8 Apr 2012 22:13:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

I'm looking at different options to use FPGAs as coprocessors for
algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
the Altera Stratix IV (360, 530 or 820), what would be my best option?
The Xilinx Spartan 6 may also be a possibility.

Thanks,
Jordan

Article: 153640
Subject: Re: Best FPGA for algorithmic acceleration
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 9 Apr 2012 06:12:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jordan Fix <jfix71@gmail.com> wrote:

> I'm looking at different options to use FPGAs as coprocessors for
> algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
> the Altera Stratix IV (360, 530 or 820), what would be my best option?
> The Xilinx Spartan 6 may also be a possibility.

There are a number of different families from each company, many of
which will work will for algorithmic acceleration.

If there is a reason to use one over the other, it will likely
depend on details of the problem at hand. 

For many such designs, the product of the number of CLBs and 
the clock speed that you can run it at is most important, in 
addition to the cost per chip. 

-- glen

Article: 153641
Subject: RPMs in xilinx 13.2
From: "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com>
Date: Mon, 09 Apr 2012 03:53:38 -0500
Links: << >>  << T >>  << A >>
Hi,
I am using xilinx 13.2 for synthesis and implementation of my design. I
wanted to create RPMs of some small logic so that I can reuse it anywhere
in my design by just instantiating. But I cannot find any relevant
documentation on the internet, and the documentation I found is for
previous versions using the floorplan method. Can anyone direct me to a
proper documentation or some guide or link, that would be great.

Also, when I create RPMs and I map the components by hand, whenever i will
instantiate it, the components will be placed in the same order or will
they change depending on the complete design and routing?



Regards
Muhammad Hassan	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153642
Subject: Re: Best FPGA for algorithmic acceleration
From: Frank Buss <fb@frank-buss.de>
Date: Mon, 09 Apr 2012 11:07:07 +0200
Links: << >>  << T >>  << A >>
Jordan Fix wrote:
> I'm looking at different options to use FPGAs as coprocessors for
> algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
> the Altera Stratix IV (360, 530 or 820), what would be my best option?
> The Xilinx Spartan 6 may also be a possibility.

What algorithm do you want to implement with it? If you don't need many
parallel calculation or hard realtime, usually a fast PC with a GPU and
something like CUDA or OpenCL is more cost-effective, and much easier to
program.

-- 
Frank Buss, http://www.frank-buss.de
electronics and more: http://www.youtube.com/user/frankbuss

Article: 153643
Subject: Re: Best FPGA for algorithmic acceleration
From: Andy <jonesandy@comcast.net>
Date: Mon, 9 Apr 2012 05:56:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 9, 12:13=A0am, Jordan Fix <jfi...@gmail.com> wrote:
> Hello,
>
> I'm looking at different options to use FPGAs as coprocessors for
> algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
> the Altera Stratix IV (360, 530 or 820), what would be my best option?
> The Xilinx Spartan 6 may also be a possibility.
>
> Thanks,
> Jordan

Things to consider when choosing an FPGA for algorithm accelleration,
presumably off-loading a CPU, include what types of communications/
memory interfaces would be required to support transferring required
data to/frrom the CPU or system? How well does each candidate support
those interfaces?

 Also, what types of internal memory (multi-port, different read/write
data widths, ECC protected, etc), and how much, would be required to
support the algorithm? How well would each candidate support that?

Andy

Article: 153644
Subject: Re: Watchdog reset for fpga designs
From: andy.mcclelland@tesco.net
Date: Mon, 9 Apr 2012 08:14:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Saturday, April 7, 2012 3:28:23 AM UTC-4, nba83 wrote:
> hi
> i 'm designing a board with fpga spartan 3(Industrial series) . while
> testing the board, specially when there is spike on any input pin of fpga=
,
> fpga enters unknown sate and won't do its job correctly, but after reset =
it
> continues working. is it a common design practice to have an external
> watchdog timer to reset the fpga in fpga based boards in case it is in
> unknown state, like watchdog timer in microcontrollers? I thought that
> fpgas are more stable than microcontroller in response to noise, but in m=
y
> test design I experienced the same thing similar to microcontrollers.
> are gates in fpga altered due to noise??
> tnx in advanced for any comment	  =20

By "reset" do you mean a re-programming/configuration of the FPGA, or a res=
et of the already configured logic?

I'm guessing that you mean the latter, and that the internal logice (a stat=
e machine, perhaps) is getting into an illegal state.  Further guessing tha=
t a short pulse/spike is being seen by some FFs, but not all of those to wh=
ich it fans out to.  I.E. metastability through lack of proper synchronisat=
ion of the incoming signal.

As Tim says ther are a number of techniques used to avoid these kinds of pr=
oblems, depending on the nature of the logic and the degree of resilience r=
equired.  A first line of defence is to register all inputs with the FFs cl=
ocked by the same clock as used by the logic that it feeds, better still is=
 two cascaded FFs.

Careful design of the state machines themselves is also important, e.g. tra=
pping illegal states and transitioning to a legal one (usually the reset or=
 initial state).

Without the specifics of your case it is difficult to give a more specific =
solution, but I hope that we have pointed you in the right direction.

--=20
Andy McC

Article: 153645
Subject: Re: Best FPGA for algorithmic acceleration
From: John Adair <g1@enterpoint.co.uk>
Date: Mon, 9 Apr 2012 10:24:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
I think it has been already siad that it depends on what you are doing
but I will make some general comments.

Some applications like data manipulation like video data need lot's of
memory so easy access to DDR memory might be a point to look for. As
an example Spartan-6 has a hardened controller which is good but only
if the 2/4 16bit potential interfaces offer enough bandwidth and size.
Other FPGA could offer harder to implement but bigger and faster
DDR2/3.

More expensive FPGAs e.g. Virtex and Stratix tend to offer more
internaal SRAM and DSP blocks so this may be a reason to go this way.
I weill counter that by saying an array approach like our Merrick3/4/6
boards might be a lower power, cheaper, alternative.

You might find that you will need a higher performance PCIe interface
to handle your data flow into a host PC. Here the more expensive FPGAs
tend to be better but there are other ways that might be worth
consideration.

These are all general statements and real way to do this is to look at
the system design level. If want more specific comment contact me
though the Enterpoint contact page http://enterpoint.co.uk/about/ and
I will happy to discuss this in more detail.

John Adair
Enterpoint Ltd.

On Apr 9, 6:13=A0am, Jordan Fix <jfi...@gmail.com> wrote:
> Hello,
>
> I'm looking at different options to use FPGAs as coprocessors for
> algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
> the Altera Stratix IV (360, 530 or 820), what would be my best option?
> The Xilinx Spartan 6 may also be a possibility.
>
> Thanks,
> Jordan


Article: 153646
Subject: Re: Best FPGA for algorithmic acceleration
From: nico@puntnl.niks (Nico Coesel)
Date: Mon, 09 Apr 2012 21:14:51 GMT
Links: << >>  << T >>  << A >>
Frank Buss <fb@frank-buss.de> wrote:

>Jordan Fix wrote:
>> I'm looking at different options to use FPGAs as coprocessors for
>> algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or
>> the Altera Stratix IV (360, 530 or 820), what would be my best option?
>> The Xilinx Spartan 6 may also be a possibility.
>
>What algorithm do you want to implement with it? If you don't need many
>parallel calculation or hard realtime, usually a fast PC with a GPU and
>something like CUDA or OpenCL is more cost-effective, and much easier to
>program.

I think this is the best suggestion so far. Some manufacturers even
offer GPU cards without connectors for a monitor. The computational
power of a GPU is huge! It will be very hard to beat with an FPGA.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 153647
Subject: Re: Best FPGA for algorithmic acceleration
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 9 Apr 2012 21:44:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
Nico Coesel <nico@puntnl.niks> wrote:

(snip, someone wrote)
>>What algorithm do you want to implement with it? If you don't need many
>>parallel calculation or hard realtime, usually a fast PC with a GPU and
>>something like CUDA or OpenCL is more cost-effective, and much easier to
>>program.

> I think this is the best suggestion so far. Some manufacturers even
> offer GPU cards without connectors for a monitor. The computational
> power of a GPU is huge! It will be very hard to beat with an FPGA.

In some cases, it is easy to beat with an FPGA.

There are some dynamic programming algorithms that need many
eight bit add/subtract/compares. I can fit hundreds of cells, 
each with about five such operations, in a Spartan 3E. 

Multiply and divide are much harder in an FPGA, as is floating point,
but small fixed point add/subtract is easy and fast.

-- glen

Article: 153648
Subject: Re: Best FPGA for algorithmic acceleration
From: nico@puntnl.niks (Nico Coesel)
Date: Tue, 10 Apr 2012 00:17:59 GMT
Links: << >>  << T >>  << A >>
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

>Nico Coesel <nico@puntnl.niks> wrote:
>
>(snip, someone wrote)
>>>What algorithm do you want to implement with it? If you don't need many
>>>parallel calculation or hard realtime, usually a fast PC with a GPU and
>>>something like CUDA or OpenCL is more cost-effective, and much easier to
>>>program.
>
>> I think this is the best suggestion so far. Some manufacturers even
>> offer GPU cards without connectors for a monitor. The computational
>> power of a GPU is huge! It will be very hard to beat with an FPGA.
>
>In some cases, it is easy to beat with an FPGA.
>
>There are some dynamic programming algorithms that need many
>eight bit add/subtract/compares. I can fit hundreds of cells, 
>each with about five such operations, in a Spartan 3E. 

A single GPU offers about 250Gflops of computational power. Maybe you
don't need the floating point but even then it might be faster than a
Spartan 3E doing fixed point operations. And don't forget the data has
to be fetched and stored somewhere. Another piece of cake for a GPU.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 153649
Subject: FPGAs directly plugged into CPU socket
From: Jim Jones <jsjones721@gmail.com>
Date: Mon, 9 Apr 2012 17:52:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm looking to purchase an FPGA that plugs directly into motherboard
CPU sockets. I've only been able to find this DRC Accelium coprocessor
(PDF warning: http://www.drccomputer.com/pdfs/DRC_Accelium_Coprocessors.pdf),
which limits me to finding a motherboard with socket F thereby
limiting my processor options.

Does anyone know of other FPGAs which can plug into AMD motherboards
with newer sockets, like C32 or G34? I imagine they exist, and would
use HyperTransport as the one above does, but I can't find any. The
HyperTransport site lists some FPGAs which use it but the links seem
out of date (http://www.hypertransport.org/default.cfm?
page=ProductsProductsByType&ProductTypeID=6#6).

Best,
Jim



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