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Nico Coesel <nico@puntnl.niks> wrote: (snip, I wrote) >>In some cases, it is easy to beat with an FPGA. >>There are some dynamic programming algorithms that need many >>eight bit add/subtract/compares. I can fit hundreds of cells, >>each with about five such operations, in a Spartan 3E. > A single GPU offers about 250Gflops of computational power. Maybe you > don't need the floating point but even then it might be faster than a > Spartan 3E doing fixed point operations. And don't forget the data has > to be fetched and stored somewhere. Another piece of cake for a GPU. For a linear systolic array, it is pretty easy to get the data in, which goes at a fairly slow rate. Coming out depends on the actual data, and can be high or low. Also, a linear systolic array can be extended by adding more chips fairly easily. You do need to power and cool them, but otherwise it is a linear array of as many chips as you can afford. -- glenArticle: 153651
How large is your spike. If it exceeds something like 4.6V then you are exceeding the specification of the device and all sorts of strange things might happen. Which variety of Spartan-3 do you have 3, 3E or 3A? Also look at the state machine reasoning mentioned elsewhere in the post responses. Spartan-3 flip-flops etc. can respond to very narrow glitches and you cannot rely on those being ignored by the device. In this sphere some flip-flops might respond to a spike and others not so state machines can go into funny illegal states and so on. John Adair Enterpoint Ltd. - Home of free PCIe seminars and labs. On Apr 7, 8:28=A0am, "nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > hi > i 'm designing a board with fpga spartan 3(Industrial series) . while > testing the board, specially when there is spike on any input pin of fpga= , > fpga enters unknown sate and won't do its job correctly, but after reset = it > continues working. is it a common design practice to have an external > watchdog timer to reset the fpga in fpga based boards in case it is in > unknown state, like watchdog timer in microcontrollers? I thought that > fpgas are more stable than microcontroller in response to noise, but in m= y > test design I experienced the same thing similar to microcontrollers. > are gates in fpga altered due to noise?? > tnx in advanced for any comment > > --------------------------------------- > Posted throughhttp://www.FPGARelated.comArticle: 153652
On Apr 9, 11:38=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Nico Coesel <n...@puntnl.niks> wrote: > > (snip, I wrote) > > >>In some cases, it is easy to beat with an FPGA. > >>There are some dynamic programming algorithms that need many > >>eight bit add/subtract/compares. I can fit hundreds of cells, > >>each with about five such operations, in a Spartan 3E. > > A single GPU offers about 250Gflops of computational power. Maybe you > > don't need the floating point but even then it might be faster than a > > Spartan 3E doing fixed point operations. And don't forget the data has > > to be fetched and stored somewhere. Another piece of cake for a GPU. > > For a linear systolic array, it is pretty easy to get the data in, > which goes at a fairly slow rate. Coming out depends on the actual > data, and can be high or low. Also, a linear systolic array can > be extended by adding more chips fairly easily. You do need to > power and cool them, but otherwise it is a linear array of as > many chips as you can afford. > > -- glen The reduced development effort of GPU vs FPGA should not be understated. It's essentially software design vs. hardware design; this comes with all the advantages (development cycles, portability, and tightly-integrated/mature-ish tools are the big ones). Last I heard, the conventional wisdom here was that GPUs can get you 10x with a few weeks of effort for most problems. FPGAs may get you 100x for some specific problems, but at 10x the development effort (even more if you're not targeting COTS). Ultimately, they are both just means to an end, but it's usually better to let the problem dictate the solution, as opposed to the other way around.Article: 153653
Hallo guys, I'm pretty new to hardware programming. I'm currently working on a project and I have to create a communication channel between my PC and FPGA (Xilinx Virtex 5 model) through a USB port. At the end of the day, it should be able to use a matlab script to send data from PC to FPGA. For example if I send 110000 from my PC, it should light some LEDs on my FPGA. I don't know how to establish this communication channel. ANY HELP ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153654
On Tuesday, April 10, 2012 6:10:33 AM UTC-7, tabenash2002 wrote: > Hallo guys, > > I'm pretty new to hardware programming. I'm currently working on a project > and I have to create a communication channel between my PC and FPGA (Xilinx > Virtex 5 model) through a USB port. > > At the end of the day, it should be able to use a matlab script to send > data from PC to FPGA. > > For example if I send 110000 from my PC, it should light some LEDs on my > FPGA. > > I don't know how to establish this communication channel. > > ANY HELP ? > > > > --------------------------------------- > Posted through http://www.FPGARelated.com You might take a look at FTDI interface chips. They have a variety of solutions as does Cypress Semi. You don't mention how much performance you need. Is it MB/sec or KB/sec? That makes a huge difference to your approach. Also - USB2 or USB3? John PArticle: 153655
You might want to look into the HDL Verifier product which allows FGPA-in-the-Loop simulation with a variety of popular FPGA boards over Gigabit Ethernet. You can also use this product to co-simulate MATLAB and an HDL simulator such as ModelSim from Mentor Graphics. http://www.mathworks.com/products/hdl-verifier/description3.html If you really need USB, I would look at the FTDI chipsets for serial port emulation over USB. They are easy to use and readily available. Disclaimer: I work as a developer for The MathWorks. Good luck! -Brian Ogilvie ---------------------------------------- "tabenash2002" <mtnyenty@n_o_s_p_a_m.yahoo.fr> writes: Path: news.mathworks.com!newsfeed-00.mathworks.com!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail Newsgroups: comp.arch.fpga Subject: Data Transfer from PC to FPGA through USB Date: Tue, 10 Apr 2012 08:10:33 -0500 > Hallo guys, > I'm pretty new to hardware programming. I'm currently working on a project and I have to create a communication channel between my PC and FPGA (Xilinx Virtex 5 model) through a USB port. > At the end of the day, it should be able to use a matlab script to send data from PC to FPGA. > For example if I send 110000 from my PC, it should light some LEDs on my FPGA. > I don't know how to establish this communication channel. > ANY HELP ? > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153656
On Tue, 10 Apr 2012 06:37:45 -0700, johnp wrote: > On Tuesday, April 10, 2012 6:10:33 AM UTC-7, tabenash2002 wrote: >> Hallo guys, >> >> I'm pretty new to hardware programming. I'm currently working on a >> project and I have to create a communication channel between my PC and >> FPGA (Xilinx Virtex 5 model) through a USB port. >> >> At the end of the day, it should be able to use a matlab script to send >> data from PC to FPGA. >> >> For example if I send 110000 from my PC, it should light some LEDs on >> my FPGA. >> >> I don't know how to establish this communication channel. >> >> ANY HELP ? >> >> >> >> --------------------------------------- Posted through >> http://www.FPGARelated.com > > You might take a look at FTDI interface chips. They have a variety of > solutions as does Cypress Semi. > > You don't mention how much performance you need. Is it MB/sec or > KB/sec? That makes a huge difference to your approach. Also - USB2 or > USB3? > > John P FWIW, OpenCores lists a USB 1.1 and a USB 2.0 core. But the FTDI chip comes with Windows drivers, which will vastly simplify your life, if your prof will let you do it that way. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 153657
Hello, I am trying to do DPR on an Atlys board, which uses Spartan-6. It seems I c= an only solve my problem if I revert to bus macros (Partitions are only sup= ported for Virtex/Kintex and you need an additional license, differential P= R is usable if you do not use block RAMs on the Spartan-6). However, the latest references I can find on bus macros date from 2007, and= searching on Xilinx, I see that the answer there is "deprecated". Is there anybody who could show me/give me examples on bus macros? Regards, JurgenArticle: 153658
On 10.04.2012 15:10, tabenash2002 wrote: > Hallo guys, > > I'm pretty new to hardware programming. > > At the end of the day, it should be able to use a matlab script to send > data from PC to FPGA. Then make your life easy: use an usb -> parallel port adapter (like http://www.amazon.de/Parallel-Centronics-Adapter-Druckerkabel-36pol/dp/B002CP8U3U ) and connect some of the data pins to the FPGA. A simple print in matlab to the proper PRN port should be sufficient.Article: 153659
On 08.04.2012 20:47, tu wrote: >> >> http://www.bitlib.de/pub/mproz/mproz3_e.pdf >> http://www.bitlib.de/pub/mproz/mproz3.zip >> >> is an example for a simple SPARTAN-3E cpu using the internal memory >> as program memory and leds as output. >> >> > Thank you indeed, but i am unable to understand the led code and the > corresponding hardware. > could you please explain it. The board I have with me is Spartan-3E starter > kit from diligent, can i use the on board led? In the documentation of your board, you should find the pin number to which the LED is connected. Drive this pin with the output of a Flip-Flop and use the CPU to modify the content of the Flip-Flop.Article: 153660
In 2001 I bought a seat of Xilinx Foundation (before Ise). I did not renew the service contract because it was working fine, and then Ise and WebPack came out. I had to go to the post office to sign for a certified letter. In it was a check for $0.03 reimbursing me for an overcharge on state sales tax. I hate to think how much it cost them to repay this, with clerical costs, printing the check, sending out the certified mail, etc. JonArticle: 153661
On Thursday, March 8, 2012 2:42:50 PM UTC+2, tu wrote: > Hello Every body, > > I have written a code in VHDL for 8 bit simple cpu and also have the test > bench for this. > The Opcodes are also written and implemented. > I also have downloaded the bit files in Spartan-3E kit. > It glows the done led and shows the configuration successfully completed. > Now my query is how can i test this cpu? Meaning can i write a code to > check the cpu is working properly? I want to check the output in LCD or > LEDs or may be in the terminal (hyper terminal) of PC. > I have no clue on this how to do this. It will be highly appreciated if > anybody an help. > > Thank you. > > > > --------------------------------------- > Posted through http://www.FPGARelated.com Hi, Have you done any simulation to verify your design? debugging on the board will be very hard to do. MotiArticle: 153662
Giuseppe Marullo wrote:
>>
>> - I suggest you to built in the FPGA a so called "Power On Reset"
>> circuit, followed by some "Reset Bridge" (one for each clock domain).
>>
>> - As you certainly already know, when using an (internal) power on
>> reset, the external reset pin can be optional.
> Claude,
> many thanks about your answer.
>
> This is what I wrote to implement the automagic reset time:
>
> reg [3:0] rst_buffer;
>
> wire user_reset = ~rst_buffer[3]; // I need a active reset signal
>
> always @(posedge user_clock or posedge user_button)
>
> if (user_button == 1'b1) // the pushbutton is high when pressed
> rst_buffer <= 4'b0;
> else
> rst_buffer <= {rst_buffer[2:0], 1'b1};
>
> User button is positive and async, probably I also need a debouncing
> cicuit.
>
> I only have a clock domain.
>
> > - As you certainly already know, when using an (internal) power on
> > reset, the external reset pin can be optional.
>
> I am still learning things, this is for hobby. I have the pushbuton
> already on the board, so ti does make sense to avoid using another pin
> just for this.
>
> Giuseppe Marullo
If you never need to reset the FPGA after configuration, then you don't
need a reset pin. Configuration itself provides a complete
initialization of all internal registers. However, it is a good idea
to delay the startup of state machines after configuration because
the skew of the global reset net is large, and the startup clock
probably isn't synchronous to your design. So usually I do essentially
what you did but without the button:
reg [3:0] rst_buffer = 4'b1111; // Active high reset
wire user_reset = rst_buffer[3]; // still active high
always @ (posedge clk) rst_buffer <= rst_buffer << 1; // shift in 0's
Note that rst_buffer will never reassert after configuration.
In the old days before XST understood initialization in the
reg declaration, I used to use the FDP primitive to accomplish
the same circuit.
HTH,
Gabor
Article: 153663Jon Elson wrote: > In 2001 I bought a seat of Xilinx Foundation (before Ise). > I did not renew the service contract because it was working fine, > and then Ise and WebPack came out. > > I had to go to the post office to sign for a certified letter. > In it was a check for $0.03 reimbursing me for an overcharge > on state sales tax. I hate to think how much it cost them to > repay this, with clerical costs, printing the check, sending out > the certified mail, etc. > > Jon Probably less than they spent on lawyers going back and forth with Aldec about "uncounted seats." By the way, if you support any designs built with old Foundation package, hold onto it. The new ISE stuff doesn't read the old (Aldec-based) Foundation projects. -- GaborArticle: 153664
Does anybody somewhere have a backup of this document, xdl.html, which was part of ISE 6.3? Regards, JurgenArticle: 153665
Hello, You could have a look "The Xilinx Design Language (XDL): Tutorial and Use Cases" http://www.mn.uio.no/ifi/english/research/projects/cosrecos/publications/paper/recosoc11beckhoff.pdf Kind regards, On 04/11/2012 07:08 AM, chthon wrote: > Does anybody somewhere have a backup of this document, xdl.html, which was part of ISE 6.3? > > Regards, > > JurgenArticle: 153666
I'm using the standalone bsp for a ppc440 on a Virtex 5. I have a scenario where I have to read from an external chip over spi in response to a gpio interrupt. The issue I run into is that when I call XSpi_Transfer from within the context of the gpio isr, the call just hangs, presumably dues to the fact that the xspi_l portion of the driver is attempting to use interrupts to service it's fifo interface. Any ideas on how to make this work? I'm suspecting there is something I can do with interrupt priorities to make this work. I've tried calling the XGpio_InterruptClear before calling the XSpi_Transfer, but the call still hung.Article: 153667
Gabor wrote: > > Probably less than they spent on lawyers going back and forth > with Aldec about "uncounted seats." By the way, if you > support any designs built with old Foundation package, hold > onto it. The new ISE stuff doesn't read the old (Aldec-based) > Foundation projects. Oh, I am ALL too well aware of this. I have a couple designs on old 5V Spartan, but hopefully there will never be any revisions of those. I hated the Aldec schematic entry so much I crafted a way to use Protel to generate the structural VHDLm but then these files needed to be edited a bit. It was a big mistake, but I did eventually move almost everything over to "real" VHDL. I am staying with Ise 10.1 to retain compatibility with Spartan IIE chips until those migrate to something newer. JonArticle: 153668
On Apr 11, 2:27=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > Gabor wrote: > > > Probably less than they spent on lawyers going back and forth > > with Aldec about "uncounted seats." =A0By the way, if you > > support any designs built with old Foundation package, hold > > onto it. =A0The new ISE stuff doesn't read the old (Aldec-based) > > Foundation projects. > > Oh, I am ALL too well aware of this. =A0I have a couple designs on > old 5V Spartan, but hopefully there will never be any revisions > of those. =A0I hated the Aldec schematic entry so much I crafted > a way to use Protel to generate the structural VHDLm but then these > files needed to be edited a bit. =A0It was a big mistake, but I > did eventually move almost everything over to "real" VHDL. > > I am staying with Ise 10.1 to retain compatibility with Spartan IIE > chips until those migrate to something newer. > > Jon ahh.. I believe many still hold on the Fndtn series, started with 1.4 and ended up with 4.2 ...Article: 153669
On Wed, 11 Apr 2012 11:16:42 -0700, Thomas Taranowski wrote: > I'm using the standalone bsp for a ppc440 on a Virtex 5. > > I have a scenario where I have to read from an external chip over spi in > response to a gpio interrupt. The issue I run into is that when I call > XSpi_Transfer from within the context of the gpio isr, the call just > hangs, presumably dues to the fact that the xspi_l portion of the driver > is attempting to use interrupts to service it's fifo interface. Any > ideas on how to make this work? I'm suspecting there is something I can > do with interrupt priorities to make this work. I've tried calling the > XGpio_InterruptClear before calling the XSpi_Transfer, but the call > still hung. This would be a much better question for comp.arch.embedded, particularly if you could talk about it in terms that don't rely on a detailed knowledge of that particular BSP. The best way to do this is to have an environment in place that allows you to respond to events in real time without using interrupt contexts as a poor-man's RTOS. Then, you can set a semaphore or event or flag or whatever you want to call it in response to the GPIO event, and have the SPI code pend on that semaphore. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 153670
>On Thursday, March 8, 2012 2:42:50 PM UTC+2, tu wrote: >> Hello Every body, >> >> I have written a code in VHDL for 8 bit simple cpu and also have the test >> bench for this. >> The Opcodes are also written and implemented. >> I also have downloaded the bit files in Spartan-3E kit. >> It glows the done led and shows the configuration successfully completed. >> Now my query is how can i test this cpu? Meaning can i write a code to >> check the cpu is working properly? I want to check the output in LCD or >> LEDs or may be in the terminal (hyper terminal) of PC. >> I have no clue on this how to do this. It will be highly appreciated if >> anybody an help. >> >> Thank you. >> >> >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > >Hi, >Have you done any simulation to verify your design? debugging on the board will be very hard to do. >Moti================================== yes i have done the simulation through a test bench, and getting perfect behavioral simulation. My code is simple it adds two integer and stores the result in memory. In the simulation, I have checked the memory and its right. Can i check it on Spartan-3E starter kit through led, lcd or the hyperterminal of pc --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153671
Mawa_fugo wrote: > On Apr 11, 2:27 pm, Jon Elson <jmel...@wustl.edu> wrote: >> Gabor wrote: >> >> > Probably less than they spent on lawyers going back and forth >> > with Aldec about "uncounted seats." By the way, if you >> > support any designs built with old Foundation package, hold >> > onto it. The new ISE stuff doesn't read the old (Aldec-based) >> > Foundation projects. >> >> Oh, I am ALL too well aware of this. I have a couple designs on >> old 5V Spartan, but hopefully there will never be any revisions >> of those. I hated the Aldec schematic entry so much I crafted >> a way to use Protel to generate the structural VHDLm but then these >> files needed to be edited a bit. It was a big mistake, but I >> did eventually move almost everything over to "real" VHDL. >> >> I am staying with Ise 10.1 to retain compatibility with Spartan IIE >> chips until those migrate to something newer. >> >> Jon > > ahh.. I believe many still hold on the Fndtn series, started with 1.4 > and ended up with 4.2 ... I've still got the CDs for 3.1, and 4.2, and maybe some others. Currently, I only have Ise loaded, and hope not to need to go back to those older packages. JonArticle: 153672
jurgenwrote: > Does anybody somewhere have a backup of this document, xdl.html, which was part of ISE 6.3? Did you try the archived WebPACK version of 6.3? http://www.xilinx.com/webpack/classics/wpclassic/ I don't have the WebPack version of 6.3 installed here to check, but in the regular ISE 6.3 release the xdl docs can be found in %XILINX%\help\data\xdl BrianArticle: 153673
hi, after few years i want to restart FPGA development once again - initially f= or personel fun, but later may move in to commercial development too. At th= e moment i am trying to find a suitable processor core for the work. These = are my requirements: 1. It must have a good documentation + tools + community support 2. It should be mature and future proof 3. Better if it is Free, how ever commercial cores are OK too provided that= i have the full documentation + tool set for free to get started. Few years back i played a little with openrisc. This time too i initially w= anted to go with it. However documentation for openrisc seems to be extreme= ly low and incomplete. Im not sure the status of tools and support, but see= ms like they are lacking as well. I'd like to get some advice from expert e= ngineers about this before going forward. Also like to know about better al= ternatives as well. thank youArticle: 153674
manusha1980@gmail.com wrote: > after few years i want to restart FPGA development once again - initially for personel fun, but later may move in to commercial development too. At the moment i am trying to find a suitable processor core for the work. These are my requirements: > > 1. It must have a good documentation + tools + community support > 2. It should be mature and future proof > 3. Better if it is Free, how ever commercial cores are OK too provided that i have the full documentation + tool set for free to get started. > > > Few years back i played a little with openrisc. This time too i initially wanted to go with it. However documentation for openrisc seems to be extremely low and incomplete. Im not sure the status of tools and support, but seems like they are lacking as well. I'd like to get some advice from expert engineers about this before going forward. Also like to know about better alternatives as well. How fast do you need it? I've used NIOS, the smallest version is free. Sometimes a bit difficult to setup a project and to use Eclipse, but when it works, it is nice, with integrated debugger. -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbuss
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Compare FPGA features and resources
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