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On Mar 6, 2:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote: > Is there a way to look at a uniform cost model which combines all of the= n? No. - A BRAM can be used ot implement a 7x7 multiplyer, but a multiplier can't be used to implement a RAM. - A BRAM can replace 1024 4-LUTs that are used as RAM or ROM, if they are part of one address range. If the addresses are independent it can only replace 1 LUT in the RAM case or 3 LUTs in the ROM case. - A 18x18 multiplier can replace 18 LUTs used as adders or 54 LUTs used as barrel shifters, but it will take 324 LUTs to replace the multiplier So, depending on application the conversion factors differ by three orders of magnitude and conversion is not possible at all in some cases. You really have to treat these as seperate ressources. There is some simplification possible: The ration of LUTs to DFFs is very much in favor of the DFFs in most FPGA architectures to simplify placement. It is very uncommon to run out of DFFs in an FPGA that has enough LUTs for your design (if you are not called Ray Andraka) so you could simply ignore DFF count in the comparison. Also: Multiplers tend to be either the limiting factor or not used at all. KoljaArticle: 153476
>Is there ... a uniform cost model which combines all of them? No, and only a Pointy-Haired Boss would think that as simplistic a metric as that was a useful measure. As other posters have suggested, for a given target FPGA, the percentage utilisation figures are useful, and if pushed by management for a single figure I would give the worst of FFs/LUTs/BRAMs/DSPs/whatever-else-is-relevant. If this is for an academic thesis, then it doesn't matter much what you put, because no-one in industry will read it... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153477
Hi =20 We are doing initial testing of a new Virtex-6 based board that we develope= d. We are having problems when trying to access the system monitor informat= ion over JTAG. It is constantly showing a die temperature of -29 degrees, a= nd incorrect voltages for VCCINT, VCCAUX and the VREFP pin on the System Mo= nitor itself. We've verified that the correct voltages are present on all i= nputs on the BGA. =20 We've successfully configured the device over the JTAG chain, thus we don't= think the problem is over there. We get the wrong values before and after = configuration (they stay constant all the time). =20 I've checked the way the connections to the device have been done many time= s, and can't find anything wrong with it. I also asked this question on the= Xilinx community forums and I've uploaded the relevant part of the schemat= ics over there: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-6-Sy= stem-Monitor-sensor-readings-in-ChipScope-gives-weird/td-p/217561 =20 Any ideas on where to look next for things that can go wrong will be much a= ppreciated. =20 Thanks, JacoArticle: 153478
Your solution is posted over at the Xilinx forum: The VREFP is connected to 2.5V, the same as AVDD. However, the reference voltage is 1.25V for V6 (and 7series). If you do not have access to a 1.25V reference on the PCB, you can tie VREFP to AVSS, and an internal reference will be used. The accuracy of measured values when using the internal reference is less accurate. I believe this is ~1% error. The user guide and data-sheet will have the accuracy numbers for both internal and external reference modes. On 3/7/2012 5:48 AM, Jaco Naude wrote: > Hi > > We are doing initial testing of a new Virtex-6 based board that we developed. We are having problems when trying to access the system monitor information over JTAG. It is constantly showing a die temperature of -29 degrees, and incorrect voltages for VCCINT, VCCAUX and the VREFP pin on the System Monitor itself. We've verified that the correct voltages are present on all inputs on the BGA. > > We've successfully configured the device over the JTAG chain, thus we don't think the problem is over there. We get the wrong values before and after configuration (they stay constant all the time). > > I've checked the way the connections to the device have been done many times, and can't find anything wrong with it. I also asked this question on the Xilinx community forums and I've uploaded the relevant part of the schematics over there: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-6-System-Monitor-sensor-readings-in-ChipScope-gives-weird/td-p/217561 > > Any ideas on where to look next for things that can go wrong will be much appreciated. > > Thanks, > JacoArticle: 153479
Hi in a project I am using a Virtex-6 with GTX RocketIO transceivers which I want to interface with a 4x 6.5 Gb/s interface on the RX side. One project contraint is not to use any channel coding, i.e. only 8B data. So I have 4x 6.5Gb/s that I have to synchronize on the RX path. That gives me two major challanges: a) Somehow achieve a clock recovery b) Synchronize the incoming data Due to the fact that I am not allowed to use a specific channel coding, I cannot get the clock signal extracted from my data. So my idea is to use one additional channel to send a 1-0-pattern to get a clock reference for the whole interface. Use this as RXRECCLK (RX recovered clock) to clock the other RocketIOs. Is this possible? If so, done! Then use a training pattern on the other channels to be able to shift and deskew the data (given that the skew does not change over time). Thereafter transmit the data over the 4 parallel channels. So what do you think of this concept? Is it feasible? Any other suggestions? Thanks, BertiArticle: 153480
Hello Every body, I have written a code in VHDL for 8 bit simple cpu and also have the test bench for this. The Opcodes are also written and implemented. I also have downloaded the bit files in Spartan-3E kit. It glows the done led and shows the configuration successfully completed. Now my query is how can i test this cpu? Meaning can i write a code to check the cpu is working properly? I want to check the output in LCD or LEDs or may be in the terminal (hyper terminal) of PC. I have no clue on this how to do this. It will be highly appreciated if anybody an help. Thank you. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153481
On Mar 8, 8:42=A0pm, "tu" <tu_ind@n_o_s_p_a_m.yahoo.co.in> wrote: > Hello Every body, > > I have written a code in VHDL for 8 bit simple cpu and also have the test > bench for this. > The Opcodes are also written and implemented. > I also have downloaded the bit files in Spartan-3E kit. > It glows the done led and shows the configuration successfully completed. > Now my query is how can i test this cpu? Meaning can i write a code to > check the cpu is working properly? I want to check the output in LCD or > LEDs or may be in the terminal (hyper terminal) of PC. > I have no clue on this how to do this. It will be highly appreciated if > anybody an help. > > Thank you. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com for a case of using normal cpu, there are some programming pins on that cpu to allow your cpu programmer to load the software into the cpu. in this case where you make a cpu out of fpga, you could assign some fpga pins as cpu programming pins, and let your cpu programmer "talk" to the cpu thru those pins.Article: 153482
On Mar 5, 6:16=A0pm, "majsta" <imajstorovic@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > My design worked for about 3 hours and now gives me this error. I just > can't understand what is wrong with it now. I didn't do anything wrong. > > !Error: JTAG chain problem detected > !Error: The TDI connection to the first detected device EP2C8 might be > shorted to VCC or is an open circuit > !Error: The TCK and TMS connections to the device before the first detect= ed > device EP2C8 might have a problem > !Info: Detected 1 device(s) > !Info: Device 1: EP2C8 > > device is EP2C8Q208C8 > > TDI pulled high with 10Kohm resistor also TMS > TCK pulled down with same resistor value > Pin 2 on JTAG header connected to GND > Pins 4 and 6 connected to VCC 3.3V > Pin 10 connected to GND > TDO connected directly to cyclone II > MSEL 0 and 1 to GND > nCE to GND > also on board is used EPCS4SI8 but I disconnect that one but problem > remains. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com sometimes altera jtag programmer is easily affected by some signal integrity issues on the jtag chain for some reason i don't know. try turning off the board and disconnect the jtag programmer (whatever blaster) from the computer and then u power on the board and connect the blaster to cpu and try again.Article: 153483
On Mar 4, 5:20=A0pm, Anssi Saari <a...@sci.fi> wrote: > John Larkin <jlar...@highlandtechnology.com> writes: > > What Altera file format should I use to burn the serial flash chip? > > RBF? RPD? Should I tell the programmer to swap ends on bytes or words? > > My experience on the last part is, you may just have to experiment to > find out. We used a 16-bit parallel flash in byte mode once and had a > CPLD read the flash in byte mode and push the data to the FPGA (Virtex 4 > from Xilinx). > > The problem was, there was just no information on the flash data sheet > about the byte order in byte mode. So we experimented and figured out > which way the data should be in the flash, writing the flash with the on > board software at that point. And of course when we wanted to write the > flash with a programmer, things were the opposite of the software > situation... Byte swap was explicitly done in software, but somehow the > flash programmer needed byte swap off to create the same flash contents. usually the rbf and rpd are used when you want to save the fpga image elsewhere (eg. in flash device attached to processor. processor reads the image from flash and configures the fpga). in your case the serial flash is attached directly to the fpga so the fpga should be set to active serial configuration (on boot up, fpga will read the flash and configures itself). thus, you can generate a POF for active serial and use your usb flash burner to write the POF into the flash. there is another alternative to write into the flash which is indirect jtag programming where you can write the flash using jtag programmer. btw, you don't really need to byte swap for altera's fpga.Article: 153484
On Feb 22, 5:43=A0am, Michael <michael_laaja...@yahoo.com> wrote: > Hi, > > How do I setup synopsys_sim.setup for simulating both Verilog and VHDL > using VCS for a Xilinx FPGA? > > I need for instance have SIMPRIM point to both the VHDL and the Verilog > compiled library path, I did try using a : and simply append them but it > failed. > > /michael have you tried using "vlog" to compile verilog codes and "vcom" to compile VHDL codes?Article: 153485
Hi: I spent the last two weeks at Xilinx in San Jose taking Doulos' "Comprehensive Verilog" and the "Essentials and Design for Performance" courses. Very enlightening. I was very impressed by the facility. Makes my workplace look a bit dumpy :-( But I do have lots of oscilloscopes and cool toys :-) Particularly cool were the badges and doors. Just stick the badge near the reader and you can get in where you belong. At my work (surprising as it is for a gov. lab) we have 4 generations of incompatible locks with no centrally networked control, with key pads, swipes where you have to stick in your badge from underneath, and they are half broken all the time. Yes I know it's kind of silly to be focusing on the door locks after such an experience. I am highly obsessed to start designing new circuits with my FPGAs now! I'm also overjoyed that the Linux tool-chain works so well. I can even program my Digilent boards in 5 seconds at the CLI rather than spending many minutes wading through Impact dialogs. The instructor was very competent and fun to interact with. The people in the classes were very nice and professional. Just as I was hoping, a great deal of concepts relating to how to use Verilog and the tools to design properly--concepts that are difficult to get from language ref. books, and cookbook example books--were solidly conveyed through this training. A great experience! I feel now that, while I don't know deeply how to do everything, I know about it all in such a way that I can build up my experience much more efficiently now on my own. Most importantly, I think many blind spots have been eliminated. The instructor tried to persuade me to consider switching my current design to Kintex-7 or Artix-7 vs. the Spartan 3E that I was targeting. Now that I see Spartan 3 series are at the bottom of the Xilinx product offerings list, I have at least decided that I will consider moving to Spartan 6. So I bought some new dev. boards for Spartan 6. But 7 series devices are either 30 times more expensive or unobtanium. Considering that I usually use single digit percentages of the resources of my PLDs, I think I'll be fine with Spartan 6. I hope that some of the folks who took the courses will find their way to this group and begin to participate. I let them know about comp.arch.fpga. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 153486
I am struggling to find a solution to my problem: I would like to get a (very) rough idea of the relative levels of power consumption used by equivelent devices from Altera's Cyclone III and IV ranges and Lattice's ECP3 and XP2 ranges. Implementing the same design on each of those devices (say the 16-17k logic element size) how big a difference in power consumption will there be between each of those FPGA ranges? I'm not looking for you to necessarily give me the answer but maybe point me in the right direction.Article: 153487
Berti Schueler wrote: > Hi > > in a project I am using a Virtex-6 with GTX RocketIO transceivers which I > want to interface with a 4x 6.5 Gb/s interface on the RX side. One project > contraint is not to use any channel coding, i.e. only 8B data. So I have 4x > 6.5Gb/s that I have to synchronize on the RX path. That gives me two major > challanges: > > a) Somehow achieve a clock recovery > b) Synchronize the incoming data > > Due to the fact that I am not allowed to use a specific channel coding, I > cannot get the clock signal extracted from my data. So my idea is to use one > additional channel to send a 1-0-pattern to get a clock reference for the > whole interface. Use this as RXRECCLK (RX recovered clock) to clock the > other RocketIOs. Is this possible? If so, done! Then use a training pattern > on the other channels to be able to shift and deskew the data (given that > the skew does not change over time). Thereafter transmit the data over the 4 > parallel channels. > > So what do you think of this concept? Is it feasible? Any other suggestions? > > Thanks, > Berti > > Your solution sounds remarkably like Channel-Link, and it's not likely to work at 6.5 Gbps. The problem (even if it were possible to wire the bit clocks together inside the V6) is that you're looking at a daunting task to match the prop delays between data and clock channels. You have a much better chance of success using 8B-10B encoding and increasing the clock rate to allow the required throughput. Is the Rx side also implemented in V6? -- GaborArticle: 153488
On 08.03.2012 13:42, tu wrote: > Hello Every body, > > I have written a code in VHDL for 8 bit simple cpu and also have the test > bench for this. > The Opcodes are also written and implemented. > I also have downloaded the bit files in Spartan-3E kit. > It glows the done led and shows the configuration successfully completed. > Now my query is how can i test this cpu? Meaning can i write a code to > check the cpu is working properly? I want to check the output in LCD or > LEDs or may be in the terminal (hyper terminal) of PC. > I have no clue on this how to do this. It will be highly appreciated if > anybody an help. http://www.bitlib.de/pub/mproz/mproz3_e.pdf http://www.bitlib.de/pub/mproz/mproz3.zip is an example for a simple SPARTAN-3E cpu using the internal memory as program memory and leds as output.Article: 153489
>Hi, > >I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen >is supposed to work but the LTM manual does not mention it. Are there >others? A seven inch screen is preferred. > >Thanks, >Gary > > Hi , There is another that is LTP - 8 "LCD / Touch in the System Builder in options GPIO-0 comes. Only be a matter of searching with Terasic. Best Regards Robert --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153490
Ok thank you, but here is some info after investigation. Two reasons first one is regarding to pin 6 on JTAG and for ByteBlaster it needs VCC connection but in USB blaster stays NC. Second one may be with AnalogGND and DigitalGND problems on the board, and after solving those two things problem is gone :) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153491
On Feb 15, 10:50=A0am, wzab <wza...@gmail.com> wrote: > I have found an SVF based solution: > > http://www.clifford.at/libxsvf/ > > but again there is no info if it is 64-bit safe... > -- > Regards, > WZab I've successfully tested libsxvf on both 32-bit and 64-bit platforms. I had to write my own "backends" matching my programming hardware (one was based on CAEN VME interface, and another one on FTDI USB bridge connected to our own JTAG "accelerator"). The only problem was to write those backends in platform independent form. Oh, well, additional problem was with Altera Quartus generated SVF file. The "FREQUENCY 10000000.00 HZ;" causes the SVF syntax error message, so it must be commented out before the SVF file is used by the libxsvf. -- Regards, WZabArticle: 153492
Hi, Pleased to introduce my new tool, VTM 2012. It is intended to be a table based edit tool for Verilog/VHDL module's interface definition, and unify the process of HDL coding and document writing. A demo is at http://www.veriloghdl.org/demo.html These tools enable you to build the design's framework, both top down and bottom up styles. I want to design the HDL in even higher level. I would like to get some ideas on how people think it before VTM's completeness. I am now considering to add system verilog interface feature to it. But I see very few people using system verilog feature like interface in their RTL designs. Do you think it a valuable feature? Any comment is welcome. ThanksArticle: 153493
Hello, I have an internal BUS for all the registers in different modules. I found it is inconvenient to build a MUX for the read BUS, instead I want to just OR all the buses together (output 0 when deselected). The design is for Spartan-3A FPGA, does anyone know whether there's any difference on resource usage or performance? Best Regards, HaiwenArticle: 153494
On Thu, 8 Mar 2012 07:46:12 -0800 (PST), Jack Leong <jacksw.leong@gmail.com> wrote: >On Mar 4, 5:20 pm, Anssi Saari <a...@sci.fi> wrote: >> John Larkin <jlar...@highlandtechnology.com> writes: >> > What Altera file format should I use to burn the serial flash chip? >> > RBF? RPD? Should I tell the programmer to swap ends on bytes or words? >> >> My experience on the last part is, you may just have to experiment to >> find out. We used a 16-bit parallel flash in byte mode once and had a >> CPLD read the flash in byte mode and push the data to the FPGA (Virtex 4 >> from Xilinx). >> >> The problem was, there was just no information on the flash data sheet >> about the byte order in byte mode. So we experimented and figured out >> which way the data should be in the flash, writing the flash with the on >> board software at that point. And of course when we wanted to write the >> flash with a programmer, things were the opposite of the software >> situation... Byte swap was explicitly done in software, but somehow the >> flash programmer needed byte swap off to create the same flash contents. > >usually the rbf and rpd are used when you want to save the fpga image >elsewhere (eg. in flash device attached to processor. processor reads >the image from flash and configures the fpga). in your case the serial >flash is attached directly to the fpga so the fpga should be set to >active serial configuration (on boot up, fpga will read the flash and >configures itself). thus, you can generate a POF for active serial and >use your usb flash burner to write the POF into the flash. > >there is another alternative to write into the flash which is indirect >jtag programming where you can write the flash using jtag programmer. > >btw, you don't really need to byte swap for altera's fpga. I had to *bit swap* the .RBF file to get it to work. -- John Larkin, President Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generatorsArticle: 153495
Haiwen <heavenfish@gmail.com> wrote: > I have an internal BUS for all the registers in different modules. I > found it is inconvenient to build a MUX for the read BUS, instead I > want to just OR all the buses together (output 0 when deselected). > The design is for Spartan-3A FPGA, does anyone know whether there's > any difference on resource usage or performance? As far as I know, if you write internal tristate logic, it generates something similar to the OR logic you mention. If you have enable lines, like for tristate gates, then the OR logic should be most efficient. If you have an encoded binary address, like for a mux select input, then the mux is probably better. Also, the enable/OR works better if the enable signals come from widely spaced modules. -- glenArticle: 153496
On Mar 13, 1:06=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Haiwen <heavenf...@gmail.com> wrote: > > I have an internal BUS for all the registers in different modules. I > > found it is inconvenient to build a MUX for the read BUS, instead I > > want to just OR all the buses together (output 0 when deselected). > > The design is for Spartan-3A FPGA, does anyone know whether there's > > any difference on resource usage or performance? > > As far as I know, if you write internal tristate logic, it generates > something similar to the OR logic you mention. > > If you have enable lines, like for tristate gates, then the OR > logic should be most efficient. If you have an encoded binary > address, like for a mux select input, then the mux is probably > better. > > Also, the enable/OR works better if the enable signals come from > widely spaced modules. > > -- glen Thanks, Glen. The design was using tristate gates and let the synthesizer to optimize it. I want the bus be 0 when it is floating (none is selected), but it seems the Synthesizer can't assure it all the time. So I decide to change it to OR-gates. HaiwenArticle: 153497
On Tuesday, March 13, 2012 3:32:28 AM UTC+1, Haiwen wrote: > Hello, > > I have an internal BUS for all the registers in different modules. I > found it is inconvenient to build a MUX for the read BUS, instead I > want to just OR all the buses together (output 0 when deselected). > > The design is for Spartan-3A FPGA, does anyone know whether there's > any difference on resource usage or performance? > > > Best Regards, > Haiwen If you have many bus terminals you can use the carry logic to do a fast wide OR. AndreasArticle: 153498
(snip, I wrote) >> As far as I know, if you write internal tristate logic, it generates >> something similar to the OR logic you mention. Haiwen <heavenfish@gmail.com> wrote: > Thanks, Glen. The design was using tristate gates and let the > synthesizer to optimize it. I want the bus be 0 when it is floating > (none is selected), but it seems the Synthesizer can't assure it all > the time. So I decide to change it to OR-gates. With tristate gates, you normally wouldn't be assured of that. The synthesizer could do it with either OR or AND logic. As they like to move around inverters, you probably can't count on one or the other, even for mutliple lines on the same bus. If you put weak pull-ups on the lines, though, and the synthesizer knows what to do with them, then it should generate OR. -- glenArticle: 153499
Haiwen Tristate muxes used to a good method in FPGAs prior to Spartan-3/3E/3A because the resource existed. The internal tristates don't exist in Spartan-3 and later so a synthesiser will attempt to convert to a logic function anyway. It might not always get that right as you physically can't do the tristate. Because of these uncertainies you might get a bigger, slower, mux this way. A logic mux is the way that OPB/PLB buses have worked and those worked by anding '1' when enabled with a given mux input. The speed and size of the mux will depend on the number of inputs and the data width. For speed you can often pipeline this sort of mux with registers and get a clocking speed increase at the penalty of extra latency. John Adair Enterpoint Ltd. - Home of Drigmorn2. The Spartan-3A Development Board. On Mar 13, 2:32=A0am, Haiwen <heavenf...@gmail.com> wrote: > Hello, > > I have an internal BUS for all the registers in different modules. I > found it is inconvenient to build a MUX for the read BUS, instead I > want to just OR all the buses together (output 0 when deselected). > > The design is for Spartan-3A FPGA, does anyone know whether there's > any difference on resource usage or performance? > > Best Regards, > Haiwen
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