Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message > tnx for your comment, so what should i do? i have tested the following > code > too, but still i have error in receiving packets. > assign RTL_TXE=RTL_RXDV; > assign RTL_TXD=RTL_RXD; If your receiver gives you a clock, put that on a global clock, work with the data in this domain and also feed the transmitter with it. Be careful with timing. I would need your schematic diagram to tell more. > tnx in advanced for help :) > Neda Baheri NPArticle: 153426
I am looking for a chip with somekind of communication port inbuilt. I am slowly planning a system where some data is sent from a computer to be processed in the chip. Processing data is probably easy, but I prefer not to make a serial port my self and an ethernet port is too much. But an Ethernet port would be very nice to have. I would like to have a reasonably priced chip with low cost evaluation board. And I need as many outputs I can get. Some time ago I was told here about LCMXO2-1200ZE-B-EVN and others. It is a good kit/chip but it doesn't have serial port logic built in.Article: 153427
On Wed, 22 Feb 2012 08:46:04 -0800, LM wrote: > I am looking for a chip with somekind of communication port inbuilt. I > am slowly planning a system where some data is sent from a computer to > be processed in the chip. > > Processing data is probably easy, but I prefer not to make a serial port > my self and an ethernet port is too much. But an Ethernet port would be > very nice to have. > > I would like to have a reasonably priced chip with low cost evaluation > board. And I need as many outputs I can get. Some time ago I was told > here about LCMXO2-1200ZE-B-EVN and others. It is a good kit/chip but it > doesn't have serial port logic built in. Asynchronous serial ports are dead easy if you use a fixed baud rate. They're so easy, in fact, that I can implement them successfully the first time!! Here's some Verilog code that implements a basic NAAUART (Not At All Universal Asynchronous Receiver Transmitter). I last worked with it in 2004, and you're not paying a cent for it -- so don't expect much in the way of support. About all I can remember of it is that (a) it worked, (b), the clock rate was 25MHz, and (c) my favorite serial port setup is 115200, n, 1, so that's probably what this is. And -- I'm not an FPGA designer: I just play one on TV. So if anyone wants to critique it, don't think I'm going to be offended. https://docs.google.com/open? id=0B5lSHlBBxGvjY2JmODk1MDEtMGYyYy00MzNiLWE0MjUtMWU3YThjZDM1MTU1 -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 153428
>I am looking for a chip with somekind of communication port inbuilt. I >am slowly planning a system where some data is sent from a computer to >be processed in the chip. > >Processing data is probably easy, but I prefer not to make a serial >port my self and an ethernet port is too much. But an Ethernet port >would be very nice to have. > >I would like to have a reasonably priced chip with low cost evaluation >board. And I need as many outputs I can get. Some time ago I was told >here about LCMXO2-1200ZE-B-EVN and others. It is a good kit/chip but >it doesn't have serial port logic built in. > The Xilinx Spartan 6 has an in-built Ethernet MAC block, and there are various development boards available: http://www.xilinx.com/products/boards/s6conn/reference_designs.htm I have never used the Spartan 6, but have used the Ethernet MAC in a Virtex 5. There are many examples of serial port code on the Interwebs. The search keyword is UART. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153429
On 23 Feb., 10:26, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > The Xilinx Spartan 6 has an in-built Ethernet MAC block, and there are > various development boards available:http://www.xilinx.com/products/boards/s6conn/reference_designs.htm > Are you sure that you do not mix this up with the built-in PCIe- endpoint? I think for Ethernet you need a soft IP-core? ThomasArticle: 153430
>On 23 Feb., 10:26, "RCIngham" ><robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >> The Xilinx Spartan 6 has an in-built Ethernet MAC block, and there are >> various development boards available:http://www.xilinx.com/products/boards/s6conn/reference_designs.htm >> > >Are you sure that you do not mix this up with the built-in PCIe- >endpoint? I think for Ethernet you need a soft IP-core? > >Thomas > Opps! Good spot - but I did say that I hadn't used Spartan 6. The transceiver I/O are compatible with Gigabit Ethernet, however. Maybe PCIe will suit the OP better than Ethernet if (s)he can't afford the soft-core license. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153431
> Asynchronous serial ports are dead easy if you use a fixed baud rate. > > They're so easy, in fact, that I can implement them successfully the > first time!! > > https://docs.google.com/open? > id=0B5lSHlBBxGvjY2JmODk1MDEtMGYyYy00MzNiLWE0MjUtMWU3YThjZDM1MTU1 > Heh. This will help of course. Thanks. Serial port is a bit slow. Ethetnet port would be more flexible. Wlan, switches and so on. >Maybe PCIe will suit the OP better than Ethernet if (s)he can't afford the >soft-core license. What I know of PCIe it is only local, inside the computer. I planned to my device to be a separate box. Any license payment at this stage is too much. This is a bit of a hobby now and the millions of euros come later. Thank you for answers so far LeifArticle: 153432
On Thu, 23 Feb 2012 08:27:35 -0800 (PST) LM <sala.nimi@mail.com> wrote: > > Asynchronous serial ports are dead easy if you use a fixed baud rate. > > > > They're so easy, in fact, that I can implement them successfully the > > first time!! > > > > https://docs.google.com/open? > > id=0B5lSHlBBxGvjY2JmODk1MDEtMGYyYy00MzNiLWE0MjUtMWU3YThjZDM1MTU1 > > > Heh. This will help of course. Thanks. > > Serial port is a bit slow. Ethetnet port would be more flexible. Wlan, > switches and so on. > > >Maybe PCIe will suit the OP better than Ethernet if (s)he can't afford the > >soft-core license. > What I know of PCIe it is only local, inside the computer. I planned > to my device to be a separate box. Any license payment at this stage > is too much. This is a bit of a hobby now and the millions of euros > come later. > > Thank you for answers so far > Leif Do you actually need an FPGA, or could a fast enough general purpose microprocessor cover your needs? You can really get a lot of horsepower for pennies these days in a micro, and it comes with peripherals for Ethernet/UARTS/whathaveyou already built in. A lot of my designs use an FPGA together with an off-the-shelf micro, exactly so as not not have to worry about implementing things like Ethernet MACs in the FPGA. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 153433
On Thu, 23 Feb 2012 09:17:21 -0800, Rob Gaddi wrote: > On Thu, 23 Feb 2012 08:27:35 -0800 (PST) LM <sala.nimi@mail.com> wrote: > >> > Asynchronous serial ports are dead easy if you use a fixed baud rate. >> > >> > They're so easy, in fact, that I can implement them successfully the >> > first time!! >> > >> > https://docs.google.com/open? >> > id=0B5lSHlBBxGvjY2JmODk1MDEtMGYyYy00MzNiLWE0MjUtMWU3YThjZDM1MTU1 >> > >> Heh. This will help of course. Thanks. >> >> Serial port is a bit slow. Ethetnet port would be more flexible. Wlan, >> switches and so on. >> >> >Maybe PCIe will suit the OP better than Ethernet if (s)he can't afford >> >the soft-core license. >> What I know of PCIe it is only local, inside the computer. I planned to >> my device to be a separate box. Any license payment at this stage is >> too much. This is a bit of a hobby now and the millions of euros come >> later. >> >> Thank you for answers so far >> Leif > > Do you actually need an FPGA, or could a fast enough general purpose > microprocessor cover your needs? You can really get a lot of horsepower > for pennies these days in a micro, and it comes with peripherals for > Ethernet/UARTS/whathaveyou already built in. > > A lot of my designs use an FPGA together with an off-the-shelf micro, > exactly so as not not have to worry about implementing things like > Ethernet MACs in the FPGA. -- and, unless your Ethernet messaging is really low-level, boneheaded, and simplified, you're going to need a microprocessor to manage it anyway (no _way_ do you want to try to make an all-logic TCP/IP stack!). So you may as well get a micro that has on-board Ethernet (and serial, to boot). Why didn't I think of that? -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 153434
On Thu, 23 Feb 2012 08:27:35 -0800, LM wrote: >> Asynchronous serial ports are dead easy if you use a fixed baud rate. >> >> They're so easy, in fact, that I can implement them successfully the >> first time!! >> >> https://docs.google.com/open? >> id=0B5lSHlBBxGvjY2JmODk1MDEtMGYyYy00MzNiLWE0MjUtMWU3YThjZDM1MTU1 >> > Heh. This will help of course. Thanks. > > Serial port is a bit slow. Ethetnet port would be more flexible. Wlan, > switches and so on. > >>Maybe PCIe will suit the OP better than Ethernet if (s)he can't afford >>the soft-core license. > What I know of PCIe it is only local, inside the computer. I planned to > my device to be a separate box. Any license payment at this stage is too > much. This is a bit of a hobby now and the millions of euros come later. I recall reading an article on using ATA ports as real-time I/O. So if your box is close to, and dependent on, a computer, using a SATA port may be easy. But it sounds so perverse that I suspect that the times when it is the best solution are few. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 153435
A lot depends on your concept of low cost and what you actually need. The LCMXO2 PLD is a relatively limited device and has it's slot in the CPLD and FPGA line up. Our Pomaddie3 (http://www.enterpoint.co.uk/polmaddie/polmaddie3.html) board is based on Spartan-3 but it's a nice balance of cost / performance / I/O. That gets you 60 I/O with a simple USB serial port based on a FTDI FT232. Our Drigmorn3 (http://www.enterpoint.co.uk/drigmorn/drigmorn3.html) is a possibility. If you have more money a PCIe card like our (Raggedstone2 http://www.enterpoint.co.uk/raggedstone/raggedstone2.html) gets you much more performance still with I/O. We have some modules that will compliment Drigmorn and Raggedstone boards and other ranges. On Ethernet we have a 10/100 Phy and 10/100 SPI controller solutions already available. A 10/100/1000 Phy solution also coming soon as a module. It's on our testbech now. If you prefer USB we have a FT4232 solution coming as well as a nice easy reasonable performance interface. John Adair Enterpoint Ltd. On Feb 22, 4:46=A0pm, LM <sala.n...@mail.com> wrote: > I am looking for a chip with somekind of communication port inbuilt. I > am slowly planning a system where some data is sent from a computer to > be processed in the chip. > > Processing data is probably easy, but I prefer not to make a serial > port my self and an ethernet port is too much. But an Ethernet port > would be very nice to have. > > I would like to have a reasonably priced chip with low cost evaluation > board. And I need as many outputs I can get. Some time ago I was told > here about LCMXO2-1200ZE-B-EVN and others. It is a good kit/chip but > it doesn't have serial port logic built in.Article: 153436
Tim Wescott <tim@seemywebsite.com> wrote: (snip) > -- and, unless your Ethernet messaging is really low-level, boneheaded, > and simplified, you're going to need a microprocessor to manage it anyway > (no _way_ do you want to try to make an all-logic TCP/IP stack!). So you > may as well get a micro that has on-board Ethernet (and serial, to boot). You might be able to do UDP/IP, though. TCP is enough harder that I would have to agree. That processor could be fairly simple, and implemented in an FPGA. > Why didn't I think of that? -- glenArticle: 153437
On 24 helmi, 10:58, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Tim Wescott <t...@seemywebsite.com> wrote: > > (snip) > > > -- and, unless your Ethernet messaging is really low-level, boneheaded, > > and simplified, you're going to need a microprocessor to manage it anyw= ay > > (no _way_ do you want to try to make an all-logic TCP/IP stack!). =A0So= you > > may as well get a micro that has on-board Ethernet (and serial, to boot= ). > > You might be able to do UDP/IP, though. TCP is enough harder that > I would have to agree. That processor could be fairly simple, and > implemented in an FPGA. > > > Why didn't I think of that? > > -- glen Some microprocessors have Ethernet in them. And Ethernet is certainly easier to use with a microprocessor. But then, I plan drive each pin separately in a loop, and that is easier in VHDL. It is faster too. I may end up using a FTDI chip or some similar serial to Ethernet chip here with the FPGA chip. I can say that my Ethernet messaging is really simple, but then, that can be handled with an Ethernet to serial chip too. When I studied VHDL, I heard that all larger devices have built in or optional logic block of common functions like Ethernet or some CPUs. And they are optimised so that you dont need to make them your self. One reason to my post is curiosity, I'd like to know what these larger devices are and what they cost. I once read that ATA ports are old simplified ISA ports in disguise, programming them may anyway be hard when Windows and PCIe try their best to stop you. This is interesting LeifArticle: 153438
LM <sala.nimi@mail.com> wrote: (snip, I wrote) >> You might be able to do UDP/IP, though. TCP is enough harder that >> I would have to agree. That processor could be fairly simple, and >> implemented in an FPGA. > Some microprocessors have Ethernet in them. And Ethernet is > certainly easier to use with a microprocessor. But what do you write to the ethernet? You need at least a TYPE (also called ethertype). UDP is a fairly simple header in front of the data. You also need ARP to make IP work, but you can fake that if needed, or use a simple state machine. > But then, I plan drive each pin > separately in a loop, and that is easier in VHDL. It is faster too. I > may end up using a FTDI chip or some similar serial to Ethernet chip > here with the FPGA chip. I can say that my Ethernet messaging is > really simple, but then, that can be handled with an Ethernet to > serial chip too. Usually it isn't so bad to have a processor (soft in the FPGA) do the harder parts like ARP, and otherwise directly write UDP to the ethernet chip. -- glenArticle: 153439
On Fri, 24 Feb 2012 08:54:26 -0800, LM wrote:
> On 24 helmi, 10:58, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>> Tim Wescott <t...@seemywebsite.com> wrote:
>>
>> (snip)
>>
>> > -- and, unless your Ethernet messaging is really low-level,
>> > boneheaded, and simplified, you're going to need a microprocessor to
>> > manage it anyway (no _way_ do you want to try to make an all-logic
>> > TCP/IP stack!). So you may as well get a micro that has on-board
>> > Ethernet (and serial, to boot).
>>
>> You might be able to do UDP/IP, though. TCP is enough harder that I
>> would have to agree. That processor could be fairly simple, and
>> implemented in an FPGA.
>>
>> > Why didn't I think of that?
>>
>> -- glen
>
> Some microprocessors have Ethernet in them. And Ethernet is certainly
> easier to use with a microprocessor. But then, I plan drive each pin
> separately in a loop, and that is easier in VHDL. It is faster too. I
> may end up using a FTDI chip or some similar serial to Ethernet chip
> here with the FPGA chip. I can say that my Ethernet messaging is really
> simple, but then, that can be handled with an Ethernet to serial chip
> too.
>
> When I studied VHDL, I heard that all larger devices have built in or
> optional logic block of common functions like Ethernet or some CPUs. And
> they are optimised so that you dont need to make them your self. One
> reason to my post is curiosity, I'd like to know what these larger
> devices are and what they cost.
Nope. There's scads of intellectual property ("soft core logic") that
implements that sort of thing, and there's a few FPGAs that have
processor cores embedded in them. But it's certainly not universal, and
while I don't know for sure what the market shares are, I'd guess that
90% of the FPGAs that ship do so without dedicated processors, PCI, or
other such hardware.
So - "built in", no. But "don't have to build it yourself" -- yes, sort
of, but you often need to be pretty sharp and knowledgeable to get a
chunk of IP working correctly with all the rest of your stuff on chip.
(I think there's even an ARM core that's designed to work on FPGAs these
days).
> I once read that ATA ports are old simplified ISA ports in disguise,
> programming them may anyway be hard when Windows and PCIe try their best
> to stop you.
PATA is a stripped-down ISA port. I'm really not up on what SATA is. I
wouldn't expect that PCI is going to "get in the way", because by
definition the PCI bus won't be active when you're doing ATA accesses.
You can count on having to have someone on your team who knows Windows
drivers if you want to use one -- but that's a software problem.
--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?
Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Article: 153440On Fri, 24 Feb 2012 18:40:03 +0000, glen herrmannsfeldt wrote: > LM <sala.nimi@mail.com> wrote: > > (snip, I wrote) >>> You might be able to do UDP/IP, though. TCP is enough harder that I >>> would have to agree. That processor could be fairly simple, and >>> implemented in an FPGA. > >> Some microprocessors have Ethernet in them. And Ethernet is certainly >> easier to use with a microprocessor. > > But what do you write to the ethernet? You need at least a TYPE (also > called ethertype). UDP is a fairly simple header in front of the data. > You also need ARP to make IP work, but you can fake that if needed, or > use a simple state machine. My understanding with Ethernet is that you can choose an unused port and just send out raw Ethernet packets fairly easily -- but that's based on a throw-away comment made by someone I trust, in an otherwise unrelated conversation. So it's in my bucket of "worthwhile to check" notions, but it certainly doesn't belong in my bucket of "count on it" ideas. Using an Ethernet soft core along with a processor soft core to handle a stack might work -- and might even come supported by an FPGA vendor. But by the time you get that much processing power into an FPGA I always start wondering if it isn't more wise to just put that much processing power _next to_ the FPGA, let the FPGA do the logic, and let the processor do the processing. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 153441
Tim Wescott <tim@seemywebsite.com> wrote: (snip) > My understanding with Ethernet is that you can choose an unused port and > just send out raw Ethernet packets fairly easily -- but that's based on a > throw-away comment made by someone I trust, in an otherwise unrelated > conversation. So it's in my bucket of "worthwhile to check" notions, but > it certainly doesn't belong in my bucket of "count on it" ideas. Ethernet without IP doesn't have ports. There is ethertype, which identifies the protocol in use. (IP is X'0800') You could use an unused ethertype, or maybe one reserved for testing. You could also put a UDP header on it with an unused UDP port. It is convenient toalso do ARP, but you could put a static ARP entry on some other host such that packets would be send to the right place, and a fixed ethernet MAC address in the FPGA for the destination. (For one-way communication, only one of those is needed.) > Using an Ethernet soft core along with a processor soft core to handle a > stack might work -- and might even come supported by an FPGA vendor. But > by the time you get that much processing power into an FPGA I always > start wondering if it isn't more wise to just put that much processing > power _next to_ the FPGA, let the FPGA do the logic, and let the > processor do the processing. For fast transfer, you want the FPGA logic connected to the ethernet device as direct as possible. Then a processor to handle the less time sensitive tasks like ARP and routing. -- glenArticle: 153442
On 25 helmi, 10:31, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Tim Wescott <t...@seemywebsite.com> wrote: > > (snip) > > > My understanding with Ethernet is that you can choose an unused port an= d > > just send out raw Ethernet packets fairly easily -- but that's based on= a > > throw-away comment made by someone I trust, in an otherwise unrelated > > conversation. =A0So it's in my bucket of "worthwhile to check" notions,= but > > it certainly doesn't belong in my bucket of "count on it" ideas. > > Ethernet without IP doesn't have ports. There is ethertype, which > identifies the protocol in use. (IP is X'0800') You could use an > unused ethertype, or maybe one reserved for testing. > > You could also put a UDP header on it with an unused UDP port. > It is convenient toalso do ARP, but you could put a static ARP > entry on some other host such that packets would be send to the > right place, and a fixed ethernet MAC address in the FPGA for the > destination. (For one-way communication, only one of those is needed.) > > > Using an Ethernet soft core along with a processor soft core to handle = a > > stack might work -- and might even come supported by an FPGA vendor. = =A0But > > by the time you get that much processing power into an FPGA I always > > start wondering if it isn't more wise to just put that much processing > > power _next to_ the FPGA, let the FPGA do the logic, and let the > > processor do the processing. > > For fast transfer, you want the FPGA logic connected to the ethernet > device as direct as possible. Then a processor to handle the less > time sensitive tasks like ARP and routing. > > -- glen I think it is either a microcontroller with Ethernet, like Arduino, or a Ethernet chip. What is a good, simple to use or easy to get running Ethernet chip. But I have to check Ethernet modules too. What I remember of them, they are like a virtual serial port. That could also work. It was some years ago I studied VHDL. So It is quite possible that I miss heard or something, about those macro blocks. I checked also Open Cores some time ago. They are like a big software projects, it is difficult to know even where to start. Well that is what they are, they are big sw projects. It is faster and easier to do this with an other way.Article: 153443
My problem got solved, had to do the timing analysis once again. Although XST wasn't reporting any timing failures, but I was on boundary, so once in a while I was getting the issue. As far as your issue is concerned, what you are missing as pointed out by NP is that you have two clock domains. So, you need to sync these two clock domains. I think your phy is giving you both TXCLK and RXCLK at 25Mhz, for 100Mbps, correct me if i am wrong. The best thing would be use a buffer at the incoming interface, write the data to the FIFO on RXCLK and after 4-5 writes, read the packet bytes at TXCLK. Also, you do know how the ethernet works, right ? like in 100Mbps you have to deal with a nibble at a time, and in 1000Mbps, it's a byte. Anyway, your issue of loopback will be solved by syncing the clock domains. >"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message >> tnx for your comment, so what should i do? i have tested the following >> code >> too, but still i have error in receiving packets. >> assign RTL_TXE=RTL_RXDV; >> assign RTL_TXD=RTL_RXD; > >If your receiver gives you a clock, put that on a global clock, work with >the data in this domain and also feed the transmitter with it. Be careful >with timing. I would need your schematic diagram to tell more. > >> tnx in advanced for help :) >> Neda Baheri > >NP > > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153444
hi all I am currently struggling trying to write Strassens Algorithm for matrix multiplication in VHDL. I have written the code for 2x2 matrices, but now have to develop it to implement 4x4 matrices or larger. Can anyone help please. Thank YouArticle: 153445
On Feb 23, 5:46=A0am, LM <sala.n...@mail.com> wrote: > I am looking for a chip with somekind of communication port inbuilt. I > am slowly planning a system where some data is sent from a computer to > be processed in the chip. > > Processing data is probably easy, but I prefer not to make a serial > port my self and an ethernet port is too much. But an Ethernet port > would be very nice to have. > > I would like to have a reasonably priced chip with low cost evaluation > board. And I need as many outputs I can get. Some time ago I was told > here about LCMXO2-1200ZE-B-EVN and others. It is a good kit/chip but > it doesn't have serial port logic built in. MachXO2 has SPI and i2c ports.built in. You really need to state some numbers, 'a bit slow' is not good enough. Specify how fast it needs to be and how much data needs to be sent each way, and over what distance. High speed serial is no slouch, you can get 12MBd Async easily, and more with sync protocols out of something like a FT2232H The FT2232H and Ethernet are available as small modules, (one is even free on the MaxhXO2 boards..) so start with those, and pull them into the logic only if you really need to. -jgArticle: 153446
>My problem got solved, had to do the timing analysis once again. Although
>XST wasn't reporting any timing failures, but I was on boundary, so once
in
>a while I was getting the issue.
>
>As far as your issue is concerned, what you are missing as pointed out by
>NP is that you have two clock domains. So, you need to sync these two
clock
>domains. I think your phy is giving you both TXCLK and RXCLK at 25Mhz,
for
>100Mbps, correct me if i am wrong.
>
>The best thing would be use a buffer at the incoming interface, write the
>data to the FIFO on RXCLK and after 4-5 writes, read the packet bytes at
>TXCLK.
>Also, you do know how the ethernet works, right ? like in 100Mbps you
have
>to deal with a nibble at a time, and in 1000Mbps, it's a byte.
>
>Anyway, your issue of loopback will be solved by syncing the clock
>domains.
>
>
>>"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
>>> tnx for your comment, so what should i do? i have tested the following
>>> code
>>> too, but still i have error in receiving packets.
>>> assign RTL_TXE=RTL_RXDV;
>>> assign RTL_TXD=RTL_RXD;
>>
>>If your receiver gives you a clock, put that on a global clock, work
with
>
>>the data in this domain and also feed the transmitter with it. Be
careful
>
>>with timing. I would need your schematic diagram to tell more.
>>
>>> tnx in advanced for help :)
>>> Neda Baheri
>>
>>NP
>>
>>
>>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
>
hi
tnx for your suggestion, i am working on the fpga program as you suggested,
but my problem still exist,i used chipscope to debug the problem, the data
is received fine to fpga but it seemed that the data is not write and read
back from dual port ram, here is the code. i don't know what's the problem
and how should i proceed? thanks in advanced for help
i read the data received from lan in this process and write in DPRAM,
generate a strob to transmit process to start sending data at the falling
edge of RXDV, and capturing the end of packet transmition for reseting
write address:
always @(posedge RTL_RXCLK)
begin
/// Reading Data from RXD pin and save it in dpram
if(RTL_RXDV)
begin
write_address2 <= write_address2+1;
Ram_Data_In <= RTL_RXD;
Ram_Write_Enable<=1;
end
else
Ram_Write_Enable<=0;
///Set Receive Packet Strob to transmit section
pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
begin
loopback_data<=1;
PacketReceived <= PacketReceived +1;
end
/// reset Receive Packet Strob
if(loopback_data)
begin
DelayCcLpbackData <= DelayCcLpbackData + 1;
if(DelayCcLpbackData>=50)
begin
loopback_data<=0;
DelayCcLpbackData<=0;
end
end
/// capture End ot Trasmission
preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
begin
write_address2<=0;
end
end
//////
always @(posedge RTL_TXCLK )
begin
/// Capture Rising edge of Receive packet Strob generated by
receive process
pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
begin
StartSendingData<=1;
end
// start transmitting data
if(StartSendingData)
begin
read_address2<=read_address2+1;
rgRTL_TXD<=Ram_Data_Out;
rgRTL_TXE <=1;
re_en<=1;
if(read_address2>write_address2)
begin
read_address2<=0;
re_en<=0;
rgRTL_TXE <=0;
End_Sending_Strobe <= 1;
StartSendingData<=0;
end
end
//////////////
if(End_Sending_Strobe)
begin
DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
if(DelayCcResetSendStrobe>=50)
begin
DelayCcResetSendStrobe <= 0;
End_Sending_Strobe <= 0;
end
end
end
duall_ram2 duall_ram2_in2
(
.CLCK_re(RTL_TXCLK),
.CLCK_wr(RTL_RXCLK),
.DIN(Ram_Data_In),
.Re(re_en),
.RE_ADDRESS(read_address2),
.We(Ram_Write_Enable),
.wr_address(write_address2),
.dout(Ram_Data_Out)
);
and the module for DPRAM is :
entity duall_ram2 is
Port ( DIN : in std_logic_vector(3 downto 0);
RE_ADDRESS : in std_logic_vector(10 downto 0);
wr_address :in std_logic_vector(10 downto 0);
CLCK_wr : in std_logic;
CLCK_re : in std_logic;
We : in std_logic;
Re : in std_logic;
dout : out std_logic_vector(3 downto 0));
end duall_ram2 ;
architecture Behavioral of duall_ram2 is
type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
signal rom: my_data;
begin
process (clck_wr)--write
begin
if (clck_wr'event and clck_wr = '0') then
if (we = '1') then
rom(conv_integer(WR_address)) <= din;
end if;
end if;
end process;
process (clck_re)--read
begin
if (clck_re'event and clck_re = '0') then ---e
if (Re = '1') then
dout<=rom(conv_integer(RE_address));
end if;
end if;
end process;
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 153447
and one thing more, i also used the dual port ram from ISE instances , but
out put is the same.
tnx in advanced for help
RAMB16_S4_S4 RAMB16_S4_S4_inst
(
// .DOA(), // Port A 4-bit Data Output
.DOB(Ram_Data_Out), // Port B 4-bit Data Output
.ADDRA(write_address2), // Port A 12-bit Address Input
.ADDRB(read_address2), // Port B 12-bit Address Input
.CLKA(GlobalClk), // Port A Clock
.CLKB(GlobalClk), // Port B Clock
.DIA(Ram_Data_In), // Port A 4-bit Data Input
//.DIB(DIB), // Port B 4-bit Data Input
.ENA(1), // Port A RAM Enable Input
.ENB(1), // Port B RAM Enable Input
.SSRA(0), // Port A Synchronous Set/Reset Input
.SSRB(0), // Port B Synchronous Set/Reset Input
.WEA(Ram_Write_Enable), // Port A Write Enable Input
.WEB(0) // Port B Write Enable Input
);
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 153448>hi all >I am currently struggling trying to write Strassens Algorithm for >matrix multiplication in VHDL. I have written the code for 2x2 >matrices, but now have to develop it to implement 4x4 matrices or >larger. >Can anyone help please. >Thank You Unless you have reached the limit of on-FPGA multipliers, the extra control complexity makes such an algorithm unattractive for real-world applications. Is this an educational assignment? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153449
On Sun, 26 Feb 2012 09:28:49 -0800, rsr1991 wrote: > hi all > I am currently struggling trying to write Strassens Algorithm for matrix > multiplication in VHDL. I have written the code for 2x2 matrices, but > now have to develop it to implement 4x4 matrices or larger. > Can anyone help please. > Thank You Why don't you do a practical implementation of Strassen's Algorithm, per the Wikipedia page: "Practical implementations of Strassen's algorithm switch to standard methods of matrix multiplication for small enough submatrices, for which those algorithms are more efficient. The particular crossover point for which Strassen's algorithm is more efficient depends on the specific implementation and hardware." My feeling on this is that you are only going to benefit from this algorithm if you have a pretty darn big matrix (32 by 32 is probably still "small"), a processor for which addition, subtraction, _and general- purpose ALU_ instructions are significantly cheaper than multiplication, and either a lot of engineering time to spend freely, or a desperate need to cut just a little bit (less than 14%) off of the time to do a matrix multiply. Note that you are replacing eight (matrix) multiplies and four additions with seven multiplies -- and _eight_ additions or subtractions. On a processor, with IEEE floating point, I'm not sure that Strassen's Algorithm wouldn't take _more_ computational resources to complete that a bog-standard matrix multiply. I could see incorporating this (or one of the more optimal algorithms) into a general-purpose math package (if it actually worked), but the notion of going to so much trouble for so little gain kind of boggles my mind -- wouldn't you get more speedup by hand-flogging your timing, and increasing your clock rate a bit, or otherwise tuning the rest of your algorithm? -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z