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On 7/29/2012 7:00 PM, Phil wrote: > On Sunday, July 29, 2012 12:56:32 PM UTC-5, BobH wrote: >> On 7/28/2012 5:39 PM, pminmo@gmail.com wrote: >> >>> If I use the core generator to generate an IBERT for a Spartan 6 and try to implement the example design the errors I'm getting I'm not understanding. I'm assuming I'm not understanding the back box portion of the example design. Module S6chipscope_ibert.v is in the project. Thanks in advance... Here are the errors, followed by the example design: >> >>> >> >>> ERROR:NgdBuild:604 - logical block 'U_S6CHIPSCOPE_IBERT' with type >> >>> 'S6chipscope_ibert' could not be resolved. A pin name misspelling can cause >> >>> this, a missing edif or ngc file, case mismatch between the block name and >> >>> the edif or ngc file name, or the misspelling of a type name. Symbol >> >>> 'S6chipscope_ibert' is not supported in target 'spartan6'. >> >>> ERROR:NgdBuild:604 - logical block 'U_ICON' with type 'chipscope_icon' could not >> >>> be resolved. A pin name misspelling can cause this, a missing edif or ngc >> >>> file, case mismatch between the block name and the edif or ngc file name, or >> >>> the misspelling of a type name. Symbol 'chipscope_icon' is not supported in >> >>> target 'spartan6'. >> >>> >> >> >> >> Do you have the .ngc file for the ibert module in the project directory? >> >> It contains the actual module guts. >> >> >> >> Good Luck, >> >> BobH > > Yes, I've tried the ngc file(s) with no luck. > It really sounds like the .ngc files are not where they can be found by the tool. The .v file is only a wrapper/prototype for the contents in the .ngc file. Is the .ngc file for the ibert in the project top level directory (where the log files and .pcf file wind up) and the .ngc name matches the one instantiated in your RTL file? I think that there is a place in the project properties page where you can explicitly tell it where to find the .ngc files. Another possibility would be if you added the .v file to the project after the project was defined, did it go into the same library as the rest of your RTL? If you look in the files window on ISE and scroll to the right, past the end of the file names, it will tell you which library a file went into. I spent 3 days fighting an issue like this, only to find that the file went into a different library and did not get included in the synthesis. Good Luck, BobHArticle: 154076
Hi all,
I'm learning Verilog. Trying to design a multiplexer:
module vector_net_multiplexer_tb;
reg [3:0] input1, input2, input3, sel_ip;
reg [1:0] sel;
initial
begin
$dumpfile ("vector_net_multiplexer_tb.vcd");
$dumpvars (1, vector_net_multiplexer_tb);
$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
input1, input2, input3, sel, sel_ip);
sel = 2'b00;
input1 = 4'b1010;
input2 = 4'b1100;
input3 = 4'b0110;
#5 sel = 2'b01;
#10 sel = 2'b10;
#15 sel = 2'b11;
#20 sel = 2'b10;
#25 $finish;
end
vector_net_multiplexer mux0 (
.input1(input1),
.input2(input2),
.input3(input3),
.sel(.sel),
.sel_ip(sel_ip)
);
endmodule // vector_net_multiplexer_tb
module vector_net_multiplexer(
//inputs
input [3:0] input1,
input [3:0] input2,
input [3:0] input3,
input [1:0] sel,
//output
output [3:0] sel_ip
);
reg sel_ip;
reg sel;
always @ ( input1 or input2 or input3 or sel)
begin
case (sel)
2'b00:
sel_ip = input1;
2'b01:
sel_ip = input2;
2'b10:
sel_ip = input3;
2'b11:
sel_ip = input1;
endcase // case (sel)
end
endmodule // vector_net_multiplexer
compiling with icarus verilog gives:
iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
vector_net_multiplexer_tb.v:29: syntax error
vector_net_multiplexer_tb.v:29: error: invalid port connection expression.
Can someone tell me what the problem is?
Thanks,
asp5
Article: 154077
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
> Hi all,
>
>
>
> I'm learning Verilog. Trying to design a multiplexer:
>
>
>
> module vector_net_multiplexer_tb;
>
>
>
> reg [3:0] input1, input2, input3, sel_ip;
>
> reg [1:0] sel;
>
>
>
> initial
>
> begin
>
> $dumpfile ("vector_net_multiplexer_tb.vcd");
>
> $dumpvars (1, vector_net_multiplexer_tb);
>
> $monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
>
> input1, input2, input3, sel, sel_ip);
>
>
>
> sel = 2'b00;
>
> input1 = 4'b1010;
>
> input2 = 4'b1100;
>
> input3 = 4'b0110;
>
>
>
> #5 sel = 2'b01;
>
> #10 sel = 2'b10;
>
> #15 sel = 2'b11;
>
> #20 sel = 2'b10;
>
> #25 $finish;
>
> end
>
>
>
> vector_net_multiplexer mux0 (
>
> .input1(input1),
>
> .input2(input2),
>
> .input3(input3),
>
> .sel(.sel),
>
> .sel_ip(sel_ip)
>
> );
>
>
>
>
>
> endmodule // vector_net_multiplexer_tb
>
>
>
>
>
>
>
> module vector_net_multiplexer(
>
> //inputs
>
> input [3:0] input1,
>
> input [3:0] input2,
>
> input [3:0] input3,
>
>
>
> input [1:0] sel,
>
>
>
> //output
>
> output [3:0] sel_ip
>
> );
>
> reg sel_ip;
>
> reg sel;
>
>
>
> always @ ( input1 or input2 or input3 or sel)
>
> begin
>
> case (sel)
>
> 2'b00:
>
> sel_ip = input1;
>
> 2'b01:
>
> sel_ip = input2;
>
> 2'b10:
>
> sel_ip = input3;
>
> 2'b11:
>
> sel_ip = input1;
>
> endcase // case (sel)
>
> end
>
>
>
> endmodule // vector_net_multiplexer
>
>
>
>
>
>
>
>
>
> compiling with icarus verilog gives:
>
>
>
> iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
>
> vector_net_multiplexer_tb.v:29: syntax error
>
> vector_net_multiplexer_tb.v:29: error: invalid port connection expression.
>
>
>
>
>
> Can someone tell me what the problem is?
>
>
>
> Thanks,
>
> asp5
Hi,
one dot too much in line 29:
.sel(.sel),
^
Have a nice synthesis
Eilert
Article: 154078
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
> Hi all,
>
>
>
> I'm learning Verilog. Trying to design a multiplexer:
>
>
>
> module vector_net_multiplexer_tb;
>
>
>
> reg [3:0] input1, input2, input3, sel_ip;
>
> reg [1:0] sel;
>
>
>
> initial
>
> begin
>
> $dumpfile ("vector_net_multiplexer_tb.vcd");
>
> $dumpvars (1, vector_net_multiplexer_tb);
>
> $monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
>
> input1, input2, input3, sel, sel_ip);
>
>
>
> sel = 2'b00;
>
> input1 = 4'b1010;
>
> input2 = 4'b1100;
>
> input3 = 4'b0110;
>
>
>
> #5 sel = 2'b01;
>
> #10 sel = 2'b10;
>
> #15 sel = 2'b11;
>
> #20 sel = 2'b10;
>
> #25 $finish;
>
> end
>
>
>
> vector_net_multiplexer mux0 (
>
> .input1(input1),
>
> .input2(input2),
>
> .input3(input3),
>
> .sel(.sel),
>
> .sel_ip(sel_ip)
>
> );
>
>
>
>
>
> endmodule // vector_net_multiplexer_tb
>
>
>
>
>
>
>
> module vector_net_multiplexer(
>
> //inputs
>
> input [3:0] input1,
>
> input [3:0] input2,
>
> input [3:0] input3,
>
>
>
> input [1:0] sel,
>
>
>
> //output
>
> output [3:0] sel_ip
>
> );
>
> reg sel_ip;
>
> reg sel;
>
>
>
> always @ ( input1 or input2 or input3 or sel)
>
> begin
>
> case (sel)
>
> 2'b00:
>
> sel_ip = input1;
>
> 2'b01:
>
> sel_ip = input2;
>
> 2'b10:
>
> sel_ip = input3;
>
> 2'b11:
>
> sel_ip = input1;
>
> endcase // case (sel)
>
> end
>
>
>
> endmodule // vector_net_multiplexer
>
>
>
>
>
>
>
>
>
> compiling with icarus verilog gives:
>
>
>
> iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
>
> vector_net_multiplexer_tb.v:29: syntax error
>
> vector_net_multiplexer_tb.v:29: error: invalid port connection expression.
>
>
>
>
>
> Can someone tell me what the problem is?
>
>
>
> Thanks,
>
> asp5
Hi,
one dot too much in line 29:
.sel(.sel),
^
Have a nice synthesis
Eilert
Article: 154079
On Monday, July 30, 2012 11:15:43 PM UTC-7, (unknown) wrote:
> Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
>
> > Hi all,
>
> >
>
> >
>
> >
>
> > I'm learning Verilog. Trying to design a multiplexer:
>
> >
>
> >
>
> >
>
> > module vector_net_multiplexer_tb;
>
> >
>
> >
>
> >
>
> > reg [3:0] input1, input2, input3, sel_ip;
>
> >
>
> > reg [1:0] sel;
>
> >
>
> >
>
> >
>
> > initial
>
> >
>
> > begin
>
> >
>
> > $dumpfile ("vector_net_multiplexer_tb.vcd");
>
> >
>
> > $dumpvars (1, vector_net_multiplexer_tb);
>
> >
>
> > $monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
>
> >
>
> > input1, input2, input3, sel, sel_ip);
>
> >
>
> >
>
> >
>
> > sel = 2'b00;
>
> >
>
> > input1 = 4'b1010;
>
> >
>
> > input2 = 4'b1100;
>
> >
>
> > input3 = 4'b0110;
>
> >
>
> >
>
> >
>
> > #5 sel = 2'b01;
>
> >
>
> > #10 sel = 2'b10;
>
> >
>
> > #15 sel = 2'b11;
>
> >
>
> > #20 sel = 2'b10;
>
> >
>
> > #25 $finish;
>
> >
>
> > end
>
> >
>
> >
>
> >
>
> > vector_net_multiplexer mux0 (
>
> >
>
> > .input1(input1),
>
> >
>
> > .input2(input2),
>
> >
>
> > .input3(input3),
>
> >
>
> > .sel(.sel),
>
> >
>
> > .sel_ip(sel_ip)
>
> >
>
> > );
>
> >
>
> >
>
> >
>
> >
>
> >
>
> > endmodule // vector_net_multiplexer_tb
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> > module vector_net_multiplexer(
>
> >
>
> > //inputs
>
> >
>
> > input [3:0] input1,
>
> >
>
> > input [3:0] input2,
>
> >
>
> > input [3:0] input3,
>
> >
>
> >
>
> >
>
> > input [1:0] sel,
>
> >
>
> >
>
> >
>
> > //output
>
> >
>
> > output [3:0] sel_ip
>
> >
>
> > );
>
> >
>
> > reg sel_ip;
>
> >
>
> > reg sel;
>
> >
>
> >
>
> >
>
> > always @ ( input1 or input2 or input3 or sel)
>
> >
>
> > begin
>
> >
>
> > case (sel)
>
> >
>
> > 2'b00:
>
> >
>
> > sel_ip = input1;
>
> >
>
> > 2'b01:
>
> >
>
> > sel_ip = input2;
>
> >
>
> > 2'b10:
>
> >
>
> > sel_ip = input3;
>
> >
>
> > 2'b11:
>
> >
>
> > sel_ip = input1;
>
> >
>
> > endcase // case (sel)
>
> >
>
> > end
>
> >
>
> >
>
> >
>
> > endmodule // vector_net_multiplexer
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> > compiling with icarus verilog gives:
>
> >
>
> >
>
> >
>
> > iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
>
> >
>
> > vector_net_multiplexer_tb.v:29: syntax error
>
> >
>
> > vector_net_multiplexer_tb.v:29: error: invalid port connection expression.
>
> >
>
> >
>
> >
>
> >
>
> >
>
> > Can someone tell me what the problem is?
>
> >
>
> >
>
> >
>
> > Thanks,
>
> >
>
> > asp5
>
>
>
> Hi,
>
> one dot too much in line 29:
>
> .sel(.sel),
>
> ^
>
>
>
> Have a nice synthesis
>
> Eilert
Thanks Eilert. Did not notice this :)
Article: 154080asp654@gmail.com wrote: (snip) > module vector_net_multiplexer( > //inputs > input [3:0] input1, > input [3:0] input2, > input [3:0] input3, > input [1:0] sel, > //output > output [3:0] sel_ip > ); > reg sel_ip; > reg sel; I don't think this is the reason for the message, but I wouldn't have made sel a reg. Maybe it doesn't matter, though. > always @ ( input1 or input2 or input3 or sel) > begin > case (sel) > 2'b00: > sel_ip = input1; > 2'b01: > sel_ip = input2; > 2'b10: > sel_ip = input3; > 2'b11: > sel_ip = input1; > endcase // case (sel) > end > endmodule // vector_net_multiplexer -- glenArticle: 154081
goouse99@googlemail.com wrote:
> Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
>> Hi all,
>>
>>
>>
>> I'm learning Verilog. Trying to design a multiplexer:
>>
>>
>>
>> module vector_net_multiplexer_tb;
>>
>>
>>
>> reg [3:0] input1, input2, input3, sel_ip;
>>
>> reg [1:0] sel;
>>
>>
>>
>> initial
>>
>> begin
>>
>> $dumpfile ("vector_net_multiplexer_tb.vcd");
>>
>> $dumpvars (1, vector_net_multiplexer_tb);
>>
>> $monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
>>
>> input1, input2, input3, sel, sel_ip);
>>
>>
>>
>> sel = 2'b00;
>>
>> input1 = 4'b1010;
>>
>> input2 = 4'b1100;
>>
>> input3 = 4'b0110;
>>
>>
>>
>> #5 sel = 2'b01;
>>
>> #10 sel = 2'b10;
>>
>> #15 sel = 2'b11;
>>
>> #20 sel = 2'b10;
>>
>> #25 $finish;
>>
>> end
>>
>>
>>
>> vector_net_multiplexer mux0 (
>>
>> .input1(input1),
>>
>> .input2(input2),
>>
>> .input3(input3),
>>
>> .sel(.sel),
>>
>> .sel_ip(sel_ip)
>>
>> );
>>
>>
>>
>>
>>
>> endmodule // vector_net_multiplexer_tb
>>
>>
>>
>>
>>
>>
>>
>> module vector_net_multiplexer(
>>
>> //inputs
>>
>> input [3:0] input1,
>>
>> input [3:0] input2,
>>
>> input [3:0] input3,
>>
>>
>>
>> input [1:0] sel,
>>
>>
>>
>> //output
>>
>> output [3:0] sel_ip
>>
>> );
>>
>> reg sel_ip;
>>
>> reg sel;
>>
>>
>>
>> always @ ( input1 or input2 or input3 or sel)
>>
>> begin
>>
>> case (sel)
>>
>> 2'b00:
>>
>> sel_ip = input1;
>>
>> 2'b01:
>>
>> sel_ip = input2;
>>
>> 2'b10:
>>
>> sel_ip = input3;
>>
>> 2'b11:
>>
>> sel_ip = input1;
>>
>> endcase // case (sel)
>>
>> end
>>
>>
>>
>> endmodule // vector_net_multiplexer
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> compiling with icarus verilog gives:
>>
>>
>>
>> iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
>>
>> vector_net_multiplexer_tb.v:29: syntax error
>>
>> vector_net_multiplexer_tb.v:29: error: invalid port connection expression.
>>
>>
>>
>>
>>
>> Can someone tell me what the problem is?
>>
>>
>>
>> Thanks,
>>
>> asp5
>
> Hi,
> one dot too much in line 29:
> .sel(.sel),
> ^
>
> Have a nice synthesis
> Eilert
It also looks like you might mis-understand the operation of the delays:
#5 sel = 2'b01;
#10 sel = 2'b10;
#15 sel = 2'b11;
#20 sel = 2'b10;
#25 $finish;
Each of the #delays adds to the previous delay, so you will
wait 5 units (usually ns, but it depends on `timescale) then
another 10 units, then another 15 units, etc. If you want to
use absolute times, then you need to either use non-blocking
assignments (this gets a bit hairy) or place each in its own
initial block.
-- Gabor
Article: 154082Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm It says "low cost", but how low is low? Is there a distributor who has stocked it or shows at least a lead time? And there is no non-BGA package for it (like TQFP) anymore? -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 154083
Frank Buss wrote: > Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: > > http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm > > It says "low cost", but how low is low? Is there a distributor who has > stocked it or shows at least a lead time? And there is no non-BGA > package for it (like TQFP) anymore? > I got the vaporware ad, too. I checked the franchised distributors, but none of them even acknowledge the existence of Artix-7. My guess is that "shipping" means something different to Xilinx than it does to you and me. Probably they have sampled the parts to some early adopters. -- GaborArticle: 154084
Gabor wrote: > Frank Buss wrote: >> Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: >> >> http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm >> >> It says "low cost", but how low is low? Is there a distributor who has >> stocked it or shows at least a lead time? And there is no non-BGA >> package for it (like TQFP) anymore? >> > > I got the vaporware ad, too. I checked the franchised distributors, > but none of them even acknowledge the existence of Artix-7. My guess > is that "shipping" means something different to Xilinx than it does > to you and me. Probably they have sampled the parts to some early > adopters. > > -- Gabor I forgot to add - the reason why I was looking was to see availability more than pricing. Early pricing is generally different from pricing a year or more into production. I also wanted to know which parts were "shipped." Usually Xilinx starts with a part somewhere in the middle of the density spectrum, but it's not clear where they would start with Artix-7 - perhaps at the high end to try to recover more NRE costs? Most of us interested in low-cost FPGA's are more likely to want the smallest part, which still has 100K "Logic Elements" (multiply LUT's times 1.6 for LE's). And I wouldn't hold my breath waiting for non-BGA packaging in 7-series parts. -- GaborArticle: 154085
They started putting PRs out about these devices out over 2 years ago. Don't believe anything Xilinx says until they are in stock.Article: 154086
Gabor wrote: > Gabor wrote: >> Frank Buss wrote: >>> Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: >>> >>> http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm >>> >>> It says "low cost", but how low is low? Is there a distributor who has >>> stocked it or shows at least a lead time? And there is no non-BGA >>> package for it (like TQFP) anymore? >>> >> >> I got the vaporware ad, too. I checked the franchised distributors, >> but none of them even acknowledge the existence of Artix-7. My guess >> is that "shipping" means something different to Xilinx than it does >> to you and me. Probably they have sampled the parts to some early >> adopters. >> >> -- Gabor > > I forgot to add - the reason why I was looking was to see availability > more than pricing. Early pricing is generally different from pricing > a year or more into production. I also wanted to know which parts > were "shipped." Usually Xilinx starts with a part somewhere in the > middle of the density spectrum, but it's not clear where they would > start with Artix-7 - perhaps at the high end to try to recover more > NRE costs? Most of us interested in low-cost FPGA's are more likely > to want the smallest part, which still has 100K "Logic Elements" > (multiply LUT's times 1.6 for LE's). And I wouldn't hold my breath > waiting for non-BGA packaging in 7-series parts. > > -- Gabor OK, it took some digging, but I found the press release: http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1715211&highlight= Apparently they are starting with the XC7A100T (smallest device). -- GaborArticle: 154087
On Wed, 1 Aug 2012 06:24:02 -0700 (PDT) Jon <jon@beniston.com> wrote: > They started putting PRs out about these devices out over 2 years ago. > > Don't believe anything Xilinx says until they are in stock. Can you think of a semi vendor for whom that statement _isn't_ true? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 154088
Gabor wrote: > > OK, it took some digging, but I found the press release: > > http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1715211&highlight= Thanks. This was from July 17, 2012: "Xilinx, Inc. (NASDAQ: XLNX) today announced first shipments of its Artixâ„¢-7 Field Programmable Gate Array (FPGA) family." Well, let's take pot luck when they will really ship it to end customers :-) > Apparently they are starting with the XC7A100T (smallest device). This would be good for my project. I was asking, because a CPLD is just by a factor of 3 of 4 too small, so any small FPGA device would work. But I guess the new Artix devices would be still more expensive than e.g. the Spartan 3A, which I hope will be produced for some more years. -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 154089
Frank Buss <fb@frank-buss.de> writes: > Gabor wrote: >> >> OK, it took some digging, but I found the press release: >> >> http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1715211&highlight= > > Thanks. This was from July 17, 2012: "Xilinx, Inc. (NASDAQ: XLNX) today > announced first shipments of its Artix™-7 Field Programmable Gate Array > (FPGA) family." > > Well, let's take pot luck when they will really ship it to end customers :-) > >> Apparently they are starting with the XC7A100T (smallest device). > > This would be good for my project. I was asking, because a CPLD is just > by a factor of 3 of 4 too small, so any small FPGA device would work. > But I guess the new Artix devices would be still more expensive than > e.g. the Spartan 3A, which I hope will be produced for some more years. The 7A100 is *massive* though (some smaller Artix devices got dropped last year IIRC): * ~100K "logic cells" (63k 6-LUTs, 127k FFs), 240 DSP blocks, nearly 5Mbit Block RAM! for a small cheap FPGA you still want Spartan 6 - smallest is 6SLX4: * ~4K "logic cells" (2400 6-LUTs, 4800 FFs), 8 DSP blocks, 216Kb Blockram. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 154090
> The 7A100 is *massive* though (some smaller Artix devices got dropped last year IIRC): > > Does anyone (without NDA) knows why the smaller devices got dropped, if there will some smaller devices reappear, and what the costs for "normal" quantities of the 7A100 are? Regards, ThomasArticle: 154091
Martin Thompson wrote: > > The 7A100 is *massive* though (some smaller Artix devices got dropped last year IIRC): > > * ~100K "logic cells" (63k 6-LUTs, 127k FFs), 240 DSP blocks, nearly 5Mbit Block RAM! > > for a small cheap FPGA you still want Spartan 6 - smallest is 6SLX4: > > * ~4K "logic cells" (2400 6-LUTs, 4800 FFs), 8 DSP blocks, 216Kb Blockram. Thanks, this looks good. Just 2 EUR more expensive at Digikey than the Spartan 3, but more features. I think I'll use a 6SLX4. BTW: this is my project, which I want to upgrade to a FPGA: http://www.ohwr.org/projects/c64cartridge/wiki Should be hobby user friendly, so no BGA. -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 154092
I would forget about using an Artix until next year as I cant see anyone having them until then. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 154093
> Thanks, this looks good. Just 2 EUR more expensive at Digikey than the > Spartan 3, but more features. I think I'll use a 6SLX4. Maybe You'd like to take Altera parts into consideration? P.S. The project page is seems like half-lithuanian? :-)Article: 154094
Hi, I have been using Avnet V5 LX110T PCIe develoment board on a Windows XP 32-bit platform with generic 32-bit device driver from Jungo. I need to migrate to a 64-bit platform as my app requires more physical memory (system RAM) for data processing. I am looking for a 64-bit kernel mode driver for the Avnet V5 PCIe board which will install the FPGA board on the 64 bit OS platform. So far I have not been able to find any, Avnet does not support or provice any except the legacy 32- bit driver. Any help in converting the existing 32-bit driver to 64- bit kernel mode driver OR finding a suitable one will be highly appreciated. I hope the same 64-bit kernel mode driver will work for ML605 Virtex 6 FPGA board ! RegardsArticle: 154095
scrts wrote: >> Thanks, this looks good. Just 2 EUR more expensive at Digikey than the >> Spartan 3, but more features. I think I'll use a 6SLX4. > > Maybe You'd like to take Altera parts into consideration? Any device which is cheaper than a Spartan 6 (I need at least 144 pins)? I get the XC6SLX4-2TQG144C for EUR 9.89 from Digikey. Looks like the cheapest Cyclone I with TQFP 144 costs EUR 9.96 at Altera, and it is less powerful than the Spartan 6. > P.S. The project page is seems like half-lithuanian? :-) The menu and navigation? Looks like the site tries to localize it, it is German for me. I hope you don't mean my not so good English :-) -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 154096
Frank Buss wrote: > > Any device which is cheaper than a Spartan 6 (I need at least 144 pins)? > I get the XC6SLX4-2TQG144C for EUR 9.89 from Digikey. Looks like the > cheapest Cyclone I with TQFP 144 costs EUR 9.96 at Altera, and it is > less powerful than the Spartan 6. > The Lattice XO2's might also be a good fit, non-volatile (no boot rom needed). The TQ100 pkg covers 256-2000 4-LUTs ( USD $4-$11 qty 1 @ DigiKey ) The TQ144 pkg covers 640-7000 4-LUTs ( USD $7-$14 qty 1 @ DigiKey ) http://www.latticesemi.com/products/cpld/machxo2/index.cfm Less block RAM & no DSP's compared to similar normalized LUT-count S6 parts; Lattice's XP2 family includes DSP blocks in a TQ144 pkg. Another thing I like about the Lattice parts is that their free Diamond tool includes the OEM version of Synplify. BrianArticle: 154097
Brian Davis wrote: > The Lattice XO2's might also be a good fit, non-volatile (no boot rom needed). > > The TQ100 pkg covers 256-2000 4-LUTs ( USD $4-$11 qty 1 @ DigiKey ) > The TQ144 pkg covers 640-7000 4-LUTs ( USD $7-$14 qty 1 @ DigiKey ) > http://www.latticesemi.com/products/cpld/machxo2/index.cfm > > Less block RAM & no DSP's compared to similar normalized LUT-count S6 parts; > Lattice's XP2 family includes DSP blocks in a TQ144 pkg. > > Another thing I like about the Lattice parts is that their free > Diamond tool includes the OEM version of Synplify. Looks interesting. I don't know Synplify, but a OEM version of Aldec Active-HDL is integrated, too, which I've used sometime ago and which was very good for debugging. And the 'C' parts need only one 3.3 V supply voltage for core and IO, so I don't need another voltage regulator (and power supply ramp rates requirements are very easy to fulfil: 0.01 - 100 mV/μs). I've installed the Diamond IDE and it is very similar to Xilinx ISE. My current design, but with a 1 MB external SRAM instead of 128 kB, fits in 125 LUTs and the VHDL file compiled without changes (just some more warnings about unused pins). -- Frank Buss, http://www.frank-buss.de electronics and more: http://www.youtube.com/user/frankbussArticle: 154098
In an answer to my own question: take a look at the xilinx XDL tool.Article: 154099
7 Haziran 2010 Pazartesi 16:12:22 UTC+3 tarihinde izaak yazd=C4=B1: > I use an internal memory Spartan 3an > When I try to burn only the FPGA I can! > Even when I try to burn the FPGA and the prom > I get in the middle of the recording process failed! > And the reason he failed is: > "'1': Configuration data download to FPGA was not successful. DONE did no= t > go high, please check your configuration setup and spi mode settings. > PROGRESS_END - End Operation." >=20 > Would love to get any help > Thanks! >=20 > =20 > =09 > --------------------------------------- =09 > Posted through http://www.FPGARelated.com Hi Izaak, I'm experiencing exactly the same problem with you. I could not find a solu= tion yet. Did you find the source of the problem and any solution?=20 I would appreciate if you can help. Thanks. Serkan.
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