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On Aug 29, 5:14=A0pm, Sharath Raju <brshar...@gmail.com> wrote: > Hello everyone, > > We are building a board in which we propose to design the FPGA > interface to a DAC in the following manner. Please give feedback > whether such an approach is feasible. > > Functionality: > Among other things, the board contains three components: ADC, DAC and > FPGA (XC3SD1800A, Spartan 3ADSP 1.8 million gates). The ADC & DAC are > connected to the FPGA. The ADC, DAC and FPGA are all clocked at 250 > MHz from an external clock source. To test whether ADC, DAC & FPGA are > working fine, we propose to use the FPGA as a pipe from the ADC to the > DAC. In this way, the output of the DAC should resemble the analog > input. > > The question is this: > Assuming the clock is routed on the PCB such that there is no phase > delay between the ADC, DAC and the FPGA, can the data output by the > FPGA be delayed by say half a clock cycle in order to satisfy the > setup & hold consideration of the DAC. The trouble is we cannot use a > DCM to phase-delay the clock inside the FPGA because the jitter- > performance of the DCM is very poor compared to the input clock. > Instead, can we use timing contraints to achieve the phase delay ? > > Thanks, > Sharath The IOBs tend to have delay elements built in. But you may not be giving the DCM enough credit. You want your clock to be pure feeding both the DAC and ADC. But a phase-shifted internal clock can provide the needed setup and hold for the data from the ADC and the appropriate clock-to-out valid window for the DAC. Some high speed ADCs are even designed to forward a regenerated (or appropriately delayed) clock along with the data to the FPGA. If you use a DCM in your clock path with timing constraints for OFFSET IN and OFFSET OUT constraints, you should have less pushback from the tools. Without that help, the clock-to-out timing becomes a bit too difficult to tie down to the proper window in a 4ns period in most FPGA families.Article: 148826
On Sun, 29 Aug 2010 14:14:21 -0700 (PDT), Sharath Raju <brsharath@gmail.com> wrote: >Hello everyone, > >We are building a board in which we propose to design the FPGA >interface to a DAC in the following manner. Please give feedback >whether such an approach is feasible. >The question is this: >Assuming the clock is routed on the PCB such that there is no phase >delay between the ADC, DAC and the FPGA, can the data output by the >FPGA be delayed by say half a clock cycle ... >Instead, can we use timing contraints to achieve the phase delay ? Probably not, but you can certainly clock the output data from the opposite clock edge. Alternatively, set the internal clock phase using the DCM to give the outputs the best timing window, and look at IOB delays (IOBDELAY constraint, or IDELAY blocks, depending on device family - I can't remember what the S3ADSP gives you) to control the input timing. - BrianArticle: 148827
If you place output FFs into IOBs you should have no problem meeting DAC's setup/hold requirements. If you still do, consider making the clock trace longer on PCB or using a clock distribution chip with a programmable delay such as e.g. AD9510. Finally, some of the modern high-speed DACs can automatically adjust their sampling time of the input data internally. /MikhailArticle: 148828
What are your latency requirements? Syms.Article: 148829
Hi! Xilinx changed BRAM initialization process in EDK 12.2. There is no system_conf configuration. Now EDK use mem-files to init BRAMs. In my project they are filled with data, but in Modelsim or Isim my software do not executes by CPU(PPC). What is wrong? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148830
I thought that the Series 7 devices would be available in Q1 2011 but have recently heard they'll be badly delayed until at least Q3. Does anyone else have any information as to when I'll be able to actually buy these parts? Thanks.Article: 148831
hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a simulation using simple testbench that sends 0,1,2,...63 as the input parameters. The dct_out(output signal) never sends out any result and it always xxxxxx. From the initial basic understanding of the code, the reading the writing of local memory seems done incorrectly. Also the original code has some compilation errors which is given below. Some of the reg needed to be converted to wires to compile. It didn't not seem to alter the functionality. Error (10663): Verilog HDL Port Connection error at dct.v(88): output or inout port "result" must be connected to a structural net expression. Is this IP tested and verified? Thanks regards ShakithArticle: 148832
Shakes <shakith.fernando@gmail.com> wrote: > I downloaded the DCT verilog module from the altera website. > http://www.altera.com/support/examples/verilog/ver_dct.html > I ran a simulation using simple testbench that sends 0,1,2,...63 as > the input parameters. The dct_out(output signal) never sends out any > result and it always xxxxxx. From the initial basic understanding of > the code, the reading the writing of local memory seems done > incorrectly. I think you can do DCT as a systolic array. I didn't look at the web site to see if that is what it is doing, though. -- glenArticle: 148833
On Aug 31, 9:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote:
>
> Is this IP tested and verified?
>
From the readme file...
Contacting Altera
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Although we have made every effort to ensure that this design example
works
correctly, there might be problems that we have not encountered. If
you have
a question or problem that is not answered by the information provided
in this
readme file or the example's documentation, please contact your Altera
Field
Applications Engineer.
If you have additional questions that are not answered in the
documentation
provided with this function, please contact Altera Applications:
World-Wide Web: http://www.altera.com
http://www.altera.com/mysupport/
Technical Support Hotline: (800) 800-EPLD (U.S.)
(408) 544-7000 (Internationally)
Article: 148834Hi all I am a 52 years old electronics technician with massive experience in analog electronics like audio and power supplies . I want to start a career in FPGA designing . My intention is to buy a good book and a good FPGA evaluation board and to do some projects on it to get experience . I did some work in VHDL in the past . My question is do I have a real chance to get into this field now at my age ? Thanks ECArticle: 148835
I think you should forget about the 7 devices for the moment, after all the Spartan/Virtex 6 devices are only just becoming available. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148836
On Aug 31, 7:07=A0pm, "Roger" <rogerwil...@hotmail.com> wrote: > I thought that the Series 7 devices would be available in Q1 2011 but hav= e > recently heard they'll be badly delayed until at least Q3. Does anyone el= se > have any information as to when I'll be able to actually buy these parts? > > Thanks. I was told that limited production would be available starting Q2 '11, meaning probably only one of each of families. I don't think full production will be until 2012, which isn't too far off what you've heard.Article: 148837
>Hi all >I am a 52 years old electronics technician with massive experience in >analog electronics like audio and power supplies . > >I want to start a career in FPGA designing . > Seriously, I would think that RF was a better bet for you if you want to increase your earnings/hour. BTW, are you UK based, or elsewhere in Europe? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148838
Xilinx Guru Austin Lesea penned a great tutorial on timing constraints in the latest issue of Xcell Journal. Here is a link to the flash version http://cde.cerosmedia.com/1G4c56e6f64dfe8012.cde/page/46. You can also download the pdf of the entire issue at http://www.xilinx.com/publications/archives/xcell/Xcell72.pdf. Austin's piece is on page 46.Article: 148839
I have a problem with an automated testbench in ModelSim/QuestaSim. I run a TCL script which invokes another script using the DO command. In the other script, I use both SWITCH and SHIFT commands to examine arguments the second script has been called with. After some modifications of the scripts, I started to experience problems: my verification software hangs or crashes - always in the same place in the TCL code, namely, the 13th (sic!) SHIFT operation fails. Meanwhile, a file is generated with something I believe is the call stack. Its contents can be viewed here: http://tl.gd/3ehhma I thought my software installation is corrupted or something, but I tried to run the simulation on another computer with a different version of the software installed, and I observed the same behaviour. What's wrong? Is this my script or a bug common to many software distributions? Any suggestions and help will be appreciated. MRArticle: 148840
RealInfo wrote: > I am a 52 years old electronics technician with massive experience in > analog electronics like audio and power supplies . > My question is do I have a real chance to get into this field now > at my age ? Depends on how deep you want to go but, sure, I did and I started at a later age than yours. I had so much fun that I started a hobby company based on it. Check out Demand Peripherals. Bob SmithArticle: 148841
>I have a problem with an automated testbench in ModelSim/QuestaSim. I >run a TCL script which invokes another script using the DO command. In >the other script, I use both SWITCH and SHIFT commands to examine >arguments the second script has been called with. After some >modifications of the scripts, I started to experience problems: my >verification software hangs or crashes - always in the same place in >the TCL code, namely, the 13th (sic!) SHIFT operation fails. >Meanwhile, a file is generated with something I believe is the call >stack. Its contents can be viewed here: http://tl.gd/3ehhma > >I thought my software installation is corrupted or something, but I >tried to run the simulation on another computer with a different >version of the software installed, and I observed the same behaviour. >What's wrong? Is this my script or a bug common to many software >distributions? > >Any suggestions and help will be appreciated. > >MR > The effect of the 'do' command seems to be to execute the contents of the target script in the current context. This is usually OK. However, sometimes this has odd effects, especially when returning, perhaps as you are observing. Using the standard Tcl 'source' command executes the script in a child context, which means that it returns cleanly. Try and see if it helps. Cheers! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148842
"Roger" <rogerwilson@hotmail.com> wrote in message news:xJ6dnegOHO-rFuDRnZ2dnUVZ8rOdnZ2d@brightview.co.uk... > I thought that the Series 7 devices would be available in Q1 2011 but have > recently heard they'll be badly delayed until at least Q3. Does anyone > else have any information as to when I'll be able to actually buy these > parts? > > Thanks. Thanks for the feedback. It's certainly depressing given all the hype surrounding Series 7. It sounds to me like they've had some problems with the design or manufacture. Rog.Article: 148843
On 09/02/2010 05:20 AM, Roger wrote: > > > "Roger" <rogerwilson@hotmail.com> wrote in message > news:xJ6dnegOHO-rFuDRnZ2dnUVZ8rOdnZ2d@brightview.co.uk... >> I thought that the Series 7 devices would be available in Q1 2011 but >> have recently heard they'll be badly delayed until at least Q3. Does >> anyone else have any information as to when I'll be able to actually >> buy these parts? >> >> Thanks. > > Thanks for the feedback. It's certainly depressing given all the hype > surrounding Series 7. It sounds to me like they've had some problems > with the design or manufacture. > > Rog. It sounds to me like this is par for the course.Article: 148844
If you are determined and patient enough and most importantly you want to learn I don't see why you can't make a move into this area. There is still a bias against taking on the older worker with limited experience so I don't think it will be an easy move. There will be a lot of rejections probably along the way. Your analogue background can be useful in understanding issues particularly at board level. Most young graduates these days don't think beyond '0' and '1' if they even think at as low a level as that. That's something you might be able to use as an advantage in gaining a position. Combining with some board level analogue electronics might also get you a way in as an all- rounder. That way an employer gets some immediate benefit but you get a path to experience. Starting on your own is a good idea to see that you like doing the work and can make the transition. If you want to go further and do something like a masters or other qualification that may also help but is costly to do. John Adair Enterpoint Ltd. On 1 Sep, 09:52, RealInfo <therighti...@gmail.com> wrote: > Hi all > I am a 52 years old electronics technician with massive experience in > analog electronics like audio and power supplies . > > I want to start a career in FPGA designing . > > My intention is to buy a good book and a good FPGA > evaluation board and to do some projects on it to > get experience . > > I did some work in VHDL in the past . > > My question is do I have a real chance to get into this field now > at my age ? > > Thanks > ECArticle: 148845
On Thu, 02 Sep 2010 03:24:32 -0500, "RCIngham" wrote: >Using the standard Tcl 'source' command executes the script in a child >context, which means that it returns cleanly. For extra credit, discover and explain why that statement is almost completely untrue. -- Jonathan BromleyArticle: 148846
On Wed, 1 Sep 2010 12:18:25 -0700 (PDT), Marcin Rodzik
<marteno_rodia@o2.pl> wrote:
>I have a problem with an automated testbench in ModelSim/QuestaSim. I
>run a TCL script which invokes another script using the DO command. In
>the other script, I use both SWITCH and SHIFT commands to examine
>arguments the second script has been called with. After some
>modifications of the scripts, I started to experience problems: my
>verification software hangs or crashes - always in the same place in
>the TCL code, namely, the 13th (sic!) SHIFT operation fails.
>Meanwhile, a file is generated with something I believe is the call
>stack. Its contents can be viewed here: http://tl.gd/3ehhma
I don't much like the [shift] command (it's a ModelSim special,
not part of standard Tcl) but I just tried a sample with over 20
arguments and it worked just fine, so I'm guessing it's some
other problem. It's hard to know what happened from that
stack trace, but at a guess I'd suggest that you are somehow
restarting the simulation (or re-entering some kind of debug
behaviour) from within a breakpoint.
One useful trick is to display the current Tcl nesting
depth, using
echo "Tcl nesting = [info level]"
perhaps each trip round a main loop, or something like that.
This will certainly tell you if you have a Tcl execution
stack overflow, but it won't help if the problem is
re-entrant calls to the simulator.
Check out the [resume], [onbreak] and [abort] commands,
too. And make sure you are returning cleanly from any
scripts you execute during a breakpoint.
Another useful trick is to trace your [do] commands,
so you can see exactly what arguments they were called with.
Execute this script using [source] or [do]:
proc trace_my_do_commands {commandstring operation} {
echo "---tracing <$operation> $commandstring"
}
proc cancel_do_tracing {} {
foreach inf [trace info execution do] {
trace remove execution do [lindex $inf 0] [lindex $inf 1]
}
}
proc start_do_tracing {} {
trace add execution do enter trace_my_do_commands
}
Now, after you issue the command
start_do_tracing
every time you (or one of your scripts) executes any [do]
command, it will be displayed in full just before it's run.
If you weary of all the output, you can suppress the trace
with your new command
cancel_do_tracing
Hope this gives you some ideas.
--
Jonathan Bromley
Article: 148847On Aug 31, 6:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote: <snippage> > Some of the reg needed to be converted to wires to compile. > Is this IP tested and verified? The statement above answers the question (above). How much testing would you expect to be completed on a module that doesn't compile? RKArticle: 148848
"Roger" <rogerwilson@hotmail.com> wrote in message news:xJ6dnegOHO-rFuDRnZ2dnUVZ8rOdnZ2d@brightview.co.uk... > I thought that the Series 7 devices would be available in Q1 2011 but have > recently heard they'll be badly delayed until at least Q3. Does anyone > else have any information as to when I'll be able to actually buy these > parts? > > Thanks. Is there anyone from Xilinx who can put the record straight on this subject for us all please? Rog.Article: 148849
On Sep 1, 9:52=A0am, RealInfo <therighti...@gmail.com> wrote: > My question is do I have a real chance to get into this field now > at my age ? Can't say, but... > My intention is to buy a good book and a good FPGA > evaluation board and to do some projects on it to > get experience . > EC I came on this news group and asked for some advice getting started a couple of weeks ago and got some really good tips. I ended up buying "FPGA Prototyping by Verilog Examples" by Pong P. Chum there is a VHDL version of the book too. Its a good read and I am finding it to be a very well structured book to learn from too so I will pass that recommendation on to you. I come from a purely software background.
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