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On Aug 9, 7:16=A0pm, "ColdStart" <teslashock@n_o_s_p_a_m.msn.com> wrote: > Hello, > > Well my code is huge... but the interesting part is.. lets say i have som= e > 10 bit wide signal, and in my logic i clear it when it reaches value 768. > > Actually its not just signal, its a D flip-flop with a controlling mux, a= nd > i load new value or clear it using the Mux... > > When i was running and synthesizing this code in ISE 9.1 my logic was jus= t > fine... but now, with version 10.1 it compiles and synthesizes good... bu= t > during debug...i noticed that when that signal reaches value 13... it > suddenly goes to 0... > > (actually it is my FSM which checks if its 768, the through the mux clear= es > it...and starts whole thing again...) > > But now, its NOT MY FSM who cleares it before 768...its reset by itself!.= .. > very weird... any ideas? > > p.s. im running same code which compiled and worked well from previous > version, without any changes... > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Have you reviewed all of the WARNING messages from the synthesizer? Which ISE version did you move to from 9.1? Ed McGettigan -- Xilinx Inc.Article: 148626
Hi, On 9 Aug., 21:16, Kolja Sulimma <ksuli...@googlemail.com> wrote: > XST honors the initialization values during synthesis and I expect > other tools to do the same. You either limit the number of tools you are using to a small degree or expecting in vain. Nevertheless using initialisations in signal declaration is sometimes necessary but is more likely masking design errors during simulation. So I suggest to use them not without justification. bye ThomasArticle: 148627
Hi, I'm working on a Xilinx FPGA design (VHDL) that uses a top level generic, and need to build multiple versions of the FPGA where the generic is the only thing that changes. The generic is used to select different modules to be used in the FPGA, the modules can't all fit in the FPGA together. Currently there are 4 different settings for the generic, and for a release I need to build the FPGA with each of the different generic options. What I am looking for is advice on how to set up a script/makefile to generate the builds in parallel, whilst ensuring that the results are all kept separate. I'm using a Windows machine with a quad core processor. Thanks in advance Neill.Article: 148628
Hi Neill,
as you wrote, you need a script or Makefile which "generates" an xst
script file where options + generics are specified (-generics {a=3DBLA}).
Further the build script must call the needed build steps: xst,
ngdbuild, map, par, trce and bitgen. To do this for multiple builds,
just call your script with different parameters or so. Since you are
using windows, I would recommend the cygwin environment.=20
cheers
ben
On Tue, 2010-08-10 at 10:17 +0100, Neill Arnell wrote:=20
> Hi,
>=20
> I'm working on a Xilinx FPGA design (VHDL) that uses a top level=20
> generic, and need to build multiple versions of the FPGA where the=20
> generic is the only thing that changes. The generic is used to select=
=20
> different modules to be used in the FPGA, the modules can't all fit in=
=20
> the FPGA together.
>=20
> Currently there are 4 different settings for the generic, and for a=20
> release I need to build the FPGA with each of the different generic optio=
ns.
>=20
> What I am looking for is advice on how to set up a script/makefile to=20
> generate the builds in parallel, whilst ensuring that the results are=20
> all kept separate. I'm using a Windows machine with a quad core processo=
r.
>=20
> Thanks in advance
>=20
> Neill.
Article: 148629I have a design with too many global clocks which ISE automatically adds. Some of these clocks are slow and feed into relatively small areas of logic. Is there a way I can specify these clocks to be non-global?Article: 148630
Hi, try to use BUFR. cheers ben On Tue, 2010-08-10 at 13:15 +0100, Fredxx wrote:=20 > I have a design with too many global clocks which ISE automatically adds. >=20 > Some of these clocks are slow and feed into relatively small areas of log= ic. >=20 > Is there a way I can specify these clocks to be non-global? >=20 >=20Article: 148631
Benjamin Krill wrote: > On Tue, 2010-08-10 at 13:15 +0100, Fredxx wrote: >> I have a design with too many global clocks which ISE automatically >> adds. >> >> Some of these clocks are slow and feed into relatively small areas >> of logic. >> >> Is there a way I can specify these clocks to be non-global? > > Hi, > > try to use BUFR. > > cheers > ben > Many thanks. I thought all was going well until Translate. Unfortunately Spartan 3A's don't support the BUFR primitive!Article: 148632
> Many thanks. I thought all was going well until Translate. Unfortunatel= y=20 > Spartan 3A's don't support the BUFR primitive! Hm, to bad. Then you have to reduce your clocks and for example use clock enables for the slower logic parts.Article: 148633
On Aug 10, 5:17=A0am, Neill Arnell <nei...@pipstechnology.co.uk> wrote: > Hi, > > I'm working on a Xilinx FPGA design (VHDL) that uses a top level > generic, and need to build multiple versions of the FPGA where the > generic is the only thing that changes. =A0The generic is used to select > different modules to be used in the FPGA, the modules can't all fit in > the FPGA together. > > Currently there are 4 different settings for the generic, and for a > release I need to build the FPGA with each of the different generic optio= ns. > > What I am looking for is advice on how to set up a script/makefile to > generate the builds in parallel, whilst ensuring that the results are > all kept separate. =A0I'm using a Windows machine with a quad core proces= sor. > > Thanks in advance > > Neill. What I do is have a top level with no generics that defines values for all of the constants that will be generics and then instantiate the 'more general' one that has the generics. These can all be in the same file if you want. At the end of the day, you need to segregate these builds for purposes of synthesis, archiving, analysis and release. You can spend your time futzing with build scripts and then trying to keep it straight which build is which or spend it creating code that avoids any build script fanciness...your choice. KJArticle: 148634
On Aug 9, 10:50=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Aug 9, 10:16=A0pm, "ColdStart" <teslashock@n_o_s_p_a_m.msn.com> > wrote: > > > Hello, > > > Well my code is huge... but the interesting part is.. lets say i have s= ome > > 10 bit wide signal, and in my logic i clear it when it reaches value 76= 8. > > My reading of what you wrote is that you *asynchronously* clear the 10 > bits when those 10 bits happen to reach the value 768. =A0If that's the > case, then you're bound to have trouble. > > > Actually its not just signal, its a D flip-flop with a controlling mux,= and > > i load new value or clear it using the Mux... > > To many uses of the word 'it' and nobody will be clear about just what > 'it' is. =A0Less description and more posting of the actual code snippet > would be 10x more useful than what you're trying to describe. > > > When i was running and synthesizing this code in ISE 9.1 my logic was j= ust > > fine... but now, with version 10.1 it compiles and synthesizes good... = but > > during debug...i noticed that when that signal reaches value 13... it > > suddenly goes to 0... > > Not surprising at all if my first sentence regarding what I think > you're describing is correct. > > > (actually it is my FSM which checks if its 768, the through the mux cle= ares > > it...and starts whole thing again...) > > Starts what whole thing? > > > But now, its NOT MY FSM who cleares it before 768...its reset by itself= !... > > very weird... any ideas? > > 1. If the logic defining the behavior of the 10 bit thing causes that > 10 bit thing to be reset when it reaches a particular value, you've > got some rewriting of the code to do. > 2. Could be timing. =A0Have you: > =A0 =A0 - Setup the timing constraints and run static timing analysis? > Did it pass? > =A0 =A0 - Is there more than one clock domain in this design? > > > p.s. im running same code which compiled and worked well from previous > > version, without any changes... > > Some things to keep in mind... > - You can't debug a working system. =A0Don't waste time analyzing the > working system, focus on the non-working one as if you didn't know > about the older, working one. > - Sometimes things 'work' although they have latent design issues > still to be uncovered. =A0Whether you should consider yourself 'lucky' > that it was working or 'unfortunate' because you didn't uncover the > problem sooner is up to you to decide. > > Feel free to post some actual snippets of code that demonstrate what > you're saying that accurately represent what you're doing. (1) > > Kevin Jennings > > (1) An example of what I think you're describing (which would be a > problem if it is what you have is) > > process(clk, clear) > begin > =A0 if (clear =3D '1') then > =A0 =A0 big_sig <=3D (others =3D> '0'); > =A0 elsif rising_edge(clk) then > =A0 =A0 big_sig <=3D big_sig + 1; > =A0 end if; > end process; > > clear <=3D '1' when (big_sig =3D 768) else '0'; While I would agree that the above code is "broken" in the sense that you have a decoded output asynchronously resetting its source, I fail to see how it would have the symptom reported in the original post of resetting at value 13. 768 requires both high order bits to be high, which does not ever occur before state 768 in a normal up counter, glitches included. So if I saw the counter reset at state 13, I would suspect something else is horribly broken, perhaps my clock is not routed on a global resource, for example, causing the counter to have hold time errors. Automatic clock buffering is the sort of thing that can change between tool versions. Regards, GaborArticle: 148635
On Aug 10, 8:38=A0am, Benjamin Krill <b...@codiert.org> wrote: > > Many thanks. =A0I thought all was going well until Translate. =A0Unfort= unately > > Spartan 3A's don't support the BUFR primitive! > > Hm, to bad. Then you have to reduce your clocks and for example use clock > enables for the slower logic parts. I'll second the clock enables. A common techinique is to use a single clock for most of your logic and (through various mechanisms) generate clock enables at the appropriate rate where necessary. This also makes timing analysis much easier since everythign is carried on a single clock. ChrisArticle: 148636
On Aug 10, 8:38=A0am, Benjamin Krill <b...@codiert.org> wrote: > > Many thanks. =A0I thought all was going well until Translate. =A0Unfort= unately > > Spartan 3A's don't support the BUFR primitive! > > Hm, to bad. Then you have to reduce your clocks and for example use clock > enables for the slower logic parts. Some spartan 3A parts have left or right half clock regions. If the buffer for these is not called a BUFR there should be some other way to use it. Also for small regions it is possible to attach a constraint to the clock net (BUFFER_TYPE =3D NONE if I remember correctly) to remove the BUFG. Then you should add a USELOWSKEWNETS (IIRC) attribute and make sure your timing analysis includes hold time. If your clock is very slow, you can also play games to avoid hold time errors like always going from rising edge to falling edge. Regards, GaborArticle: 148637
On Aug 10, 10:02=A0am, Gabor <ga...@alacron.com> wrote: > So if I saw the counter reset at state > 13, I would suspect something else is horribly broken Which is why I also suggested checking timing. KJArticle: 148638
Gabor wrote: > On Aug 10, 8:38 am, Benjamin Krill <b...@codiert.org> wrote: >>> Many thanks. I thought all was going well until Translate. >>> Unfortunately Spartan 3A's don't support the BUFR primitive! >> >> Hm, to bad. Then you have to reduce your clocks and for example use >> clock enables for the slower logic parts. > > Some spartan 3A parts have left or right half clock regions. If the > buffer for these is not called a BUFR there should be some other > way to use it. > > Also for small regions it is possible to attach a constraint to > the clock net (BUFFER_TYPE = NONE if I remember correctly) > to remove the BUFG. Then you should add a USELOWSKEWNETS > (IIRC) attribute and make sure your timing analysis includes hold > time. If your clock is very slow, you can also play games to avoid > hold time errors like always going from rising edge to falling edge. > Many thanks. I used the attribute buffer_type = "none", but it seem to remove the offending clock altogether from the design. Not quite what I had intended. I then had a myraid more errors. In the end I resorted to removing the offending clocks and capture its edge with a high speed clock. All seemed well until Map when I got: FATAL_ERROR:3:xstphs.c:71:1.11.10.1 - Physical Synthesis Failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.Article: 148639
Whether initialized in the declaration or in a reset branch of a process, do it with ":= (others => '0');" ! This module has no feedback (within it), so initialization is likely not critical anyway (within it). When initialization is critical the initialization (or at least the end of initialization needs to be synchronized somehow. There are a multitude of different ways to accomplish it, and some of them are compatible with declaration initializations. AndyArticle: 148640
Same question. Does anybody know it? --- news://freenews.netfront.net/ - complaints: news@netfront.net ---Article: 148641
On 8/10/2010 4:24 PM, Xin Yang wrote: > Same question. Does anybody know it? > > --- news://freenews.netfront.net/ - complaints: news@netfront.net --- 113. Absolutely, without question. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148642
Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet. This is on a Spartan3a design which uses a DCM to multiply the incoming 25MHz clock up to 50MHz, then feeds it to another DCM which generates CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz clock. The 0deg clock is used to drive the CPU, SDRAM controller and other stuff, while the 90deg clock is used to drive the SDRAM itself. I've tried searching Xilinx's website for an "interactive datasheet" and found nothing. This INFO alert caught my interest because I'd like to get my design running a bit faster (66MHz would be nice, 75MHz or 100MHz even better, the SDRAM tops out at 133MHz). In theory a single-DCM design should be good to 133MHz (at least that's what the timing report says), but as soon as I add the frequency synth, the max frequency drops to 60MHz or so. Is there anything I can do to eek a bit more speed out of this thing? Thanks, -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 148643
On Aug 10, 8:43=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > Hi guys, > > Can anyone explain the following INFO alert I saw in my ISE build log? > > INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis > performance > =A0 =A0with the CLKFX and CLKFX180 outputs of the DCM comp > =A0 =A0clock_generator/DCM_SP_INST, consult the device Interactive Data S= heet. > > This is on a Spartan3a design which uses a DCM to multiply the incoming > 25MHz clock up to 50MHz, then feeds it to another DCM which generates > CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz > clock. The 0deg clock is used to drive the CPU, SDRAM controller and > other stuff, while the 90deg clock is used to drive the SDRAM itself. > > I've tried searching Xilinx's website for an "interactive datasheet" and > found nothing. This INFO alert caught my interest because I'd like to get > my design running a bit faster (66MHz would be nice, 75MHz or 100MHz even > better, the SDRAM tops out at 133MHz). > > In theory a single-DCM design should be good to 133MHz (at least that's > what the timing report says), but as soon as I add the frequency synth, > the max frequency drops to 60MHz or so. Is there anything I can do to eek > a bit more speed out of this thing? > > Thanks, > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ > If mail bounces, replace "10" with the last two digits of the current yea= r From your description, I assume that you have been using the CLK2X output of a DCM to go from 25MHz to 50MHz and then cascade that to another DCM to get the 0 and 90 degrees outputs, and now you want to use the CLKFX instead to go a bit faster. Is that correct? If so, you need to be aware that the CLKFX output of the DCM adds more jitter than any of the other outputs. I have not checked the S3A, but on the V4 the CLKFX adds too much jitter to use it as the input to another DCM. Check the S3A data sheet to see if that is the case for the S3A. Jitter adds root mean square, so if the CLKFX jiiter is too much, see if you can cascade two CLK2X DCM outputs and have less jitter. If so two CLK2X DCM outputs cascaded with a 1.5 CLKDV output would get you 66.66... MHz Regards, John McCaskill www.FasterTechnology.comArticle: 148644
On Aug 3, 6:03=A0pm, alpha <zhg....@gmail.com> wrote: > On Aug 3, 3:26 am, Frank van Eijkelenburg <fei.technolut...@gmail.com> > wrote: > > > > > On Aug 2, 5:28 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > > > Frank van Eijkelenburg <fei.technolut...@gmail.com> wrote: > > > > > I have a custom made PCIe board with a Virtex 5 FPGA on which I > > > > implemented aDMAunit which uses the PCIe endpoint block plus v1.14. > > > > I also implemented simple read/write operations from the PC to the > > > > board (the board responds with completion TLPs). The read/write > > > > operations are working,DMAis not working (transferring data from > > > > FPGA to PC). > > > > (snip) > > > > > When I start aDMAoperation by writing a register in the FPGA, I can > > > > see in chipscope the correct physical addresses in the TLP header (= of > > > > the memory write requests). However, I do not see the correct value= s > > > > in the allocated memory at the PC. What can I do to check where it = is > > > > going wrong? > > > > Not having tried to doDMAthrough PCI before, is data being > > > written, but the wrong data? > > > That is what I do not know. Yes the correct data is send to the PC, > > but if I readout the memory the values are unchanged. > > > > I would try writing all zeros or all ones and see if those come > > > through fine. =A0It could be timing between the FPGA and PCI such > > > that the wrong data is being latched. > > > > Then try slightly less predictable data and see what gets through. > > > > -- glen > > > If it was timing, I expect the other way around also problems (which I > > don't have). Also single memory read/write requests send from the PC > > are working correctly. > > Does CPU caches get snooped whenDMAwrote into host memory? =A0If not, > then you may not see right data by normal read. Finally, I solved the problem. For those who want to learn from mistakes of others, here comes the cause of the problem: The packets which were transmitted to the pc were too large (more than the maximum payload size of the receiver). In that case, the packets are simply dropped (no errors). Of course I have to read the maximum payload size from the device control register in the PCI Express Capability structure. best regards, FrankArticle: 148645
On Jul 6, 12:12=A0pm, Michael S <already5cho...@yahoo.com> wrote: > On Jul 6, 11:00=A0am, Frank van Eijkelenburg > > <fei.technolut...@gmail.com> wrote: > > I hope to fix the problem before my vacation (only one day left :) > > Something, I most certainly DO NOT RECOMMEND for final solution, but > it could help to go to vacation in better mood. > Scrap all the schoolbook nice&complex WindowsDMAAPI stuff. Instead, > take your Irp->MdlAddress, do MmGetMdlPfnArray() and access physical > addresses directly. It's wrong, it's immoral but on simple x86/x64 PC > or on small dual-processor server it always work. > Just don't forget to bring back the officialDMAAPI when you are back > from vocation and have more time than a few hours. Finally, I solved the problem. For those who want to learn from mistakes of others, here comes the cause of the problem: The packets which were transmitted to the pc were too large (more than the maximum payload size of the receiver). In that case, the packets are simply dropped (no errors). Of course I have to read the maximum payload size from the device control register in the PCI Express Capability structure. best regards, FrankArticle: 148646
On Aug 10, 12:00=A0pm, "Fredxx" <fre...@spam.com> wrote: > Gabor wrote: > > On Aug 10, 8:38 am, Benjamin Krill <b...@codiert.org> wrote: > >>> Many thanks. I thought all was going well until Translate. > >>> Unfortunately Spartan 3A's don't support the BUFR primitive! > > >> Hm, to bad. Then you have to reduce your clocks and for example use > >> clock enables for the slower logic parts. > > > Some spartan 3A parts have left or right half clock regions. =A0If the > > buffer for these is not called a BUFR there should be some other > > way to use it. > > > Also for small regions it is possible to attach a constraint to > > the clock net (BUFFER_TYPE =3D NONE if I remember correctly) > > to remove the BUFG. =A0Then you should add a USELOWSKEWNETS > > (IIRC) attribute and make sure your timing analysis includes hold > > time. =A0If your clock is very slow, you can also play games to avoid > > hold time errors like always going from rising edge to falling edge. > > Many thanks. =A0I used the attribute buffer_type =3D "none", but it seem = to > remove the offending clock altogether from the design. =A0Not quite what = I had > intended. =A0I then had a myraid more errors. > > In the end I resorted to removing the offending clocks and capture its ed= ge > with a high speed clock. =A0All seemed well until Map when I got: > FATAL_ERROR:3:xstphs.c:71:1.11.10.1 - Physical Synthesis Failed. Process > will > =A0 =A0terminate. For technical support on this issue, please open a WebC= ase > with =A0 this project attached athttp://www.xilinx.com/support.- Hide quo= ted text - > > - Show quoted text - I can't comment on the error, but be careful with capturing clocks to create clock enables. Make sure your sampling clock is fast enough (Nyquist and then some at an absolute minimum, a couple times more if possible) - if necessary divide your to-be-sampled clock in a PLL and regenerate the higher rate once you sample the lower one. Make sure you run the to-be-sampled clock through a few FFs on the sampling clock for stability. And then make sure you do a good edge detect on the sampled clock. ChrisArticle: 148647
On Aug 11, 5:50=A0pm, Frank van Eijkelenburg <fei.technolut...@gmail.com> wrote: > > Finally, I solved the problem. For those who want to learn from > mistakes of others, here comes the cause of the problem: > > The packets which were transmitted to the pc were too large (more than > the maximum payload size of the receiver). In that case, the packets > are simply dropped (no errors). Of course I have to read the maximum > payload size from the device control register in the PCI Express > Capability structure. > > best regards, > > Frank Thanks for the interesting update, Frank. I never even thought in that direction. Last time we did PCIe on FPGA we used Altera core with Avalon-MM wrapper. This configuration doesn't support outstanding packets that are longer than 256 bytes so, obviously, we were immune to maximum payload size trap.Article: 148648
On Tue, 10 Aug 2010 19:58:35 -0700, John McCaskill wrote: > From your description, I assume that you have been using the CLK2X > output of a DCM to go from 25MHz to 50MHz and then cascade that to > another DCM to get the 0 and 90 degrees outputs, and now you want to use > the CLKFX instead to go a bit faster. Is that correct? Sorry -- I should have been more clear about this. I'm using the first DCM's CLKFX output to drive the second DCM's clock input, then the main control logic gets CLK0 from DCM#2, and the SDRAM gets CLK90 from DCM#2. The best clock rate I've managed to get out of it is CLK0 = 50MHz, and the timing report says the best I should expect is about 63MHz. I'd just like to get that up to around 75MHz or so... > I have not checked the S3A, but on the V4 the CLKFX adds too much jitter > to use it as the input to another DCM. Check the S3A data sheet to see > if that is the case for the S3A. Ah -- I didn't realise that; I'll check the datasheet. Is there an explicit statement in the V4 datasheet about this, or just a subtle note buried in a data table? > Jitter adds root mean square, so if > the CLKFX jiiter is too much, see if you can cascade two CLK2X DCM > outputs and have less jitter. If so two CLK2X DCM outputs cascaded with > a 1.5 CLKDV output would get you 66.66... MHz Thanks for the suggestion -- I'll try that when I get a few minutes. At the moment I'm trying to graft my new SDRAM controller core onto my Latticemico32 SoC (and not having much success). -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 148649
Phil, what board are you using? Cant you just swap the oscillator for a faster one? Jon --------------------------------------- Posted through http://www.FPGARelated.com
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