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I have a custom 8051 RTL core that I want to put into a CPLD
on a development board.
I also need an external Flash/EEProm memory on the same
CPLD development board to run 8051 code from.
Are there any CPLD EVM/development boards that come with
an 8 bit with Flash/EEProm ?
If not I, I will have to attach a socket(for the EEProm), to an
existing
CPLD board.
thanks,
-steve
Article: 148676On 8/17/2010 8:08 AM, stevem1 wrote: > I have a custom 8051 RTL core that I want to put into a CPLD > on a development board. > > I also need an external Flash/EEProm memory on the same > CPLD development board to run 8051 code from. > > Are there any CPLD EVM/development boards that come with > an 8 bit with Flash/EEProm ? > > If not I, I will have to attach a socket(for the EEProm), to an > existing > CPLD board. > > thanks, > -steve How many macrocells are you going to need? An 8051 is a non-trivial amount of logic. Meanwhile, I think that both the Altera MAX II and the Lattice MachXO have on-chip flash that will do what you want, so you don't need to worry about a separate chip on the EVM. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148677
Hello, I have been trying to implement the SDK example
(http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/edk_ctt.pdf)
into my Avnet Virtex 5 FXT Eval Kit... but the program gives an error...
/*************************************************************
* This program drives the LEDs using the custom circuit. *
*************************************************************/
#include "xparameters.h"
#include "mb_interface.h"
#include "stdio.h"
#include "xutil.h"
#include "stdlib.h"
int main() {
int offset = 0;
int *addr_ptr;
char keyboard;
int LED_value = 0;
int status;
int reg_value;
int all_off_value;
int run_value;
int linear_value;
while(1) {
/* Print initialization message, and prompt for user input. */
xil_printf ("*********************************************\r\n");
xil_printf ("* --> Hyperterm window must be selected <-- *\r\n");
xil_printf ("* *\r\n");
xil_printf ("* Enter value and Carriage Return *\r\n");
xil_printf ("* Enter 0 to read status *\r\n");
xil_printf ("* Enter 1 for LEDs off. *\r\n");
xil_printf ("* Enter 2 for LEDs on. *\r\n");
xil_printf ("* Enter 3 for Log scale. *\r\n");
xil_printf ("* Enter 4 for Linear scale. *\r\n");
xil_printf ("* Enter 5 for Constant value. *\r\n");
xil_printf ("* Enter 6 to exit program. *\r\n");
xil_printf ("*********************************************\r\r\n");
/* Read the keyboard, print the entry. */
keyboard = XUartLite_RecvByte(XPAR_RS232_UART_1_BASEADDR);
xil_printf ("%c \r\r\n", keyboard);
/* Perform requested action. */
switch ( keyboard ) {
case '0': { /* Print the status as read from the circuit */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR;
status = *addr_ptr;
reg_value = (status & 0x0000ff00) >> 8;
all_off_value = (status & 0x00000008) >> 3;
run_value = (status & 0x00000004) >> 2;
linear_value = (status & 0x00000003);
xil_printf ("Raw status read = %x \r\n", status);
xil_printf ("Register value = %d \r\n", reg_value);
xil_printf ("All_off value = %d \r\n", all_off_value);
xil_printf ("Run value = %d \r\n", run_value);
xil_printf ("Linear value = %d \r\r\n", linear_value); }
break;
case '1': { /* Turn off LEDs */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR;
*addr_ptr = 0x00000000; }
break;
case '2': { /* Turn on LEDs */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR + 4;
*addr_ptr = 0x00000000; }
break;
case '3': { /* Use log drive for LEDs */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR + 8;
*addr_ptr = 0x00000000; }
break;
case '4': { /* Use linear drive for LEDs */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR + 12;
*addr_ptr = 0x00000000; }
break;
case '5': { /* Drive LEDs with register value */
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR + 16;
xil_printf ("* Enter LED intensity value (0 to 255) and CR:
*\r\n");
scanf ("%d", &LED_value);
if (LED_value > 255) LED_value = 255;
xil_printf ("%d \r\r\n", LED_value);
*addr_ptr = LED_value << 24; }
break;
case '6': /* Exit program */
xil_printf ("That was exciting, wasn't it? \r\r\n");
exit(0);
break;
default: {
addr_ptr = XPAR_PWM_LIGHTS_0_BASEADDR;
*addr_ptr = 0x00000000; }
break;
}
}
}
The error is:
Building file: ../led.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0
-I../../empty_application_bsp_0/microblaze_0/include -mxl-pattern-compare
-mcpu=v7.30.a -mno-xl-soft-mul -MMD -MP -MF"led.d" -MT"led.d" -o"led.o"
"../led.c"
./led.c: In function ‘main’:
./led.c:40: warning: implicit declaration of function
‘XUartLite_RecvByte’
./led.c:47: warning: assignment makes pointer from integer without a cast
./led.c:61: warning: assignment makes pointer from integer without a cast
./led.c:66: warning: assignment makes pointer from integer without a cast
./led.c:71: warning: assignment makes pointer from integer without a cast
./led.c:76: warning: assignment makes pointer from integer without a cast
./led.c:81: warning: assignment makes pointer from integer without a cast
./led.c:94: warning: assignment makes pointer from integer without a cast
./led.c:13: warning: unused variable ‘offset’
Finished building: ../led.c
Building target: LEDs.elf
Invoking: MicroBlaze gcc linker
mb-gcc
-L"C:\Xilinx\12.1\ISE_DS\EDK\gnu\microblaze\nt\microblaze-xilinx-elf\include"
-Wl,-T -Wl,../src/lscript.ld
-L../../empty_application_bsp_0/microblaze_0/lib -mxl-pattern-compare
-mcpu=v7.30.a -mno-xl-soft-mul -o"LEDs.elf" ./led.o -lstdio.h
/cygdrive/c/Xilinx/12.1/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld:
cannot find -lstdio.h
collect2: ld returned 1 exit status
make: *** [LEDs.elf] Error 1
Any help would be appreciated.
Thank you very much in advance.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148678Hi, I'm interested in learning more about FPGAs in a hands on way. Can anyone recommend an inexpensive set of tools to get started with? My wishlist is: I'd like to develop on Linux, I'd like to spend no more than a few hundred $ on a starter kit, I'd like to learn using the tools and up-to-date skills that are relevant to the more high end set ups available. Which is better to start with, Xilinx or Altera or something else? Is there a choice between Verilog and VHDL to be made, or can both be tried out just as easily? At the moment I am not too bothered about specific applications, just if I can get some hands on experience, whatever i/o ports are available on whatever board I use, I will think of some little project to try out using them. Thanks for your recommendations. RupertArticle: 148679
> How many macrocells are you going to need? =A0An 8051 is a non-trivial > amount of logic. > > Meanwhile, I think that both the Altera MAX II and the Lattice MachXO > have on-chip flash that will do what you want, so you don't need to > worry about a separate chip on the EVM. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order The custom 8051 is ~10-15K std 2-input gates. That's what we get when we put the 8051 RTL into an ASIC. But I want the 8051 programation to be ~permanent in the CPLD and then be able to access the external Flash/EEprom as the code memory for the 8051. We need many of these to give to customers for 8051 code development, but I don't want them affecting the 8051 core programmation. I just want them to be able to write code for the 8051 and put that code into an external Flash/EE, that they can program on a programmer. It sounds like I just need to put an EEporm socket on the CPLD board. -steveArticle: 148680
rupertlssmith@googlemail.com <rupertlssmith@googlemail.com> wrote: > I'm interested in learning more about FPGAs in a hands on way. Can > anyone recommend an inexpensive set of tools to get started with? My > wishlist is: I'd like to develop on Linux, I'd like to spend no more > than a few hundred $ on a starter kit, I'd like to learn using the > tools and up-to-date skills that are relevant to the more high end set > ups available. There are many starter kit boards available. Both X and A have free versions of the software to use with such boards (or separately). > Which is better to start with, Xilinx or Altera or something else? Both work, some use one some the other. > Is there a choice between Verilog and VHDL to be made, > or can both be tried out just as easily? If you have done digital logic design, even at the freshman level wiring up TTL chips, you shouldn't have too hard a time with either one. As was suggested to me and I still believe, C programmers should learn verilog, others might prefer VHDL. Not that there is any connection between the languages, or in the way there are used, but it is deeper than that. VHDL tends to be wordy, where the same idea in verilog takes much less writing. -- glenArticle: 148681
>On Mon, 16 Aug 2010 17:24:00 -0500, "hvo" wrote:
>
>>When initializing input/output signals in a multilevel VHDL design, is
it
>>"better" to initiate the values in the component declaration in the
>>toplevel? or the submodule entity declaration? Does it make a
difference?
>
>I guess you're talking about default values of input ports?
>
> entity widget is
> port (clk: in std_logic;
> mode: in std_logic = '0'; -- like this?
> count: out std_logic_vector);
>
>That is not an initialisation in the ordinary sense;
>it's a default value. It is used only if the port
>is unconnected when you instance the entity, and
>in that case the port acts as though it is permanently
>driven with the default value. If there's no default,
>an unconnected input port takes its "normal" default
>value ('U' for std_logic, -huge for integer, etc, etc).
>
>For synthesisable designs I generally agree with Mark
>and Mike that components are not worth the trouble,
>but if you do use components then you must be
>careful about these default input values, because
>you can get some slightly surprising results.
>
>If you insist on using components, my standard
>advice is to make the defaults the same on both
>entity and component. At the end of this post
>there's a long tedious ramble explaining why.
>
>In theory there are some interesting creative
>uses for defaults that differ between component
>and entity. In practice I've never found a
>situation where it was any use to me.
>
>Finally, a word of caution. Default input values
>are a pretty neat idea, but increasingly I choose
>never to use them. There is very little additional
>work in writing an explicit tie-off in the instance's
>port connection list, and I think that makes my intent
>much clearer. It also insulates me from the risk that
>some well-meaning goon will change the entity default
>in the future, and will fail to notice because all his
>own tests use explicit connection to the port.
>--
>Jonathan Bromley
>
Thanks for your explanation. I guess what most are saying is that
default/initial values are not necessary when the ports are being used
externally. For example the following is unecessary:
entity thing is
Port(
Clk : in std_logic := '0';
A : in std_logic := '0';
B : in std_logic := '0';
O : out std_logic := '0'
);
Only when a port is unconnected externally then you would give it a default
value, but in that case, it is better to explicitly write tie-off to avoid
confusions.
In a multiple component design, it is also unecessary to give each
component a default/initial value since it could introduce surprising
results.
Please let me know if I mis-interpreted anything.
Thanks
hv
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148682On 08/17/2010 10:07 AM, rupertlssmith@googlemail.com wrote: > Hi, > > I'm interested in learning more about FPGAs in a hands on way. Can > anyone recommend an inexpensive set of tools to get started with? My > wishlist is: I'd like to develop on Linux, I'd like to spend no more > than a few hundred $ on a starter kit, I'd like to learn using the > tools and up-to-date skills that are relevant to the more high end set > ups available. Which is better to start with, Xilinx or Altera or > something else? Is there a choice between Verilog and VHDL to be made, > or can both be tried out just as easily? > > At the moment I am not too bothered about specific applications, just > if I can get some hands on experience, whatever i/o ports are > available on whatever board I use, I will think of some little project > to try out using them. <Disclaimer> I'm not really an FPGA guy: I'm a systems engineer with formal training in math and analog circuits, who's been designing control and signal processing algorithms for FPGA, embedded processors and DSP chips for years. But while I've also implemented those algorithms on the processors, there have always been excellent digital folks on tap to implement my algorithms in FPGAs, and the projects have always been cutting-edge enough that no sensible person (including me) wanted a relative junior mucking about in the Verilog code. Since I've started my business I have done two projects: one (Verilog) because the customer knew me and I had just started freelancing, so I gave him a deep discount over my usual rate to learn FPGA stuff; the other (VHDL) because I developed a control algorithm for the customer, and when they saw how well it worked, how complex it was, and how busy they were they decided that it made sense for me to do the digital design for it. So I'm kind of a really, really good amateur at this. </Disclaimer> I just checked Xilinx development board prices on DigiKey -- they look pretty reasonable. For that matter, I have a Spartan 3 development board that I'd let go for a song -- but I wouldn't let you have the download cable, and that's over half the value of the thing at this point. You may want to check on eBay -- I bet there are obsolete devel boards there, too, for cheap. Xilinx ISE version 11.1 works fine on my installation of Ubuntu Lucid. I had to build the driver for the old parallel cable I had lying around from the last time that I did FPGA work, but my understanding is that this isn't such an issue with the new USB cables. Look to market share: I think Xilinx has the most parts out there, Altera second, and everyone else third. VHDL and Verilog are both about the same amount of effort to step up to, but they definitely have different flavors. Designer's use of VHDL or Verilog seems to vary by region -- Verilog came out of civilian practice and is big on the west coast*, VHDL came out of military practice (it intentionally inherits several features from ADA) and is big on the east coast. I have no clue what you'd find in Detroit or Austin (or London), etc.. So you may want to poll your local companies, to see what they use, and let that guide your choice of language to learn. Whichever one you use, keep in mind that the biggest thing you're doing is learning how to envision a physical logic implementation in your head, then write it out in textual form. That's going to be the same whether you do Verilog or VHDL (or SystemC); the language itself is just a means to do the final step, and isn't the most important part of the process. * In spite of living on the west coast I think I prefer VHDL -- I can certainly see that its easier to write well-structured code, even if my current effort is a snarled-up mess. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148683
Hi Andy, I thought I would wait to address your comments until after I checked the results in a couple of synthesis tools. Too busy to spend too much time fooling around, but I finally got to it. > The information on types and conversions in Jim's paper is very good. > > The recommendations for coding style (based on limitations of > synthesis tools) are a bit dated. Synth tools have come a long way in > 7 years. The paper's focus is on using numeric_std. Outside of showing how to use numeric_std and its overloading, there are only two recommendations and I note you (Andy) object to both. 1) Use integers primarily for literal values 2) Separate arithmetic objects from statemachines. It was pretty cool that the integer counters tested well in all of the synthesis tools I tried. However, I note that unsigned integers are currently limited to 31 bits, and signed integers are limited to 32 bits so from a coding perspective, this integers are not a complete solution. Instead, Integers are great for counters and small math problems and for all else one has to use numeric_std (and hence the relevancy of the paper). In addition, if one likes thinking in bits, this is much easier to do with signed and unsigned than with integers. > His recommendations for resource sharing and separation of computation > from state logic are unnecessary now; code it so you know WHAT it is > doing, and let the tool figure out HOW to do it. The second guideline, separate arithmetic objects from statemachines, is based as much on methodology as it is on historical tool issues. From a methodology perspective, collecting all arithmetic objects into a separate process and coding them allows one to focus more on the anticipated hardware architecture/ structure. This is important as it allows us to see the problem holistically and potentially implement an alternate, better hardware architecture. When a chip is big and fast enough, relative to the problem we are trying to solve, we do not need to worry as much about hardware architecture/ structure, but for many of us, I doubt that we are there yet. Best, JimArticle: 148684
Hi, I've recently started FPGA development after doing a little work with CPLDs in 2007. After much pondering, the set-up I plumped for the following, which should not be considered a direct recommendation: 1. Xilinx Spartan 3A-DSP board (HW-SD1800A-DSP-SB-UNI-G) Xilinx quote $600 for this, it set me back about 350 GBP in the UK. I chose it primarily because I'm working in a DSP environment. Other Spartan boards have more peripherals (keyboard support, USB, etc) but fewer on-chip resources for around the same price. Note that some boards have built-in USB programmers and others do not. This one doesn't. 2. "PC-3 clone" parallel port programmer. This was about 5 GBP from eBay and has the same schematic as Xilinx's (obsolete) PC-3 programmer. It needed electrical modifications to work with the development board's 2.5V JTAG interface. Nothing major -- just bypassing a diode here or there and changing capacitor values to allow sufficient rise time to the relatively high thresholds. It works pretty solidly now. Official programmers are very expensive, but faster and better supported. 3. Xilinx ISE Webpack This is a free and functional but somewhat crippled version of the ISE suite. I have posted recently about the lack of regard Xilinx apparently has for VHDL as a language and the workarounds and hacks that may be necessary. I can't recommend ISE but I've not used any alternatives. My own motivation was the Linux support which is, admittedly, quite good and apparently lacking in Altera's offerings. However, getting the programmer working required a third-party wrapper: http://groups.google.com/group/comp.arch.fpga/msg/2dfa36541174a4f2 To clarify, by "crippled" I mean that device support is generally limited to FPGAs found on pre-built demo boards. Also, the ISE simulator will artificially slow itself down on larger designs which I have found pretty annoying. 4. VHDL My choice of VHDL was historical. The VHDL/Verilog debate (flamewar) is covered thoroughly elsewhere. I came from a background of electronic hardware design and assembler/C programming and I'm of the opinion that VHDL's steeper learning curve is worth its subsequent flexibility. Software suites generally support both anyway. A hands-on approach is commendable but in my experience I'd had the board for a couple of weeks before I was happy enough with the simulations to start programming it. Factor this in if you begin to think about potential applications -- particularly if requirements may change during development. In any event, good luck! Andrew 0xADFArticle: 148685
On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), rupertlssmith@googlemail.com wrote: >I'm interested in learning more about FPGAs Wow. I think this thread reminds me why it's still kinda nice to hang out on comp.arch.fpga (and comp.lang.vhdl, .verilog). You get three seriously expert people, with distinctly different viewpoints and distinctly different positions, each giving a clearly expressed and nuanced take on a bunch of issues (X vs A, Verilog vs VHDL) that could so easily degenerate into a schoolyard scrap. And the OP gets spot-on advice too. Hard to beat. Thanks to all the contributors for their time and their generously shared expertise. -- Jonathan BromleyArticle: 148686
On Tue, 17 Aug 2010 12:28:25 -0500, "hvo" wrote: >In a multiple component design, it is also unecessary to give each >component a default/initial value since it could introduce surprising >results. That was not exactly what I intended to say. My point was that IF you use VHDL components then it is a good idea to ensure that any input port defaults are the same on a component as on the matching entity that will bind to it. If the component and the entity have different defaults, you may find the results are not quite what you expect. Most people use direct entity instantiation and do not use components, so the problem does not arise. Apologies if I was unclear earlier. Since this is a pure VHDL question, you are more likely to get good answers on comp.lang.vhdl. -- Jonathan BromleyArticle: 148687
On 08/17/2010 12:43 PM, Jonathan Bromley wrote: > On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), > rupertlssmith@googlemail.com wrote: > >> I'm interested in learning more about FPGAs > > Wow. I think this thread reminds me why it's still > kinda nice to hang out on comp.arch.fpga (and > comp.lang.vhdl, .verilog). > > You get three seriously expert people, with distinctly > different viewpoints and distinctly different positions, > each giving a clearly expressed and nuanced take on > a bunch of issues (X vs A, Verilog vs VHDL) that > could so easily degenerate into a schoolyard scrap. Schoolyard scrap? Oh dang -- I forgot that part! YOU'RE ALL WRONG -- EVEN THAT WESCOTT GUY! The _only_ language to use for HDL is SystemFourth! And the best logic to put it onto is mine, if only those dingbat venture capitalists would give me the time of day so I can start my company! So there. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148688
On 08/17/2010 12:50 PM, Tim Wescott wrote: > On 08/17/2010 12:43 PM, Jonathan Bromley wrote: >> On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), >> rupertlssmith@googlemail.com wrote: >> >>> I'm interested in learning more about FPGAs >> >> Wow. I think this thread reminds me why it's still >> kinda nice to hang out on comp.arch.fpga (and >> comp.lang.vhdl, .verilog). >> >> You get three seriously expert people, with distinctly >> different viewpoints and distinctly different positions, >> each giving a clearly expressed and nuanced take on >> a bunch of issues (X vs A, Verilog vs VHDL) that >> could so easily degenerate into a schoolyard scrap. > > Schoolyard scrap? Oh dang -- I forgot that part! > > YOU'RE ALL WRONG -- EVEN THAT WESCOTT GUY! > > The _only_ language to use for HDL is SystemFourth! And the best logic > to put it onto is mine, if only those dingbat venture capitalists would > give me the time of day so I can start my company! > > So there. SystemCOBAL if it's for a bank teller machine, of course. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148689
On 8/17/2010 10:07 AM, rupertlssmith@googlemail.com wrote: > I'm interested in learning more about FPGAs in a hands on way. Can > anyone recommend an inexpensive set of tools to get started with? My > wishlist is: I'd like to develop on Linux, I'd like to spend no more > than a few hundred $ on a starter kit, I'd like to learn using the > tools and up-to-date skills that are relevant to the more high end set > ups available. Which is better to start with, Xilinx or Altera or > something else? Is there a choice between Verilog and VHDL to be made, > or can both be tried out just as easily? https://www.altera.com/download/software/quartus-ii-we is free and now has a usable version of modelsim for vhdl and verilog. > At the moment I am not too bothered about specific applications, just > if I can get some hands on experience, whatever i/o ports are > available on whatever board I use, I will think of some little project > to try out using them. The quartus RTL viewer is an appropriate tool for learning to code RTL. The modelsim editor is good for learning vhdl and verilog syntax, even if you are not interested in simulation. -- Mike TreselerArticle: 148690
On Aug 17, 12:33=A0pm, "Rice"
<albertopv@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:
> Hello, I have been trying to implement the SDK example
> (http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/edk_c...=
)
> into my Avnet Virtex 5 FXT Eval Kit... but the program gives an error...
>
> /*************************************************************
> * This program drives the LEDs using the custom circuit. =A0 =A0 *
> *************************************************************/
>
> #include "xparameters.h"
> #include "mb_interface.h"
> #include "stdio.h"
> #include "xutil.h"
> #include "stdlib.h"
>
> int main() {
>
> =A0 int offset =3D 0;
> =A0 int *addr_ptr;
> =A0 char keyboard;
> =A0 int LED_value =3D 0;
> =A0 int status;
> =A0 int reg_value;
> =A0 int all_off_value;
> =A0 int run_value;
> =A0 int linear_value;
>
> =A0 while(1) {
>
> /* =A0Print initialization message, and prompt for user input. */
> =A0 xil_printf ("*********************************************\r\n");
> =A0 xil_printf ("* --> Hyperterm window must be selected <-- *\r\n");
> =A0 xil_printf ("* =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *\r\n");
> =A0 xil_printf ("* Enter value and Carriage Return =A0 =A0 =A0 =A0 =A0 *\=
r\n"); =A0 =A0
> =A0 xil_printf ("* Enter 0 to read status =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0*\r\n");
> =A0 xil_printf ("* Enter 1 for LEDs off. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 *\r\n");
> =A0 xil_printf ("* Enter 2 for LEDs on. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0*\r\n");
> =A0 xil_printf ("* Enter 3 for Log scale. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0*\r\n");
> =A0 xil_printf ("* Enter 4 for Linear scale. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 *\r\n");
> =A0 xil_printf ("* Enter 5 for Constant value. =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 *\r\n");
> =A0 xil_printf ("* Enter 6 to exit program. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0*\r\n");
> =A0 xil_printf ("*********************************************\r\r\n");
>
> /* Read the keyboard, print the entry. =A0*/ =A0
> =A0 keyboard =3D XUartLite_RecvByte(XPAR_RS232_UART_1_BASEADDR); =A0
> =A0 xil_printf ("%c \r\r\n", keyboard);
>
> =A0/* Perform requested action. */
> =A0 switch ( keyboard ) {
>
> =A0 =A0 =A0 =A0 case '0': { =A0 =A0/* Print the status as read from the c=
ircuit */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR;
> =A0 =A0 =A0 =A0 =A0 status =3D *addr_ptr;
> =A0 =A0 =A0 =A0 =A0 reg_value =3D (status & 0x0000ff00) >> 8;
> =A0 =A0 =A0 =A0 =A0 all_off_value =3D (status & 0x00000008) >> 3;
> =A0 =A0 =A0 =A0 =A0 run_value =3D (status & 0x00000004) >> 2;
> =A0 =A0 =A0 =A0 =A0 linear_value =3D (status & 0x00000003); =A0 =A0 =A0
> =A0 =A0 =A0 =A0 =A0 xil_printf ("Raw status read =3D %x \r\n", status);
> =A0 =A0 =A0 =A0 =A0 xil_printf ("Register value =A0=3D %d \r\n", reg_valu=
e); =A0 =A0 =A0 =A0
> =A0 =A0 =A0 =A0 =A0 xil_printf ("All_off value =A0 =3D %d \r\n", all_off_=
value); =A0 =A0
> =A0 =A0 =A0 =A0 =A0 xil_printf ("Run value =A0 =A0 =A0 =3D %d \r\n", run_=
value); =A0 =A0 =A0 =A0
> =A0 =A0 =A0 =A0 =A0 xil_printf ("Linear value =A0 =A0=3D %d \r\r\n", line=
ar_value); } =A0 =A0 =A0 =A0 =A0 =A0
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '1': { =A0 =A0/* Turn off LEDs */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR;
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D 0x00000000; }
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '2': { =A0 /* Turn on LEDs */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR + 4;
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D 0x00000000; }
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '3': { =A0 /* Use log drive for LEDs */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR + 8;
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D 0x00000000; }
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '4': { =A0 /* Use linear drive for LEDs */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR + 12;
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D 0x00000000; }
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '5': { =A0 /* Drive LEDs with register value */
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR + 16;
> =A0 =A0 =A0 =A0 =A0 xil_printf ("* Enter LED intensity value (0 to 255) a=
nd CR: =A0 =A0
> *\r\n");
> =A0 =A0 =A0 =A0 =A0 scanf ("%d", &LED_value);
> =A0 =A0 =A0 =A0 =A0 if (LED_value > 255) LED_value =3D 255;
> =A0 =A0 =A0 =A0 =A0 xil_printf ("%d \r\r\n", LED_value);
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D LED_value << 24; }
> =A0 =A0 =A0 =A0 =A0 break;
>
> =A0 =A0 =A0 =A0 case '6': =A0 /* Exit program */
> =A0 =A0 =A0 =A0 =A0 xil_printf ("That was exciting, wasn't it? \r\r\n");
> =A0 =A0 =A0 =A0 =A0 exit(0);
> =A0 =A0 =A0 =A0 =A0 break;
> =A0 =A0 =A0 =A0 default: {
> =A0 =A0 =A0 =A0 =A0 addr_ptr =3D XPAR_PWM_LIGHTS_0_BASEADDR;
> =A0 =A0 =A0 =A0 =A0 *addr_ptr =3D 0x00000000; } =A0 =A0 =A0
> =A0 =A0 =A0 =A0 =A0 break;
> =A0 =A0 } =A0
> =A0 }
>
> }
>
> The error is:
>
> Building file: ../led.c
> Invoking: MicroBlaze gcc compiler
> mb-gcc -Wall -O0 -g3 -c -fmessage-length=3D0
> -I../../empty_application_bsp_0/microblaze_0/include -mxl-pattern-compare
> -mcpu=3Dv7.30.a -mno-xl-soft-mul -MMD -MP -MF"led.d" -MT"led.d" -o"led.o"
> "../led.c"
> ./led.c: In function =91main=92:
> ./led.c:40: warning: implicit declaration of function
> =91XUartLite_RecvByte=92
> ./led.c:47: warning: assignment makes pointer from integer without a cast
> ./led.c:61: warning: assignment makes pointer from integer without a cast
> ./led.c:66: warning: assignment makes pointer from integer without a cast
> ./led.c:71: warning: assignment makes pointer from integer without a cast
> ./led.c:76: warning: assignment makes pointer from integer without a cast
> ./led.c:81: warning: assignment makes pointer from integer without a cast
> ./led.c:94: warning: assignment makes pointer from integer without a cast
> ./led.c:13: warning: unused variable =91offset=92
> Finished building: ../led.c
>
> Building target: LEDs.elf
> Invoking: MicroBlaze gcc linker
> mb-gcc
> -L"C:\Xilinx\12.1\ISE_DS\EDK\gnu\microblaze\nt\microblaze-xilinx-elf\incl=
ude"
> -Wl,-T -Wl,../src/lscript.ld
> -L../../empty_application_bsp_0/microblaze_0/lib -mxl-pattern-compare
> -mcpu=3Dv7.30.a -mno-xl-soft-mul -o"LEDs.elf" =A0./led.o =A0 -lstdio.h
> /cygdrive/c/Xilinx/12.1/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/micro=
blaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld:
> cannot find -lstdio.h
> collect2: ld returned 1 exit status
> make: *** [LEDs.elf] Error 1
>
> Any help would be appreciated.
>
> Thank you very much in advance. =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com
"cannot find -lstdio.h"
Looks like a syntax error in your make file. Maybe there should
be a space like -l stdio.h?
Article: 148691On Aug 10, 6:43=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > Hi guys, > > Can anyone explain the following INFO alert I saw in my ISE build log? > > INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis > performance > =A0 =A0with the CLKFX and CLKFX180 outputs of the DCM comp > =A0 =A0clock_generator/DCM_SP_INST, consult the device Interactive Data S= heet. > > This is on a Spartan3a design which uses a DCM to multiply the incoming > 25MHz clock up to 50MHz, then feeds it to another DCM which generates > CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz > clock. The 0deg clock is used to drive the CPU, SDRAM controller and > other stuff, while the 90deg clock is used to drive the SDRAM itself. I get this same exact warning on every design which uses the DCM's clock synthesizer (CLKFX) output in any Xilinx FPGA family. It shows up even when there is just one DCM, no cascading, nothing special. It's another example of Xilinx lossage. Open a WebCase and see if they can explain it to you! -aArticle: 148692
My makefile is the following: ################################################################################ # Automatically-generated file. Do not edit! ################################################################################ -include ../makefile.init RM := rm -rf # All of the sources participating in the build are defined here -include sources.mk -include subdir.mk -include objects.mk ifneq ($(MAKECMDGOALS),clean) ifneq ($(strip $(C_DEPS)),) -include $(C_DEPS) endif ifneq ($(strip $(S_UPPER_DEPS)),) -include $(S_UPPER_DEPS) endif endif -include ../makefile.defs # Add inputs and outputs from these tool invocations to the build variables ELFSIZE += \ LEDs.elf.size \ ELFCHECK += \ LEDs.elf.elfcheck \ # All Target all: LEDs.elf secondary-outputs # Tool invocations LEDs.elf: $(OBJS) $(USER_OBJS) @echo 'Building target: $@' @echo 'Invoking: MicroBlaze gcc linker' mb-gcc -L"C:\Xilinx\12.1\ISE_DS\EDK\gnu\microblaze\nt\microblaze-xilinx-elf\include" -Wl,-T -Wl,../src/lscript.ld -L../../empty_application_bsp_0/microblaze_0/lib -mxl-pattern-compare -mcpu=v7.30.a -mno-xl-soft-mul -o"LEDs.elf" $(OBJS) $(USER_OBJS) $(LIBS) @echo 'Finished building target: $@' @echo ' ' LEDs.elf.size: LEDs.elf @echo 'Invoking: MicroBlaze Print Size' mb-size LEDs.elf |tee "LEDs.elf.size" @echo 'Finished building: $@' @echo ' ' LEDs.elf.elfcheck: LEDs.elf @echo 'Invoking: Xilinx ELF Check' elfcheck LEDs.elf -hw ../../ledd/system.xml -pe microblaze_0 |tee "LEDs.elf.elfcheck" @echo 'Finished building: $@' @echo ' ' # Other Targets clean: -$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES)$(ELFSIZE)$(ELFCHECK)$(S_UPPER_DEPS) LEDs.elf -@echo ' ' secondary-outputs: $(ELFSIZE) $(ELFCHECK) .PHONY: all clean dependents .SECONDARY: -include ../makefile.targets There is not anything like -lstdio.h Is there any way of searching a word inside the whole project in order to locate the error? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148693
>On Tue, 17 Aug 2010 12:28:25 -0500, "hvo" wrote: > >>In a multiple component design, it is also unecessary to give each >>component a default/initial value since it could introduce surprising >>results. > >That was not exactly what I intended to say. > >My point was that IF you use VHDL components then it is a >good idea to ensure that any input port defaults are the >same on a component as on the matching entity that will >bind to it. If the component and the entity have >different defaults, you may find the results are >not quite what you expect. > >Most people use direct entity instantiation and do not use >components, so the problem does not arise. > >Apologies if I was unclear earlier. > >Since this is a pure VHDL question, you are more likely to >get good answers on comp.lang.vhdl. >-- >Jonathan Bromley > Thanks for the answer. I just wanted to establish a good rule of thumb to go by for setting the default values of IO signals. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148694
On 8/17/2010 1:07 PM, rupertlssmith@googlemail.com wrote: > Hi, > > I'm interested in learning more about FPGAs in a hands on way. Can > anyone recommend an inexpensive set of tools to get started with? My > wishlist is: I'd like to develop on Linux, I'd like to spend no more > than a few hundred $ on a starter kit, I'd like to learn using the > tools and up-to-date skills that are relevant to the more high end set > ups available. Which is better to start with, Xilinx or Altera or > something else? Is there a choice between Verilog and VHDL to be made, > or can both be tried out just as easily? > > At the moment I am not too bothered about specific applications, just > if I can get some hands on experience, whatever i/o ports are > available on whatever board I use, I will think of some little project > to try out using them. > > Thanks for your recommendations. > > Rupert I'm pretty much a novice when it comes to the actual coding, but I've been lurking around this group and looking into low end development kits for some time now. I'd say that you should take a good look at the Digilent web site (www.digilentinc.com), they specialize in entry level kits and actually designed more than one of the boards that have been offered by the big guys. The "Nexys 2" board, for example, is only $129 and could keep you busy with interesting projects for some time. And I think the associated "Digital Design" book is worth the extra $50 for a beginner. It starts out pretty slowly, but does get up to projects with modest complexity by the end. It's available in both Verilog and VHDL flavors. If you just want a minimum cost FPGA board with a bunch of I/O to play with (but less hand-holding) look at Enterpoint's Craignell modules (enterpoint.co.uk), Sparkfun's Break Out Board (www.sparkfun.com), OHO-Elektronik's GODIL boards (www.oho-elektronik.de), KNJN's Pluto boards (www.knjn.com), or terasIC's Max II Micro board (www.terasic.com.tw/en/). The terasIC and KNJN boards are Altera, the rest are Xilinx. The terasIC and the Nexys_2 are unique because they don't need a separate programmer (well KNJN only needs a serial adapter). In fact the terasIC board can even be used in place of an Altera programmer to configure other boards. Just some ideas for things to look at. Chris AbeleArticle: 148695
Hi,John.
Thanks for the solution. The world look better.
>On Aug 17, 2:57=A0am, "aaron123"
><Aaronsmagazine@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
>> Thanks,John. Your idea make things better , though it still need
generate
>> the CDC =A0by hand.
>>
>>
>>
>> >On Aug 13, 6:59=3DA0am, "aaron123"
<Aaronsmagazine@n_o_s_p_a_m.gmail.com=
>>
>> >wrote:
>> >> Hi,
>> >> =3DA0 =3DA0 I'am seeking a way to use VIO and core inserter at the
sam=
>e
>> time.=3D
>> > I
>> >> found that if I want to use VIO , I must also instantiating ILA. I
fee=
>l
>> >> it's awkward.
>> >> Please help me find a better way.Thanks.
>>
>> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0
>> >> Posted throughhttp://www.FPGARelated.com
>>
>> >While not quite what you want to do, a work around is to put the VIO
>> >and ILA in using the generator flow. Just hook the ILA up to anything
>> >convenient at the top level. =A0Go through place and route, and then
>> >open the design in FPGA editor. Under the tools menu is an entry for
>> >ILA. Select that, and you will get a pop up window that will allow you
>> >to reconnect the ILA to the signals you want. =A0Save the ncd, and
take
>> >it through PAR again.
>>
>> >Regards,
>>
>> >John McCaskill
>> >www.FasterTechnology.com
>>
>> --------------------------------------- =A0 =A0 =A0 =A0
>> Posted throughhttp://www.FPGARelated.com
>
>On the FPGA Editor ILA tool pop up window, there is a write CDC
>button. If after you make your changes, you press that it will write
>out a new CDC file for that LIA core for you.
>
>Regards,
>
>John McCaskill
>www.FasterTechnology.com
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148696On Aug 17, 8:43=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), > > rupertlssm...@googlemail.com wrote: > >I'm interested in learning more about FPGAs > > Wow. =A0I think this thread reminds me why it's still > kinda nice to hang out on comp.arch.fpga (and > comp.lang.vhdl, .verilog). > > You get three seriously expert people, with distinctly > different viewpoints and distinctly different positions, > each giving a clearly expressed and nuanced take on > a bunch of issues (X vs A, Verilog vs VHDL) that > could so easily degenerate into a schoolyard scrap. > > And the OP gets spot-on advice too. > > Hard to beat. =A0Thanks to all the contributors for > their time and their generously shared expertise. > -- > Jonathan Bromley Yes, some excellent advice, thanks very much. I hadn't really appreciated that I can download Xilinx ISE or Altera Quartus web editions for free and that both run on Linux. Also that I can run simulations of designs without having a chip to program them onto, so it looks like I can at least have a play around with the basics at no cost at all. Is a development environment like Xilinx ISE or Altera Quartus necessary? or are there standalone Verilog or VHDL compilers available that can be used? I'm a bit unclear as to the process of going from the source code to writing the design onto the chip. The development boards generally have an FPGA chip that is removable, and one removes it and inserts it into a 'programmer' to burn in the design? or is the FPGA chip fixed onto the dev board and gets programmed in place?Article: 148697
On Wed, 18 Aug 2010 01:38:00 -0700 (PDT) "rupertlssmith@googlemail.com" <rupertlssmith@googlemail.com> wrote: > On Aug 17, 8:43=C2=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> > wrote: > > On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), > > > > rupertlssm...@googlemail.com wrote: > > >I'm interested in learning more about FPGAs > > > > Wow. =C2=A0I think this thread reminds me why it's still > > kinda nice to hang out on comp.arch.fpga (and > > comp.lang.vhdl, .verilog). > > > > You get three seriously expert people, with distinctly > > different viewpoints and distinctly different positions, > > each giving a clearly expressed and nuanced take on > > a bunch of issues (X vs A, Verilog vs VHDL) that > > could so easily degenerate into a schoolyard scrap. > > > > And the OP gets spot-on advice too. > > > > Hard to beat. =C2=A0Thanks to all the contributors for > > their time and their generously shared expertise. > > -- > > Jonathan Bromley >=20 > Yes, some excellent advice, thanks very much. >=20 > I hadn't really appreciated that I can download Xilinx ISE or Altera > Quartus web editions for free and that both run on Linux. Also that I > can run simulations of designs without having a chip to program them > onto, so it looks like I can at least have a play around with the > basics at no cost at all. >=20 > Is a development environment like Xilinx ISE or Altera Quartus > necessary? or are there standalone Verilog or VHDL compilers available > that can be used? I'm a bit unclear as to the process of going from > the source code to writing the design onto the chip. The development > boards generally have an FPGA chip that is removable, and one removes > it and inserts it into a 'programmer' to burn in the design? or is the > FPGA chip fixed onto the dev board and gets programmed in place? I can only speak for Xilinx, as I've never used Altera. I do use the xilinx tools on linux exclusively, however.=20 The actual synthesis tools (xst, par, map, bitgen etc) can all be driven from the command line, or even better, Makefiles. There is no actual need to use the ISE environment, except possibly for simulations. And simulations are better and faster done by modelsim in any case, but that might cost money. There is also F/OSS simulation tools out there, but I have very limited experience with them. It might even be possible to Makefile up the ISE simulator, but I've never tried. Modelsim spoiled me. Our main projects are all straight Makefiles for building, but I have recently had to use the ISE for a smaller project. It works well enough for small code, especially since the GUI updates from 10.1 -> 12, but I would definitely bypass it if I didn't have to use it, as there is a lot of overhead I'm not using / have substitutes for.=20 //OscarArticle: 148698
[snip] > >Most people use direct entity instantiation and do not use >components, so the problem does not arise. > [snip] My experience is that most people DO use components, some in packages, and some not. I am trying to educate them to use direct entity instantiation... Few use port default values. I tend to avoid these for code that I intend to synthesize, but it is a useful feature for testbench models. Cheers! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148699
> If you just want a minimum cost FPGA board with a bunch of I/O to play > with (but less hand-holding) look at Enterpoint's Craignell modules > (enterpoint.co.uk), Sparkfun's Break Out Board (www.sparkfun.com), > OHO-Elektronik's GODIL boards (www.oho-elektronik.de), KNJN's Pluto > boards (www.knjn.com), or terasIC's Max II Micro board > (www.terasic.com.tw/en/). =A0The terasIC and KNJN boards are Altera, the > rest are Xilinx. =A0The terasIC and the Nexys_2 are unique because they > don't need a separate programmer (well KNJN only needs a serial > adapter). =A0In fact the terasIC board can even be used in place of an > Altera programmer to configure other boards. > > Just some ideas for things to look at. > > Chris Abele terasIC's MAX boards have CPLD, not FPGA.
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