Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Another thing, when the FPGA 2 gets programmed and i read its status register, it looks perfectly in accordance to a working FPGA's status word but it doesn't show any output. Is it possible that FPGA 2 never comes out of the startup sequunce ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148376
On 15 juil, 10:08, Nicolas Matringe <nic_o_...@msn.com> wrote: > Hello > I've been trying to download these 2.9GB for 3 days with numerous > retries (thanks to the download manager, the 'resume' resulted in a > restart from 0) and when I finally managed to get the full file it was > corrupted. I finally managed to get the full file in running order after another 6 hours download, now I'm installing it. NicoArticle: 148377
On 16 July, 11:42, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Another thing, when the FPGA 2 gets programmed and i read its status > register, it looks perfectly in accordance to a working FPGA's status wor= d > but it doesn't show any output. Is it possible that FPGA 2 never comes ou= t > of the startup sequunce ? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com On the face of it your having the same results as I had and it was all straightforward. An unprogrammed FPGA drives done low using open drain. When you program them they fail at the very last point " I am now programmed, I have released done but done is still low so I will not start working". All I did was programmed each FPGA using JTAG but only when you program the last FPGA does done go high and the FPGA starts. Done is now not being driven low by anything and programming any FPGA will make it work. Typing "done pin" at xilinx.com and selecting the first hit explains this fairly well. ColinArticle: 148378
On Jul 15, 9:28=A0am, rich12345 <aiiad...@gmail.com> wrote: > On Jul 15, 1:08=A0am, Nicolas Matringe <nic_o_...@msn.com> wrote: > > > Hello > > I've been trying to download these 2.9GB for 3 days with numerous > > retries (thanks to the download manager, the 'resume' resulted in a > > restart from 0) and when I finally managed to get the full file it was > > corrupted. > > I had the same problem. =A0I can't remember which browser wasn't working > (IExplorer or FireFox)..... =A0But when I switched to the other browser, > the download worked fine with the download manager. > > Rich I had similar results. My thought was that it was a Java problem - different browsers typically have different ways of dealing with embedded Java. RK.Article: 148379
Our third product based on Spartan-6 is Drigmorn4 http://www.enterpoint.co.uk/drigmorn/drigmorn4.html and it is now available in very limited quantities. It's very much of the same concept as Drigmorn3 but with the benefit of a bigger Spartan-6 FPGA - XC6SLX45 through to XC6SLX150. We also support bitstream encryption with FPGA's XC6SLX75-XC6SLXLX150. There is a better USB interface this time based on FT2232 and we have also added a CY22394 clock generator. The power supply capability have also been increased significantly and there is also a DC Jack now as an alternate power option. It also power off a USB cable for light-mid size/speed FPGA designs. We are hoping that this board will be available in bigger quantities in Sepetember-October timeframe but that does depend on the availability of Spartan-6. John Adair Enterpoint Ltd.Article: 148380
How do I assign an integer value to 'signed' or 'unsigned' from the IEEE libraries? I'm having this difficulty with my test benches. Surely there's a set of library functions to do it, but I can't seem to figure out what they are!! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148381
On Jul 15, 6:17=A0am, Gladys <yuhu...@gmail.com> wrote: > hi all, I want to implement a DDR2 SDRAM controller, as Xilinx > provides MIG =A0software tool to create IP core for the memory > interface, however I have some questions about the port configuration. > > I want to store up to 9 frames(3000H x 2748V) of image data into 1GB > DDR2 SDRAM(MT47H64M16), the frame size is resolution x bits/pixel =3D 10 > megapixels(3664H x 2748V) x 12bits/pixel =3D 15MB. > 3664 x 2748 x 12 x 9 =3D 1,087,416,576 bits. That won't quite fit into 1 gigabit or 1,073,741,824 bits. > In the prototyping, the address bits =3D 14, data bits=3D16, bank > address=3D3bits, I need asynchronous write and read from SDRAM: > > 1- How to choose Port Configuration among the 5 configurations? For > example:2 32bits Bidir + 4 32bits Unidir, 4 32bits Bidir, 2 64bits > Bidir, etc. > Is this the Spartan 6 memory controller? You need to select the size and number of ports based on your system requirements. How fast is the pixel data coming in? Is the readout required to run at the same rate or possibly even faster (as with image averaging).? > 2- How to choos the fruequency, in the datasheet, the max frequency > could be 333MHz, actually the master clock of FPGA is set to 25MHz, > what frequency for the SDRAM should be fine? > Again this depends on your required bandwidth. Obviously you can't run the memory faster than the chip allows (your part number should have a speed grage at the end like -5 or -3. you would need the -3 speed grade to run 333 MHz). On the other hand why waste extra power and make it harder to meet timing constraints if you don't really need to run effectively 1.33 gigabytes per second total memory bandwidth? > 3- Since each pixel has 12bits, the data bus is 16bits, How should the > storage perform, the extra 4 bits will be a waste, is it? > Not if you want to fit 9 frames in memory. You'll need to pack your data 4 pixels to every three words of memory, and even then there will not quire be enough unless you reduce the image size slightly. > 4- how are the frames stored? line by line, frame by frame, how to > seperate each line or each frame? > When you have extra memory to waste you can use nice binary powers to store lines and frames. In your case you don't have that luxury and will need to keep track of the starting address of each frame buffer and the line stride within the frame. > Thanks for your help! > > GladysArticle: 148382
On 7/16/2010 12:07 PM, Tim Wescott wrote: > How do I assign an integer value to 'signed' or 'unsigned' from the IEEE > libraries? > > I'm having this difficulty with my test benches. Surely there's a set of > library functions to do it, but I can't seem to figure out what they are!! > I'm assuming you're talking about numeric_std? TO_SIGNED(intval, width) and TO_UNSIGNED(intval, width) -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148383
On 07/16/2010 12:18 PM, Rob Gaddi wrote: > On 7/16/2010 12:07 PM, Tim Wescott wrote: >> How do I assign an integer value to 'signed' or 'unsigned' from the IEEE >> libraries? >> >> I'm having this difficulty with my test benches. Surely there's a set of >> library functions to do it, but I can't seem to figure out what they >> are!! >> > > I'm assuming you're talking about numeric_std? > > TO_SIGNED(intval, width) and TO_UNSIGNED(intval, width) > That worked. I seem to have a collision between libraries in my Xilinx ISE: declaring both of the following: USE ieee.numeric_std.ALL; use IEEE.STD_LOGIC_ARITH.ALL; gets me a flood of errors, although I seem to be able to comment out the std_logic_arith. I lack a good language/library reference*, or I'm stupidly not looking in the right place, else I'd be able to answer my questions by myself. * By definition -- because a good reference would answer the question. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148384
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d@web-ster.com... > I seem to have a collision between libraries in my Xilinx ISE: > > declaring both of the following: > > USE ieee.numeric_std.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > > gets me a flood of errors, although I seem to be able to comment out the > std_logic_arith. > These two libs should never be used together. The former is a standard library, which should be used in new code, and the latter is a legacy Synopsys library which might be required when working with the existing code. /MikhailArticle: 148385
On 07/16/2010 02:24 PM, MM wrote: > "Tim Wescott"<tim@seemywebsite.com> wrote in message > news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d@web-ster.com... >> I seem to have a collision between libraries in my Xilinx ISE: >> >> declaring both of the following: >> >> USE ieee.numeric_std.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> >> gets me a flood of errors, although I seem to be able to comment out the >> std_logic_arith. >> > > These two libs should never be used together. The former is a standard > library, which should be used in new code, and the latter is a legacy > Synopsys library which might be required when working with the existing > code. Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when you get lazy and tell it to just make you a test bench from a file. Thanks for the tip. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148386
On Jul 16, 3:01=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > On 07/16/2010 02:24 PM, MM wrote: > > > > > > > "Tim Wescott"<t...@seemywebsite.com> =A0wrote in message > >news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d@web-ster.com... > >> I seem to have a collision between libraries in my Xilinx ISE: > > >> declaring both of the following: > > >> USE ieee.numeric_std.ALL; > >> use IEEE.STD_LOGIC_ARITH.ALL; > > >> gets me a flood of errors, although I seem to be able to comment out t= he > >> std_logic_arith. > > > These two libs should never be used together. The former is a standard > > library, which should be used in new code, and the latter is a legacy > > Synopsys library which might be required when working with the existing > > code. > > Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when > you get lazy and tell it to just make you a test bench from a file. > > Thanks for the tip. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details athttp://www.wescottdesign.com/actfes/actfes.html- Hide quote= d text - > > - Show quoted text - It used to frustrate me no end the way ISE plugged in the wrong library, until I found the script that does it and CHANGED it. Look under Xilinx=3D>ISE=3D>data=3D>projnav=3D>scripts and modify file "dpm_sourceTasks.tcl" to your liking. TCL syntax is fairly basic in the area you'll want to change. delete: puts $hFile "use IEEE.STD_LOGIC_ARITH.ALL;" puts $hFile "use IEEE.STD_LOGIC_UNSIGNED.ALL;" add: puts $hFile "use ieee.numeric_std.all;" Customize to add your own name, company header, etc. Hopefully they haven't changed the framework in version 12. HTH, JohnArticle: 148387
On Fri, 16 Jul 2010 11:06:13 -0700, John Adair wrote: > Our third product based on Spartan-6 is Drigmorn4 > http://www.enterpoint.co.uk/drigmorn/drigmorn4.html and it is now > available in very limited quantities. I found this feature amusing: 4 sets of Traffic Lights (red, amber,green) are available to use Cheers, AllanArticle: 148388
Hi Tim, a good quick reference is the "Qualis Ref Card": http://www.google.de/url?sa=t&source=web&cd=1&ved=0CBwQFjAA&url=http%3A%2F%2Fwww.vhdl.org%2Frassp%2Fvhdl%2Fguidelines%2Fvhdlqrc.pdf&rct=j&q=qualis%20vhdl%20refcard&ei=qX1BTIHIN9ecOODYraQN&usg=AFQjCNFjtNN-k9EA-H4S1K1CZrW58cNRrQ or just type "qualis vhdl refcard" into the market hegemonial browser if the link above is bent over 17 lines. It's the first hit (at leas it was for me) Other references I use: - VHDL Spec from IEEE - Ashendon's Book Or what I usually do, power up the Aldec activeHDL simulator (you can get a free version from the Lattice website) and click on the Library manager. If you select the IEEE libraries and go to the "Package Contents" window you get the prototypes for all functions and procedures. This might of course work in modelsim too, I haven't tried. Regards, CharlesArticle: 148389
Hi again Tim, sorry, the reference card you are probably really looking for is under http://www.google.de/url?sa=t&source=web&cd=1&ved=0CBwQFjAA&url=http%3A%2F%2Fwww.vhdl.org%2Frassp%2Fvhdl%2Fguidelines%2F1164qrc.pdf&ei=_oBBTN7hKo2iOM6i7fAM&usg=AFQjCNHBm6d324gTZ40kvAWp6Lq0nB_5BQ (or "qualis packages refcard" in the previously mentioned hegemonial search engine) CharlesArticle: 148390
> I had similar results. =A0My thought was that it was a Java problem - > different browsers typically have different ways of dealing with > embedded Java. > > RK. If there is a such need, I could mirror the image somewhere.Article: 148391
On Wed, 14 Jul 2010 08:37:06 -0700, Jon wrote: > I believe I can supply the Micron chip. If you are interested in crosses > I will check it out and let you know. All parts are new in original > factory packaging. Please let me know if you have an interest and how > many you need. Unfortunately it's not really an option -- swapping the BGA RAM chip on all my DM2s is a bit beyond my capabilities (I've tried a few times with a hot-air soldering tool but never got a BGA off a board without ruining the board, the chip or both). At this point, I want to get the SDRAM controller working with this chip and this hardware... I'm starting to suspect an issue in my SDRAM controller's implementation of the WISHBONE bus WAIT state -- the read errors usually occur after the 9th address bit (A8) goes high. Strange. And I'm seeing the same issue on a second DM2 board -- so that pretty much rules out hardware, leaving HDL issues and timing issues. Process of elimination... fun. -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 148392
John Speth <johnspeth@yahoo.com> wrote: (snip) > I'm looking for an HDL replacement for sprintf() that will do a float to > string conversion using the "%.3E" format specification. Such a conversion > in C source code is laborius in code and hence time consuming. I need to > convert in about 20 usec on a NIOS on FPGA clocking at 100 MHz. 20us*100MHz=2000 clock cycles. Not so bad. > I'm guessing the best way to do it is to use some C code coupled with > various HDL modules to reduce the C processing load. Such a solution is > acceptable to me as long as I can meet my conversion time target. The best > solution would be all in HDL if possible. I prefer verilog but will take > anything that works. An IP purchase is better than trying to figure out > somthing that isn't finished or is academic but at this point anything I can > find is better than nothing. How big or small can the values be? Last I looked at such routines, they had a table of powers of 10 from 0 to 9 and from 10 to the largest floating point value by tens. In a loop, compare the input value, then divide (or multiply by the reciprocal) as appropriate, first the tens then the ones. After that, you have the appropriate exponent, and only need to convert the resulting value to decimal, still not so easy. Now, how much memory do you have available? Using the binary exponent and a small table should get you within a factor of 10, that is, within 1 of the correct decimal exponent. Then one compare using a table of powers of 10 and one multiply should get you the binary value to convert to decimal and apply the exponent. IEEE single has an eight bit binary exponent, double has 11 bits, so you would need a 256 by 24 or 2048 by 53 table, respectively. Well, maybe two tables, also one for the multplier. Now long does the multply take? Oh, you don't need so many decimal digits, though if you don't do the full precision some values might round the wrong way. Well, you can do the compare to full precision (to get the right exponent), but the multiply (to get the significand) at reduced precision. I think that works. -- glenArticle: 148393
On Fri, 16 Jul 2010 14:06:00 -0700, Tim Wescott wrote: >declaring both of the following: > >USE ieee.numeric_std.ALL; >use IEEE.STD_LOGIC_ARITH.ALL; > >gets me a flood of errors, although I seem to be able to comment out the >std_logic_arith. Right. The two packages are somewhat similar. For example they both define types SIGNED and UNSIGNED, and they both define "+" operators for those types. In VHDL, if you "use .all" some packages and more than one of the packages defines the same identifier, then the identifier is hidden to spare you the embarrassment of not knowing which one is being used. You can still reach it. For example, given your two USE clauses, you could do signal S8: SIGNED(7 downto 0); -- Error, SIGNED is hidden signal S8: ieee.numeric_std.SIGNED(7 downto 0); -- OK and, indeed, S8 <= S8 + 1; -- ERROR: "+" operator definition is hidden S8 <= ieee.numeric_std."+"(S8, 1); -- OK but I suspect you would agree with me that neither of these is a terribly good idea. It's nice that JustJohn showed us how to defeat the silly Xilinx default use clauses - thanks for the tip! -- Jonathan BromleyArticle: 148394
Hello All, I have a requirement to build a SOC design with two Arm cores along with some standard and custom peripherals. The Actel Cortex-M1 enabled FPGA's appear to be ideal for my application because the licensing fee is included in the price of the processor. I have started playing around with the Libero tools to see how processor development is done with them. The Libero environment comes with a tool called SmartDesign for assembling a processor system. It seems to work reasonably well for creating an initial system. You connect the pieces with a graphical editor and the tool outputs VHDL (or Verilog) for synthesis and simulation. Though fine for initial prototyping I do not like to use graphical tools to maintain a delivered design. It is just too likely that some glitch will block me from doing what I want. I prefer to enter and maintain the design at the HDL level with just a text editor and synthesis tool. I looked at the VHDL that comes out of SmartDesign and it is typical machine generated code. Just a bunch of block instantiations connected by meaningless signal names. Here comes my question. Using Actel tools can you work with the Arm/Amba processor IP directly in HDL? Is there a library of cores with documentation? Any comments are greatly appreciated. Best wishes, PeteArticle: 148395
On Sat, 17 Jul 2010 03:14:05 -0700 (PDT), Socrates <mailsoc@gmail.com> wrote: >> I had similar results. My thought was that it was a Java problem - >> different browsers typically have different ways of dealing with >> embedded Java. >> >> RK. > >If there is a such need, I could mirror the image somewhere. Because of copyright issues, it wouldn't be advisable for you to distribute Xilinx files without explicit permission. The best case would be for Xilinx to have multiple servers for their own files. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 148396
On Jul 16, 5:03=A0pm, JustJohn <justjohna...@gmail.com> wrote: > On Jul 16, 3:01=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > > > > > > > On 07/16/2010 02:24 PM, MM wrote: > > > > "Tim Wescott"<t...@seemywebsite.com> =A0wrote in message > > >news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d@web-ster.com... > > >> I seem to have a collision between libraries in my Xilinx ISE: > > > >> declaring both of the following: > > > >> USE ieee.numeric_std.ALL; > > >> use IEEE.STD_LOGIC_ARITH.ALL; > > > > These two libs should never be used together. The former is a standar= d > > > library, which should be used in new code, and the latter is a legacy > > > Synopsys library which might be required when working with the existi= ng > > > code. > > > Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when > > you get lazy and tell it to just make you a test bench from a file. > > > Thanks for the tip. > > > Tim Wescott > > Wescott Design Serviceshttp://www.wescottdesign.com > > > Do you need to implement control loops in software? > > "Applied Control Theory for Embedded Systems" was written for you. > > See details athttp://www.wescottdesign.com/actfes/actfes.html-Hide quot= ed text - > > > - Show quoted text - > > It used to frustrate me no end the way ISE plugged in the wrong > library, until I found the script that does it and CHANGED it. Look > under Xilinx=3D>ISE=3D>data=3D>projnav=3D>scripts and modify file > "dpm_sourceTasks.tcl" to your liking. TCL syntax is fairly basic in > the area you'll want to change. > delete: > =A0 puts $hFile "use IEEE.STD_LOGIC_ARITH.ALL;" > =A0 puts $hFile "use IEEE.STD_LOGIC_UNSIGNED.ALL;" > add: > =A0 puts $hFile "use ieee.numeric_std.all;" > > Customize to add your own name, company header, etc. > Hopefully they haven't changed the framework in version 12. > > HTH, > John- Hide quoted text - > > - Show quoted text - Umm, the tcl file I listed above is for regular vhdl modules. For testbenches, the tcl'er is: Xilinx->ver->ISE->data->testbnch2.tclArticle: 148397
Hi All I am implementing an I2C slave and low level interface to interface it to EEPROM. I am using I2c Master for verifying this module . The I2C Master code is reused from some other module. He has implemented the I2C in a fashion that the PULL up and the Pull Down is to be provided from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some other control signals. It doesnot generate a start and stop condition inside i2c master block. I have seen the code it waits for the SDA to go from LOW to HIGH .My question is 1. in I2C master do we have to make a separate module in verilog ( the code is in verilog) to generate start and stop condition. or it is expected to have this functionality inside the I2C master controller. 2. How do I connect for verifying the slave and the Interface . The SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and stop generation /detection module as it is not inside the controller has to be connected from outside. Will the START gen module just send SCL and SDA to I2c Master for start operation and the the master will take from there. 3. In the initial state when it is reset under normal protocol situation the SCL is Z and the SDA is Z both pulled up . To start the operation for a start gen condition is there a separate module to do so .How normally in I2C master it is done( someone who has already done it. 4. I have gone througn the standard but got confused as how the first start and stop condition is generated and who will toggle the first SDA low to high. I have googled also and looked for some reference designs but it is not running well in sumulation to understand how the first start operation is gereated as the slave is IDLE and waiting for the start signal from the master. I would highly appreciate any suggestions on this issue. Thanks in advance VipulArticle: 148398
On 7/16/2010 8:07 PM, Tim Wescott wrote: > How do I assign an integer value to 'signed' or 'unsigned' from the IEEE > libraries? > > I'm having this difficulty with my test benches. Surely there's a set of > library functions to do it, but I can't seem to figure out what they are!! > http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdfArticle: 148399
Tried to install ISE 12.x Webpack for supporting a customer. After 6 hours of downloading, installing and cleaning up HDD space i made a small mistake in the first install process to obtain a license. After rebooting, when i select the "obtain license key" tab in the ISE12 HELP, a connection to the xilinx web page fails with "Oops! This page appears broken" Going back one step in the IE to xilinx.com again, there is only a 1 month ISE license selected, other input requirements as host name etc. is not selectable, a whole SHIT. There is no button to get anything. Support for one customer failed completely because of LICENSE BS, now i'm too late to resume, must drive to another customer. I'm really pissed off. MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z