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Michael S schrieb: > > Anyway, the discussion doesn't belong here. I recommend > http://groups.google.com/group/microsoft.public.development.device.drivers > No it doesn't. It belongs just where it is. If you followed from the beginning, the OP has two problems/questions 1) How to do 64-Bit addressing in PCIe. This is definitely FPGA related. 2) Why are his data not appearing as expected. It only became clear in the course of discussion that this may be due to his driver DMA type setting. (He hasn't confirmed yet) Nit-picking when everything is (maybe) solved is easy when you haven't really been contributing constructively.Article: 148276
On Jul 4, 2:01=A0am, Charles Gardiner <charles.gardi...@invalid.invalid> wrote: > Michael S schrieb: > > > > > Anyway, the discussion doesn't belong here. I recommend > >http://groups.google.com/group/microsoft.public.development.device.dr... > > No it doesn't. It belongs just where it is. If you followed from the begi= nning, > the OP has two problems/questions > I insist that subthread started by Nico Coesel could be discussed in mpddd with better depth and precision. > 1) How to do 64-Bit addressing in PCIe. This is definitely FPGA related. You mean, 32-bit addressing. > > 2) Why are his data not appearing as expected. It only became clear in th= e course > of discussion that this may be due to his driver DMA type setting. (He ha= sn't > confirmed yet) Microsoft calls them "data buffer access methods". DMA type (or, by KMDF terminology, profile) is something else. I hope you realize how important it is to use the same terminology as the rest of the world. http://msdn.microsoft.com/en-us/library/ff554436%28v=3DVS.85%29.aspx > > Nit-picking when everything is (maybe) solved is easy when you haven't re= ally been > =A0contributing constructively. If you followed from the beginning, you would realize that I constructively contributed the answer to the first question 4 minutes ahead of you ;) Also, IMHO, pointer to the most appropriate newsgroup is very constructive.Article: 148277
Avnet is sole disti for Xilinx, now lets see what Avnet says: searching for Spartan-6 all items are no stock, with notice factory leadtime 16 weeks but some items have extra note, "stock in asia" good this means there is stock? but what does the "stock in asia" link do? it opens a popup window saying: no stock, factory leadtime 143 weeks! 143 weeks leadtime on spartan-6? should we all smile or cry? AnttiArticle: 148278
Michael S schrieb: > I insist that subthread started by Nico Coesel could be discussed in > mpddd with better depth and precision. > You insist? Do I care? > > If you followed from the beginning, you would realize that I > constructively contributed the answer to the first question 4 minutes > ahead of you ;) 4 mins.? WOW. Incredible. Impressive, Awesome..... What I see in this posting is a terse reply to the easy part of the problem with not a single thought spent on the more complex part, even though this is really the OPs show stopper. For the rest of your postings, I mainly see blowholed personal seals of approval assigned to what others have said (aka nit-picking). All coming in "posthumously" (still assuming that specifying DO_DIRECT_IO actually solves the problem) I really love attending meetings when guys like you are involved, especially in the last phase when those who havn't contributed much insist on getting a chance to lift their leg. The german comedian Karl Valentin had perhaps a more literary way of putting it: "I suppose everything has been said then, but not yet by everybody". Oh, don't take my personal aversion too much to heart. I'm sure somebody on this planet recognises your contribution, even if it's only DilbertArticle: 148279
It's even better when that 143 week lead time comes through as a formal quote. I have a number of Jan2013 delivery quotations. I'm sure it's not as bad as that but the people on the ground at Avnet think but they do go by their system quoted leadtimes. Meanwhile I will announce a new Spartan-6 board later this week. We have a limited supply of silicon sold to me by Nuho when they were still franchaise but after that I guess it's maybe a wait until 2013. John Adair Enterpoint Ltd. On 4 July, 10:18, Antti <antti.luk...@googlemail.com> wrote: > Avnet is sole disti for Xilinx, now lets see what Avnet says: > > searching for Spartan-6 > all items are no stock, with notice factory leadtime 16 weeks > but some items have extra note, "stock in asia" > good this means there is stock? > but what does the "stock in asia" link do? > > it opens a popup window saying: no stock, > factory leadtime 143 weeks! > > 143 weeks leadtime on spartan-6? > > should we all smile or cry? > > AnttiArticle: 148280
On Jul 4, 11:59=A0am, Charles Gardiner <charles.gardi...@invalid.invalid> wrote: > Michael S schrieb: > > > I insist that subthread started by Nico Coesel could be discussed =A0in > > mpddd with better depth and precision. > > You insist? Do I care? > > > If you followed from the beginning, you would realize that I > > constructively contributed the answer to the first question 4 minutes > > ahead of you ;) > > 4 mins.? WOW. Incredible. Impressive, Awesome..... > > What I see in this posting is a terse reply to the easy part of the probl= em with > not a single thought spent on the more complex part, even though this is = really > the OPs show stopper. > > For the rest of your postings, I mainly see blowholed personal seals of a= pproval > assigned to what others have said (aka nit-picking). All coming in "posth= umously" > (still assuming that specifying DO_DIRECT_IO actually solves the problem) And I am 90% sure that 3DW was his only problem. The following sentence in his original post suggests that he doesn't use BUFFERED_IO: "The driver locks the memory". For me it sounds like he is doing NEITHER I/O. So it's either 3DW or, less likely, he erroneously too early completes his ReadFile() request. > > I really love attending meetings when guys like you are involved, especia= lly in > the last phase when those who havn't contributed much insist on getting a= chance > to lift their leg. The german comedian Karl Valentin had perhaps a more l= iterary > way of putting it: "I suppose everything has been said then, but not yet = by > everybody". > > Oh, don't take my personal aversion too much to heart. I'm sure somebody = on this > planet recognises your contribution, even if it's only Dilbert You are wrong. I never really was obsessed with getting the credit. More like obsessed with precise formulations, although more so in real life than on the Web. Also I am one of those types that don't like to quickly jump to conclusion.Article: 148281
Antti wrote: > Avnet is sole disti for Xilinx, now lets see what Avnet says: > > searching for Spartan-6 > all items are no stock, with notice factory leadtime 16 weeks > but some items have extra note, "stock in asia" > good this means there is stock? > but what does the "stock in asia" link do? > > it opens a popup window saying: no stock, > factory leadtime 143 weeks! > > 143 weeks leadtime on spartan-6? > > should we all smile or cry? Switch to Altera. I've never heard of delivery problems for the Cyclone 2, which a customer is still using for a product which I helped to program. Even for the latest Cyclone 4 there are already some chips available in the Altera online shop. For the Cyclone 3 device there are hundreds of each type in stock. Digikey, Farnell and other distributors have it in stock, too. 16 weeks should be enough time for changing a design from one vendor to the other, if you didn't use special features which are not available in the other FPGA. And in the end you'll have a more FPGA independant design, if you need to change it again :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 148282
Antti <antti.lukats@googlemail.com> wrote: > Avnet is sole disti for Xilinx, now lets see what Avnet says: > searching for Spartan-6 > all items are no stock, with notice factory leadtime 16 weeks > but some items have extra note, "stock in asia" > good this means there is stock? > but what does the "stock in asia" link do? > it opens a popup window saying: no stock, > factory leadtime 143 weeks! > 143 weeks leadtime on spartan-6? Digikey now also has 251 XC6SLX items. All not on stock, but must parts scheduled around mid of august . -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148283
On some these they will come back and say order book isn't open. That's what happened to me. I placed a pile of orders this way when this list appeared mid-week as a emergency way to get silicon and an alternative to Avnet. However I suspect, given what I have seen, that they will meet these dates but you never know/ John Adair Enterpoint Ltd. On 4 July, 12:29, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Antti <antti.luk...@googlemail.com> wrote: > > Avnet is sole disti for Xilinx, now lets see what Avnet says: > > searching for Spartan-6 > > all items are no stock, with notice factory leadtime 16 weeks > > but some items have extra note, "stock in asia" > > good this means there is stock? > > but what does the "stock in asia" link do? > > it opens a popup window saying: no stock, > > factory leadtime 143 weeks! > > 143 weeks leadtime on spartan-6? > > Digikey now also =A0has 251 XC6SLX items. All not on stock, but must part= s > scheduled around mid of august . > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148284
I'm looking for Xilinx Foundation 3.1i or XACT 5 or 6 because I want to use XC3000 FPGA. I know, that chips are very old but I don't want scrap it. Maybe someone has copy? Thanks KrzychArticle: 148285
On Jul 4, 5:18=A0am, Antti <antti.luk...@googlemail.com> wrote: > Avnet is sole disti for Xilinx, now lets see what Avnet says: > > searching for Spartan-6 > all items are no stock, with notice factory leadtime 16 weeks > but some items have extra note, "stock in asia" > good this means there is stock? > but what does the "stock in asia" link do? > > it opens a popup window saying: no stock, > factory leadtime 143 weeks! > > 143 weeks leadtime on spartan-6? > > should we all smile or cry? > > Antti What's the lead time for Spartan 5 parts? Or how about Altera or Lattice parts? Why look for trouble? RickArticle: 148286
rickman <gnuarm@gmail.com> wrote: (snip) > What's the lead time for Spartan 5 parts? Or how about Altera or > Lattice parts? Why look for trouble? I believe the lead time for Spartan 5, as with Spartan 4, is much longer, likely approaching infinity. Spartan 6 does have some interesting new features previously only in Virtex devices. -- glenArticle: 148287
I'm trying to see the difference from an external point of view, and I can't see one, apart from having a 1.8V supply rather than a 2.5V. I can see increased clock speed and increased clock latency, but that's about it I am aware the internal clock runs at half main clock, and that the burst order in interleaved data is different, but on the surface I should be able to use a DDR controller to access DDR2. Where am I going wrong?Article: 148288
I have used DDR2 but not DDR but I am fairly sure that the init seq is different. I wouldnt be surprised if there are different timings and burst types too. Because of the faster timings on DDR2 some form of read calibration would be needed. So you could probably modify a DDR controller but using it straight out of the box is not possible. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148289
I think the problem is that if people want the very latest and greatest tech they need to put up with long lead times and bugs in the development software. Personally I would wait until these things are resolved and just use a slightly older techology. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148290
On Jul 5, 2:37=A0am, rickman <gnu...@gmail.com> wrote: > > What's the lead time for Spartan 5 parts? =A0 Don't you mean Spartan 3E? > Or how about Altera or > Lattice parts? =A0Why look for trouble? > > Rick Don't know about Lattice. As to Altera, Spartan 6 has many features not available in Cyclone2/3. Lead time for Cyclone IV is probably not much shorter than for Spartan 6. Also, Spartan 6 is both build on more modern silicon process and has more advanced LUT architecture than even Cyclone IV, so, in theory, it should be faster. Of course, there is Arria II GX that easily matches (and beats) Spartan 6 feature4feature and MHz4Mhz. It is even sort of available, at least some parts. However, Arria II GX is more like mid-cost device rather than low-cost.Article: 148291
Gladys <yuhui.b@gmail.com> writes: > Sorry, for the 2nd question, I just forgot that I can use Lool Up > Table, just use CASE statement to implement this. > So the only problem is how can I access the location data from SPI > flash, since these data should be always available for bad pixel > correction while FPGA running. If you use a BRAM to store the data, you can arrange to have it initialised by the bitstream, so you don't need to do that. This means a new bitstream for each set of bad pixels though, so that might not work out in your application! In which case, you need to write a small peripheral, or use a small microcontroller core in the FPGA to read the data from the SPI flash (once, at startup) into a BRAM internally. Then you can use that data to feed to your dead-pixel corrector. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 148292
On Jul 5, 12:49=A0pm, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I think the problem is that if people want the very latest and greatest > tech they need to put up with long lead times and bugs in the development > software. Personally I would wait until these things are resolved and jus= t > use a slightly older techology. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Around 10/2009 we were forced by our customer to work with Stratix IV GX. What a nightmare! Until Quartus9.1 SP1 pretty much nothing worked as expected. Were we starting the same project around 03/2010 it would be walk in the park.Article: 148293
On 5 July, 11:45, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I have used DDR2 but not DDR but I am fairly sure that the init seq is > different. I wouldnt be surprised if there are different timings and burs= t > types too. Because of the faster timings on DDR2 some form of read > calibration would be needed. So you could probably modify a DDR controlle= r > but using it straight out of the box is not possible. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I have control over the initialisation sequence so that should not be an issue. I also have control over the clock and strobe timings as well. You haven't outlined any show-stoppers that I might have expected. Many thanks for your view.Article: 148294
On Jul 4, 11:31=A0am, Krzych <kb...@wp.pl> wrote: > I'm looking for Xilinx Foundation 3.1i or XACT 5 or 6 because I want > to use XC3000 FPGA. I know, that chips are very old but I don't want > scrap it. > > Maybe someone has copy? > > Thanks > Krzych There are a number of discussions about using antique FPGA parts in this Usenet group. Search for "antique Xilinx", "XACT", or "Hitting yourself on the head with a mallet". Consensus is that it is less expensive to recycle those parts (properly) and then design & build an adapter that allows a cool- runner to fit in the socket than it is to program one of them. Cheers, RKArticle: 148295
On 5 Lip, 18:24, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Jul 4, 11:31=A0am, Krzych <kb...@wp.pl> wrote: > > > I'm looking for Xilinx Foundation 3.1i or XACT 5 or 6 because I want > > to use XC3000 FPGA. I know, that chips are very old but I don't want > > scrap it. > > > Maybe someone has copy? > > > Thanks > > Krzych > > There are a number of discussions about using antique FPGA parts in > this Usenet group. > > Search for "antique Xilinx", "XACT", or "Hitting yourself on the head > with a mallet". > > Consensus is that it is less expensive to recycle those parts > (properly) and then design & build an adapter that allows a cool- > runner to fit in the socket than it is to program one of them. > > Cheers, > RK Thank you, maybe you are rigth, the best wayt is to scrap it and replace with new one. Thanks KrzychArticle: 148296
On Jul 5, 8:21=A0am, Fred <fred__blo...@lycos.com> wrote: > On 5 July, 11:45, "maxascent" > > <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > > I have used DDR2 but not DDR but I am fairly sure that the init seq is > > different. I wouldnt be surprised if there are different timings and bu= rst > > types too. Because of the faster timings on DDR2 some form of read > > calibration would be needed. So you could probably modify a DDR control= ler > > but using it straight out of the box is not possible. > > > Jon =A0 =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > I have control over the initialisation sequence so that should not be > an issue. I also have control over the clock and strobe timings as > well. > > You haven't outlined any show-stoppers that I might have expected. > > Many thanks for your view. I think you may be able to configure the DQS as single-ended, but normally DDR2 uses differential DQS signals. Also on-die termination was added in DDR2, this requires an extra signal if you use it. The start-up sequences are different and the DDR2 has more mode registers. Regards, GaborArticle: 148297
On Jul 5, 6:57=A0am, Michael S <already5cho...@yahoo.com> wrote: > On Jul 5, 2:37=A0am, rickman <gnu...@gmail.com> wrote: > > > > > What's the lead time for Spartan 5 parts? =A0 > > Don't you mean Spartan 3E? > > > Or how about Altera or > > Lattice parts? =A0Why look for trouble? > > > Rick > > Don't know about Lattice. > > As to Altera, Spartan 6 has many features not available in Cyclone2/3. > Lead time for Cyclone IV is probably not much shorter than for Spartan > 6. Also, Spartan 6 is both build on more modern silicon process and > has more advanced LUT architecture than even Cyclone IV, so, in > theory, it should be faster. > Of course, there is Arria II GX that easily matches (and beats) > Spartan 6 feature4feature and MHz4Mhz. It is even sort of available, > at least some parts. However, Arria II GX is more like mid-cost device > rather than low-cost. Lattice has a policy of build first and then announce. It makes customers much happier. It also occasionally blindsides the competition. They may not have all sizes and footprints of a new series when announced, but you can be sure that SOME silicon is available, not just smoke and mirrors.Article: 148298
Hi all,
I just came across a - what I think - must be a quite standard
programming idiom for implementing an FSM. Essentially, I read
a byte value byte_in sequentially, and assign it to the appropriate
portions of signal register. As you can see, the read_en signal
must be HIGH in the state before the data in byte_in can be read.
Unfortunately, my FSM looks messy and I wonder if I could compress
the states a bit.
signal read_en : std_logic;
signal byte_in : std_logic_vector(7 downto 0);
signal register : std_logic_vector(31 downto 0);
process (clk, reset)
begin
if (clk'event and clk = '1') then
case state is
when READ0 =>
read_en <= 1;
state = READ1;
when READ1 =>
read_en <= 1;
register(7 downto 0) <= byte_in;
state = READ2;
when READ2 =>
read_en <= 1;
register(15 downto 8) <= byte_in;
state = READ3;
when READ3 =>
read_en <= 1;
register(23 downto 16) <= byte_in;
state = READ4;
when READ4 =>
register(31 downto 24) <= byte_in;
state = DONE;
end case;
end process;
Many thanks for your comments,
Rich
Article: 148299John, Thanks for your patience. I have been in contact with your FAE, and he now has the document. If he hasn't gotten it to you within a day or two, please let me know. Bryan
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